To Same Side Of Substrate Patents (Class 438/750)
  • Patent number: 9762323
    Abstract: A method (1200) of transmitting digital information via a nonlinear optical channel (722), comprises receiving (1202) data (702) comprising at least a portion of the digital information. A plurality of frequency domain symbols is generated (1204) from the data, and each symbol is assigned to one of a predetermined plural number of frequency sub-bands. Each sub-band may be processed separately (1206) to reduce a peak-to-average power ratio (PAPR) of a transmitted optical signal. The optical signal (12) is then generated (1208) comprising the plural number of sub-bands, and transmitted via the nonlinear optical channel (722). The plural number of frequency sub-bands is predetermined so as to reduce nonlinear optical distortion of the optical signal within the nonlinear optical channel relative to a corresponding single frequency band signal. A corresponding information-receiving method, a transmitter apparatus and a receiver apparatus are also disclosed.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 12, 2017
    Assignee: Ofidium Pty. Ltd.
    Inventor: William Shieh
  • Patent number: 9698121
    Abstract: A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Jing-Cheng Lin
  • Patent number: 9340761
    Abstract: A substrate processing method includes an SPM supplying step of supplying SPM having high temperature to an upper surface of a substrate, a DIW supplying step of supplying, after the SPM supplying step, DIW having room temperature to the upper surface of the substrate to rinse off a liquid remaining on the substrate, and a hydrogen peroxide water supplying step of supplying, after the SPM supplying step and before the DIW supplying step, hydrogen peroxide water of a liquid temperature lower than the temperature of the SPM and not less than room temperature, to the upper surface of the substrate in a state where the SPM remains on the substrate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 17, 2016
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Sei Negoro, Ryo Muramoto, Yasuhiko Nagai, Tsutomu Osuka, Keiji Iwata
  • Patent number: 9029268
    Abstract: Processes are described to etch metals. In an embodiment, a process may include contacting a substrate with a stripping solution to remove photoresist from the substrate to produce a stripped substrate. The stripped substrate may include a plurality of solder pillars and a plurality of metal-containing field regions disposed around the plurality of solder pillars. In an illustrative embodiment, the plurality field regions may include copper. Additionally, the process may include rinsing the stripped substrate to produce a rinsed substrate. The rinsed substrate may be substantially free of a Sn layer or a Sn oxide layer. Further, the process may include contacting the rinsed substrate with an etch solution that is capable of removing an amount of one or more metals from the plurality of field regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Dynaloy, LLC
    Inventors: Richard Dalton Peters, Travis Acra, Spencer Erich Hochstetler, Kimberly Dona Pollard
  • Patent number: 9023735
    Abstract: An etchant composition includes ammonium persulfate (((NH4)2)S2O8), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bong-Kyun Kim, Hong Sick Park, Wang Woo Lee, Young Min Moon, Seung Ho Yoon, Young Joo Choi, Sang-Woo Kim, Ki-Beom Lee, Dae-Woo Lee, Sam-Young Cho
  • Patent number: 9005464
    Abstract: A tool and method is provided for mixing multiple components and feeding a single blend of the multiple components into the tool. The method includes adjusting a concentration of etchant solution. The method includes determining an etch target for each batch of wafers of a plurality of batches of wafers entering an etch chamber of a wafer processing tool. The method further includes adjusting a concentration of 40% NH4F to 49% HF for the each batch of wafers of the plurality of batches of wafers entering the wafer processing tool during a single run.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Russell H. Arndt, David F. Hilscher
  • Patent number: 8969216
    Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: March 3, 2015
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Victor Prajapati, Joachim John
  • Patent number: 8951430
    Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Matthew T. Dejarld, Jae Cheol Shin, Winston Chern
  • Patent number: 8951901
    Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Patent number: 8945952
    Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 3, 2015
    Assignee: Intermolecular, Inc.
    Inventor: John Foster
  • Patent number: 8900478
    Abstract: Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 2, 2014
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Akira Hosomi, Kensuke Ohmae
  • Patent number: 8894867
    Abstract: Disclosed is a method for producing ZnO contact layers for solar cells. The layers are etched using hydrofluoric acid so as to generate a texture.
    Type: Grant
    Filed: August 7, 2010
    Date of Patent: November 25, 2014
    Assignee: Forschungszentrum Juelich GmbH
    Inventors: Eerke Bunte, Jorj Owen, Juergen Huepkes
  • Patent number: 8835210
    Abstract: The present invention reduces the time required to manufacture a solar cell. After etching main surfaces (10B1, 10B2) of a crystalline silicon substrate (10B) using one etching solution, the main surfaces (10B1, 10B2) of the crystalline silicon substrate (10B) are etched at a lower etching rate than the etching performed using the one etching solution by using another etching solution that has a higher concentration of etching components than the one etching solution. In this way, a textured structure is formed in the main surfaces (10B1, 10B2) of the crystalline silicon substrate (10B).
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 16, 2014
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takuo Nakai, Naoki Yoshimura, Masaki Shima
  • Publication number: 20140256151
    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
  • Patent number: 8822346
    Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Kurt Weiner
  • Patent number: 8778802
    Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Dai Fukushima, Gaku Minamihaba, Hiroyuki Yano
  • Patent number: 8759231
    Abstract: The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. Processes for texturing a crystalline silicon substrate using these formulations are also described.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: June 24, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-Wen Sun, Sagar Vijay
  • Patent number: 8759219
    Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 24, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ya-Hsueh Hsieh, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao
  • Patent number: 8759230
    Abstract: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Michael Melzl, Josef Schwaiger, Thilo Stache
  • Patent number: 8741168
    Abstract: According to one embodiment, an etching method includes: supplying an etching-resistant material; and etching the silicon nitride film. The supplying includes supplying the etching-resistant material to a processing surface including a surface of a silicon nitride film and a surface of a non-etching film, the non-etching film including a material different from the silicon nitride film. The etching includes etching the silicon nitride film using an etchant in a state of the etching-resistant material being formed relatively more densely on the surface of the non-etching film than on the surface of the silicon nitride film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Yoshimizu, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 8703509
    Abstract: A method for manufacturing a substrate for liquid-ejecting heads includes etching a surface of a silicon substrate using a first etchant, with a silicon oxide layer as a mask, to form a depression as a part of a liquid supply port, and subsequently etching at least the silicon oxide layer and the thickness sandwiched between the depression and the etched surface of the silicon substrate with a second etchant to form the liquid supply port.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Abo, Keiji Watanabe, Keiji Matsumoto
  • Patent number: 8641913
    Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: February 4, 2014
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Yoichi Kubota, Teck-Gyu Kang, Jae M. Park
  • Patent number: 8618000
    Abstract: Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Prashant Raghu, Yi Yang
  • Patent number: 8609550
    Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: December 17, 2013
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 8603837
    Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 10, 2013
    Assignee: Intermolecular, Inc.
    Inventor: John Foster
  • Patent number: 8580126
    Abstract: An exemplary method for a producing a piezoelectric vibrating piece having at least one mesa step includes forming a metal film on a main surface of a piezoelectric wafer. A through-groove is formed through the thickness of the wafer to form a plan profile of a desired piezoelectric substrate. A film of photoresist is formed on the surface of the metal film. A resist is applied, exposed, and formed into a resist pattern that defines a first mesa step along at least a portion of the plan profile. In regions not protected by the metal film, the piezoelectric substrate is etched to a defined depth to form a mesa step. The denuded edge surface of the metal film is edge-etched. A second mesa step, inboard of the first mesa step, can be formed by repeating the edge-etching and substrate-etching steps using the metal film as an etch protective film.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 12, 2013
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Hiroyuki Sasaki, Kenji Shimao, Manabu Ishikawa
  • Patent number: 8563441
    Abstract: Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 22, 2013
    Assignee: Spansion LLC
    Inventors: Yi Ma, Robert Bertram Ogle
  • Patent number: 8530359
    Abstract: An apparatus for wet etching metal from a semiconductor wafer comprises a wafer holder for rotating a wafer and a plurality of nozzles for applying separate flow patterns of etching liquid to the surface of the wafer. The flow patterns impact the wafer in distinct band-like impact zones. The flow pattern of etching liquid from at least one nozzle is modulated during a total etching time control the cumulative etching rate in one local etch region relative to the cumulative etching rate in one or more other local etch regions. Some embodiments include a lower etch chamber and an upper rinse chamber separated by a horizontal splash shield. Some embodiments include a retractable vertical splash shield used to prevent splashing of etching liquid onto the inside walls of a treatment container. An etch-liquid delivery system includes a plurality of nozzle flow paths having corresponding nozzle flow resistances, and a plurality of drain flow paths having corresponding drain flow resistances.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: September 10, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter
  • Patent number: 8435904
    Abstract: A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having the at least one cavity or more than one density or strain is exposed to a gaseous mixture of NH3 and HF and heated, to substantially uniformly remove the silicon oxide. A method of removing an exposed sacrificial layer without substantially removing exposed isolation regions using the gaseous mixture of NH3 and HF and heat is also disclosed, as is an intermediate semiconductor device structure that includes a semiconductor substrate, a sacrificial layer overlying the semiconductor substrate, a diffusion barrier overlying the sacrificial layer, and exposed isolation regions.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 7, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, Joseph N. Greeley
  • Patent number: 8419953
    Abstract: A method for fabricating a transducer on a substrate is described. The transducer includes an antiferromagnetic seed structure. The antiferromagnetic seed structure includes a first NiFe layer, a first multilayer including a first Ru layer, a second NiFe layer, and a second multilayer including a second Ru layer. The second multilayer, the second NiFe layer and part of the first Ru layer are removed using a first wet etch, which uses a first etchant combination to remove NiFe and in which Ru is insoluble. The second Ru layer is removed through lift-off due to etching of the second NiFe layer. A remainder of the first Ru layer is removed through a second wet etch, which uses a second etchant combination to remove Ru. A remaining portion of the first multilayer and the first NiFe layer are removed through a third etch, which uses a third etchant combination that removes NiFe.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 16, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Wencheng Su, Zhigang Zhou, Jane Ang, Ming Jiang
  • Patent number: 8398877
    Abstract: A method is provided for forming an opening in a layer of a selected material. The method comprises, forming a polymer resist layer over said selected material and plasticising areas of the resist where openings are to be formed. The plasticising is performed by depositing a first solution onto the surface of said polymer resist layer, where the first solution is a plasticiser selected to increase permeability of the polymer resist layer to a second solution, in an area which has absorbed the first solution. The second solution is selected to be an etchant or solvent for the selected material. After the resist layer has been selectively plasticised, it is contacted with the second solution, which permeates the polymer resist layer in the area of increased permeability and forms an opening in the selected material.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: March 19, 2013
    Assignee: Newsouth Innovations Pty Ltd.
    Inventors: Stuart Ross Wenham, Alison Lennon, Roland Yudadibrata Utama, Anita Wing Yi Ho-Baillie
  • Patent number: 8389418
    Abstract: The present disclosure relates to a solution for selectively removing metal, such as Ta or TaN, from a substrate, such as an aluminum containing substrate. The solution comprises an acid, such as HF or buffered HF, an ingredient comprising a fluorine ion, such as ammonium fluoride (NH4F), ethylene glycol, and water. A method of selectively removing metal from a substrate using this solution is also disclosed.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: March 5, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jeremy W. Epton, John Deem
  • Patent number: 8372757
    Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: February 12, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Eric Webb, David W. Porter
  • Patent number: 8318607
    Abstract: A method of performing a single step/single solvent edge bead removal (EBR) process on a photolithography layer stack including a photoresist layer and a top coat layer using propylene glycol monomethyl ether acetate (PGMEA) or a mixture of PGMEA and gamma-butyrolactone (GBL) is disclosed. The single step/single solvent EBR process is compatible with organic and inorganic BARC layers.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 27, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Benjamen Michael Rathsack, Mark Howell Somervell
  • Patent number: 8303723
    Abstract: In a liquid processing apparatus configured to remove, from a substrate including a first film and a second film formed above the first film, the first film and the second film, a first chemical-liquid supply part supplies, to a substrate W, a first liquid for dissolving the first film, a second chemical-liquid supply part supplies a second chemical liquid for weakening the second film, and a fluid supply part serving also as an impact giving part gives a physical impact to the second film so as to break the second film and supplies a fluid for washing away debris of the broken second film. A control device controls the respective parts such that, after the second liquid has been supplied and then the fluid has been supplied from the fluid supply part, the first chemical liquid is supplied.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: November 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Teruomi Minami, Fumihiro Kamimura, Kazuki Kosai, Takashi Yabuta, Kenji Yokomizo, Shogo Mizota
  • Patent number: 8293129
    Abstract: A manufacturing method of the present invention comprises the step of epitaxially growing a PZT layer on a first electrode layer, and the step of processing the PZT layer to a desired shape using an etching solution after the growing step. The etching solution contains at least one acid from among hydrochloric acid and nitric acid in a concentration CHCl+3.3CHNO3 ranging from 1 wt % to 10 wt %, CHCl and CHNO3 denoting, respectively, a weight concentration of the hydrochloric acid and nitric acid relative to a weight of the etching solution; and at least one fluorine compound from among ammonium fluoride and hydrogen fluoride, such that a weight concentration of fluorine derived from ammonium fluoride and hydrogen fluoride ranges from 0.1 wt % to 1 wt % relative to the weight of the etching solution.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 23, 2012
    Assignees: TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Katsuyuki Kurachi, Hirofumi Sasaki
  • Patent number: 8288291
    Abstract: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 ?m×2 ?m) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: October 16, 2012
    Assignee: IMEC
    Inventors: Sonja Sioncke, Marc Meuris
  • Patent number: 8283258
    Abstract: Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Prashant Raghu, Yi Yang
  • Patent number: 8283257
    Abstract: Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition different than the first. Prior to rinsing the portion of the workpiece surface, the portion is sequentially exposed to the first and second chemistries again. The first and second chemistries are removed from the portion, and, after sequentially exposing the portion to each of the first and second chemistries at least twice, and removing the first and second chemistries, the portion is rinsed and dried.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Michael Andreas
  • Patent number: 8236704
    Abstract: An etchant includes hydrogen peroxide (H2O2), and a mixed solution including at least one of an organic acid, an inorganic acid, and a neutral salt.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: August 7, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Gyoo-Chul Jo, Ki-Sung Chae
  • Publication number: 20120190209
    Abstract: Disclosed is a method for producing ZnO contact layers for solar cells. The layers are etched using hydrofluoric acid so as to generate a texture.
    Type: Application
    Filed: August 7, 2010
    Publication date: July 26, 2012
    Inventors: Eerke Bunte, Jorj Owen, Juergen Huepkes
  • Patent number: 8222118
    Abstract: A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Mark Dydyk, Arturo Urquiza, Charles Singleton, Tim McIntosh
  • Patent number: 8158465
    Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: April 17, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
  • Patent number: 8124535
    Abstract: A method of fabricating a solar cell is provided. A saw damage removal process is performed on a silicon substrate. A dry surface treatment is performed to a surface of the silicon substrate on form an irregular surface. A metal-activated selective oxidation is performed to the irregular surface. By using an aqueous solution, the irregular surface is etched to form a nanotexturized surface of the silicon substrate. A dopant diffusion process is performed on the silicon substrate to form a P-N junction. An anti-reflection layer is formed on the silicon substrate. An electrode is formed on the silicon substrate.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Hsi Lin, Chien-Rong Huang, Dimitre Zahariev Dimitrov
  • Patent number: 8053371
    Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: November 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
  • Publication number: 20110215441
    Abstract: The present invention provides silicon nanostructures and their producing method. By employing a metal-assisted chemical etching method, the bottom of the produced silicon nanostructures, connected to the silicon substrate, is porous and side etched, such that the silicon nanostructures can be easily transferred to a hetero-substrate by a physical manner.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 8, 2011
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: CHING-FUH LIN, SHU-JIA SYU
  • Patent number: 7993452
    Abstract: A role of a bottom face of a silicon wafer is identified in a manufacturing process of the silicon wafer. And preferable characteristic feature is also identified. In order to obtain the above characteristic feature, a process method to be implemented into the method of manufacturing a normal silicon wafer is provided. For example, the method comprises: a pre-cleaning process for cleaning the silicon wafer having top and bottom faces processed to a mirror finish; and a rapid thermal process or an epitaxial growth process, wherein the pre-cleaning process comprises a hydrofluoric acid (HF) process and a subsequent pure water (DIW) process.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Koichiro Hayashida, Kazuhiro Narahara, Hirotaka Kato
  • Publication number: 20110143550
    Abstract: A method for manufacturing a semiconductor device, including: partially removing a first layer formed on a wafer supported by a support member by supplying a first liquid at a temperature of 60 degrees C. or higher over the wafer (step S1); cooling the wafer after the partially removing the first layer (step S2); and removing the remaining portions of the first layer by supplying the first liquid at a temperature of 60 degrees C. or higher over the wafer after the cooling the wafer, the remaining portions of the first layer being remained after the partially removing the first layer (step S3).
    Type: Application
    Filed: December 16, 2010
    Publication date: June 16, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunsuke SAITO
  • Patent number: 7943526
    Abstract: The present invention relates in general terms to the treatment or processing of substrate surfaces. In particular, the invention relates to processes for modifying the surface of silicon wafers.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: May 17, 2011
    Assignee: Rena Sondermaschinen GmbH
    Inventor: Franck Delahaye
  • Patent number: 7935642
    Abstract: A method for calculating the amount of solution components to add to an advanced coating removal (ACR) stripping solution in a coating removal stripping bath to replenish and recover stripping potential. The stripping effectiveness may be restored by the addition of only the primary acid of the composition of acids of the stripping bath and fresh water, in an amount necessary to restore the stripping solution to its original density.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: May 3, 2011
    Assignee: General Electric Company
    Inventors: Lawrence B. Kool, Gabriel K. Ofori-Okai