Sequential Application Of Etchant Patents (Class 438/749)
  • Patent number: 9214468
    Abstract: A semiconductor device and a method for fabricating the same are provided to enable a bit line to be formed easily, increase a bit line process margin and reduce capacitance between the adjacent bit lines. The semiconductor device comprises: a first pillar and a second pillar each extended vertically from a semiconductor substrate and including a vertical channel region; a first bit line located in the lower portion of the vertical channel region inside the first pillar and the second pillar; and an interlayer insulating film located between the first pillar and the second pillar that include the first bit line.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 15, 2015
    Assignee: HYNIX SEMICONDUCTOR INC.
    Inventor: Seung Hwan Kim
  • Patent number: 9142488
    Abstract: A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas, Tuan A. Vo
  • Patent number: 9029268
    Abstract: Processes are described to etch metals. In an embodiment, a process may include contacting a substrate with a stripping solution to remove photoresist from the substrate to produce a stripped substrate. The stripped substrate may include a plurality of solder pillars and a plurality of metal-containing field regions disposed around the plurality of solder pillars. In an illustrative embodiment, the plurality field regions may include copper. Additionally, the process may include rinsing the stripped substrate to produce a rinsed substrate. The rinsed substrate may be substantially free of a Sn layer or a Sn oxide layer. Further, the process may include contacting the rinsed substrate with an etch solution that is capable of removing an amount of one or more metals from the plurality of field regions.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Dynaloy, LLC
    Inventors: Richard Dalton Peters, Travis Acra, Spencer Erich Hochstetler, Kimberly Dona Pollard
  • Patent number: 9023735
    Abstract: An etchant composition includes ammonium persulfate (((NH4)2)S2O8), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 5, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bong-Kyun Kim, Hong Sick Park, Wang Woo Lee, Young Min Moon, Seung Ho Yoon, Young Joo Choi, Sang-Woo Kim, Ki-Beom Lee, Dae-Woo Lee, Sam-Young Cho
  • Patent number: 9005458
    Abstract: Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Roy Meade
  • Patent number: 9005464
    Abstract: A tool and method is provided for mixing multiple components and feeding a single blend of the multiple components into the tool. The method includes adjusting a concentration of etchant solution. The method includes determining an etch target for each batch of wafers of a plurality of batches of wafers entering an etch chamber of a wafer processing tool. The method further includes adjusting a concentration of 40% NH4F to 49% HF for the each batch of wafers of the plurality of batches of wafers entering the wafer processing tool during a single run.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Russell H. Arndt, David F. Hilscher
  • Patent number: 8981345
    Abstract: Provided is a graphene nanoribbon sensor. The sensor includes a substrate, a graphene layer formed on the substrate in a first direction, and an upper dielectric layer on the graphene layer. Here, the graphene layer may have a plurality of electrode regions respectively separated in the first direction and a channel between the plurality of electrode regions.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young-Jun Yu, Choon Gi Choi
  • Patent number: 8969217
    Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
  • Patent number: 8962492
    Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 24, 2015
    Assignee: Soitec
    Inventors: Patrick Reynaud, Ludovic Ecarnot, Khalid Radouane
  • Patent number: 8951901
    Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Patent number: 8951828
    Abstract: A method for making electronic devices based on derivatized ladder polymer poly(benzo-isimidazobenzophenanthroline) (BBL) including photovoltaic modules and simple thin film transistors in planar and mechanically flexible and stretchable constructs.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: February 10, 2015
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventors: William W. Lai, Alfred J. Baca
  • Patent number: 8945952
    Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: February 3, 2015
    Assignee: Intermolecular, Inc.
    Inventor: John Foster
  • Patent number: 8883033
    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
  • Patent number: 8883030
    Abstract: A substrate processing apparatus comprising a substrate holding rotating mechanism, a process liquid supply mechanism having a nozzle for dispensing a process liquid toward a principal face of the substrate, a processing liquid reservoir for holding sufficient process liquid to form a liquid film covering the whole principal face of the substrate, a liquid film forming unit for forming the liquid film by supplying the process liquid onto the principal face of the substrate in a single burst, and a control unit for controlling the liquid film forming unit and the process liquid supply mechanism such that the process liquid is dispensed from the process liquid nozzle toward the principal face of the substrate after formation of the liquid film covering the whole area of the principal face of the substrate by the liquid film forming unit.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: November 11, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Masahiro Miyagi, Koji Hashimoto, Toru Endo
  • Patent number: 8877653
    Abstract: A solvent vapor containing a solvent material capable of dissolving hydrogen fluoride is supplied to a surface of a substrate, thereby covering the surface of the substrate with a liquid film containing solvent material. Thereafter an etching vapor containing a hydrogen fluoride is supplied to the surface of the substrate covered by the liquid film containing the solvent material, thereby etching the surface of the substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 4, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takahiro Yamaguchi, Akio Hashizume, Yuya Akanishi, Takashi Ota
  • Patent number: 8859431
    Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, John Foster, Olov Karlsson, James Mavrinac, Usha Raghuram
  • Patent number: 8835261
    Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edward J. Nowak, Richard Q. Williams
  • Patent number: 8822346
    Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Kurt Weiner
  • Patent number: 8778802
    Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Dai Fukushima, Gaku Minamihaba, Hiroyuki Yano
  • Patent number: 8759230
    Abstract: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Michael Melzl, Josef Schwaiger, Thilo Stache
  • Publication number: 20140170857
    Abstract: A method of combinatorial processing involving etching a first material and a second material on a substrate comprising: etching the first material with a high first etch rate with a first etchant; etching the second material with a high second etch rate with a second etchant, wherein the first etchant and the second etchant are used sequentially without being separated by a rinse.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventors: Chi-I Lang, Shuogang Huang, Jeffrey Chih-Hou Lowe, Robert Anthony Sculac
  • Patent number: 8753969
    Abstract: A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 8703005
    Abstract: A method for removing a plurality of dielectric materials from a supporting substrate by providing a substrate with a plurality of materials, contacting the substrate at a first temperature with a solution to more quickly remove a first dielectric material than a second dielectric material at the first temperature, and then contacting the substrate at a second temperature with a solution to more quickly remove the second dielectric material than the first dielectric material at the second temperature. Thus, the dielectric materials exhibit different etch rates when etched at the first and second temperatures. The solutions to which the first and second dielectric materials are exposed may contain phosphoric acid. The first dielectric material may be silicon nitride and the second dielectric material may be silicon oxide. Under these conditions, the first temperature may be about 175° C., and the second temperature may be about 155° C.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8691703
    Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 8, 2014
    Assignee: SK Hynix Inc.
    Inventors: Suk Ki Kim, Hyeon Soo Kim
  • Publication number: 20140080313
    Abstract: An etching composition for a semiconductor wafer is provided, including 0.5-50 wt % base, 10-80 wt % alcohol, 0.01-15 wt % additive and water. A method for etching a semiconductor wafer is also provided. When the etching composition is applied to the entire surface or a partial surface of the semiconductor wafer at 60-200° C., the etching composition reacts on the semiconductor wafer to form a foam that etches the semiconductor wafer and includes a solid, a liquid and a gas. At the same time, the additive forms an oxide mask on the surface of the semiconductor wafer. Therefore, an excellent texture structure is formed on the surface of the semiconductor wafer, and a single surface of the semiconductor wafer is etched.
    Type: Application
    Filed: December 21, 2012
    Publication date: March 20, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Min YU, Wen-Ching SUN, Tai-Jui WANG, Yi-Fan CHEN, Chia-Liang SUN, Hao-Hsiang CHIANG, Pin-Guan LIAO, Chi-Fan CHIANG, Tzer-Shen LIN
  • Patent number: 8632690
    Abstract: A method for combinatorially processing a substrate is provided. The method includes introducing a first etchant into a reactor cell and introducing a fluid into the reactor cell while the first etchant remains in the reactor cell. After initiating the introducing the fluid, contents of the reactor cell are removed through a first removal line and a second removal line, wherein the first removal line extends farther into the reactor cell than the second removal line. A level of the fluid above an inlet to the first removal line is maintained while removing the contents. A second etchant is introduced into the reactor cell while removing the contents through the first removal line and the second removal line. The method includes continuing the introducing of the second etchant until a concentration of the second etchant is at a desired level, wherein the surface of the substrate remains submerged.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 21, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Edwin Adhiprakasha, Shuogang Huang
  • Patent number: 8623231
    Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Chih-Yang Yeh
  • Patent number: 8613864
    Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: December 24, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Prashant Raghu
  • Patent number: 8609550
    Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: December 17, 2013
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 8603837
    Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 10, 2013
    Assignee: Intermolecular, Inc.
    Inventor: John Foster
  • Patent number: 8563429
    Abstract: Methods of forming a metal silicide layer are provided that include exposing polysilicon through just dry etching (JDE) and recessesing an oxide layer through chemical dry etching (CDE). In particular, dry etching is primarily performed to an extent to expose the polysilicon. Then, CDE is secondarily performed to expose the polysilicon. The CDE process includes selecting an etchant source among combinations of NF3 and NH3, HF and NH3, and N2, H2, and NF3, dissociating the etchant source, forming an etchant of NH4F and NH4F.HF through the dissociation, producing solid by-products of (NH4)2SiF6 through the reaction between the etchant and an oxide at a low temperature, and annealing the by-products at a high temperature such that the by-products are sublimated into gas-phase SiF4, NH3, and HF.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Goo Hur, Kyu-Tae Na, Min Kim, Hyun-Young Kim, Je-Hyeon Park
  • Patent number: 8551846
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Myungsun Kim, Hoi Sung Chung
  • Patent number: 8492288
    Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: July 23, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, Niraj B. Rana, Sandra Tagg, Robert J. Hanson, Gundu M. Sabde, Donald L. Yates, Patrick M. Flynn, Prashant Raghu, Kyle Grant
  • Patent number: 8461056
    Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 11, 2013
    Assignee: Rexchip Electronics Corporation
    Inventors: Wei-Che Chang, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
  • Patent number: 8455366
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Publication number: 20130122716
    Abstract: Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 16, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Berthold Reimer, Claudia Wolf
  • Patent number: 8435903
    Abstract: In one embodiment, a method for treating a surface of a semiconductor substrate is disclosed. The semiconductor substrate has a first pattern covered by a resist and a second pattern not covered by the resist. The method includes supplying a resist-insoluble first chemical solution onto a semiconductor substrate to subject the second pattern to a chemical solution process. The method includes supplying a mixed liquid of a water repellency agent and a resist-soluble second chemical solution onto the semiconductor substrate after the supply of the first chemical solution, to form a water-repellent protective film on a surface of at least the second pattern and to release the resist. In addition, the method can rinse the semiconductor substrate using water after the formation of the water-repellent protective film, and dry the rinsed semiconductor substrate.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Ogawa, Shinsuke Kimura, Tatsuhiko Koide, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 8420546
    Abstract: In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lov, area to a desired dimensional range so that the dimension thereof becomes larger.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ichiro Uehara, Hideomi Suzawa
  • Patent number: 8409893
    Abstract: A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?U; and (c) further etching the backing so as to form a convex-part lower layer whose sectional shape on the cutting plane corresponding to the {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?D (where ?D??U).
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 2, 2013
    Assignee: Sony Corporation
    Inventors: Kiyotaka Yashima, Yoshinari Kiwaki, Kamada Michiru, Sachio Karino, Hironobu Narui, Nobukata Okano
  • Patent number: 8398877
    Abstract: A method is provided for forming an opening in a layer of a selected material. The method comprises, forming a polymer resist layer over said selected material and plasticising areas of the resist where openings are to be formed. The plasticising is performed by depositing a first solution onto the surface of said polymer resist layer, where the first solution is a plasticiser selected to increase permeability of the polymer resist layer to a second solution, in an area which has absorbed the first solution. The second solution is selected to be an etchant or solvent for the selected material. After the resist layer has been selectively plasticised, it is contacted with the second solution, which permeates the polymer resist layer in the area of increased permeability and forms an opening in the selected material.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: March 19, 2013
    Assignee: Newsouth Innovations Pty Ltd.
    Inventors: Stuart Ross Wenham, Alison Lennon, Roland Yudadibrata Utama, Anita Wing Yi Ho-Baillie
  • Patent number: 8377830
    Abstract: An electrically conductive first chemical solution is supplied to the back surface of a semiconductor substrate, on the front surface of which elements are formed. After starting supplying the first chemical solution, wet processing is performed by supplying an electrically conductive second chemical solution to the front surface of the semiconductor substrate.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Suzuki
  • Patent number: 8378385
    Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: February 19, 2013
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
  • Patent number: 8367556
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Patent number: 8354348
    Abstract: An object is to provide a method suitable for reprocessing a semiconductor substrate which is reused to manufacture an SOI substrate. A semiconductor substrate is reprocessed in the following manner: etching treatment is performed on a semiconductor substrate in which a projection including a damaged semiconductor region and an insulating layer exists in a peripheral portion, whereby the insulating layer is removed; and etching treatment is performed on the semiconductor substrate with the use of a mixed solution including a substance that oxidizes a semiconductor material included in the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls oxidation speed of the semiconductor material and dissolution speed of the oxidized semiconductor material, whereby the damaged semiconductor region is selectively removed with a non-damaged semiconductor region left.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: January 15, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Keitaro Imai
  • Patent number: 8338205
    Abstract: A method of fabricating and encapsulating MEMS devices is disclosed, using least two carbon films as the dual sacrificial layers sandwiching a MEMS structural film which is anchored onto a substrate and covered by an encapsulating film containing a plurality of thru-film sacrificial release holes. The dual sacrificial carbon films are selectively removed via plasma-enhanced oxygen or nitrogen ashing through the thru-film sacrificial release holes for releasing the MEMS structural film inside a cavity formed between the encapsulating film and the substrate. The thru-film sacrificial release holes, preferably with a relative high asperity ratio, are then sealed off by depositing a hole-sealing film in a physical vapor deposition process or a chemical vapor deposition process or combination.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: December 25, 2012
    Assignee: Shanghai Lexvu Opto Microelectronics Technology Co., Ltd.
    Inventor: Herb He Huang
  • Patent number: 8303723
    Abstract: In a liquid processing apparatus configured to remove, from a substrate including a first film and a second film formed above the first film, the first film and the second film, a first chemical-liquid supply part supplies, to a substrate W, a first liquid for dissolving the first film, a second chemical-liquid supply part supplies a second chemical liquid for weakening the second film, and a fluid supply part serving also as an impact giving part gives a physical impact to the second film so as to break the second film and supplies a fluid for washing away debris of the broken second film. A control device controls the respective parts such that, after the second liquid has been supplied and then the fluid has been supplied from the fluid supply part, the first chemical liquid is supplied.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: November 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Teruomi Minami, Fumihiro Kamimura, Kazuki Kosai, Takashi Yabuta, Kenji Yokomizo, Shogo Mizota
  • Patent number: 8283257
    Abstract: Systems and methods for oscillating exposure of a semiconductor workpiece to multiple chemistries are disclosed. A method in accordance with one embodiment includes sequentially exposing a portion of a semiconductor workpiece surface to a first chemistry having a first chemical composition and a second chemistry having a second chemical composition different than the first. Prior to rinsing the portion of the workpiece surface, the portion is sequentially exposed to the first and second chemistries again. The first and second chemistries are removed from the portion, and, after sequentially exposing the portion to each of the first and second chemistries at least twice, and removing the first and second chemistries, the portion is rinsed and dried.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Michael Andreas
  • Patent number: 8278187
    Abstract: Disclosed is a method for reprocessing a semiconductor substrate which is by-produced in manufacturing a silicon-on-insulator substrate. The method includes: forming an embrittlement layer in a single crystal semiconductor substrate; bonding the single crystal semiconductor substrate with a base substrate having an insulating surface; and separating the single crystal semiconductor substrate along the embrittlement layer to give a silicon-on-insulator substrate and a semiconductor substrate to be reprocessed. The above steps provide, in the peripheral portion on the semiconductor substrate, a projection comprising the embrittlement layer and a single crystal semiconductor layer over the embrittlement layer. The method is characterized by an etching step to selectively remove the projection without etching a portion where the projection is absent, which allows the semiconductor substrate to be reused for the production of another silicon-on-insulator substrate.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kazuya Hanaoka
  • Patent number: 8221642
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8222160
    Abstract: According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Uozumi