Silicon Patents (Class 438/753)
  • Patent number: 10428415
    Abstract: The present invention discloses a method of manufacturing a shadow mask, wherein hybrid processing is used to form a mask pattern on the shadow mask, the method includes: forming a wet-etched pattern by performing wet etching from above a base; and forming a laser-processed pattern that continues from the wet-etched pattern, by performing laser processing from above the base or from below the base on which the wet-etched pattern is formed. The present invention uses hybrid processing including wet etching and laser processing for manufacturing a shadow mask. The method has an effect on solving the productivity degradation of the conventional laser processing and provides a shadow mask with high quality using wet etching.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 1, 2019
    Assignee: AP SYSTEMS INC.
    Inventors: Jong-Kab Park, Bo-Ram Kim, Jun-Gyu Hur, Doh-Hoon Kim
  • Patent number: 10414978
    Abstract: An etching composition may include a peracetic acid mixture, a fluorine compound, an organic solvent (e.g., acetate-series organic solvent), and water. The etching composition may be used to selectively etch silicon-germanium (SiGe).
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 17, 2019
    Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.
    Inventors: Soo Jin Kim, Hyo Sun Lee, Jin Hye Bae, Jung Hun Lim, Yong Jae Choi
  • Patent number: 10309958
    Abstract: A system for detecting target elements such as bacteria in a host analyte, comprising a substrate with an ordered array of wells having diameters to fit the size of the targets. The substrate may be a periodic macro-PSi array structure (MPSiAS) illuminated with a broadband source. The reflected light spectrum diffracted from the substrate is optically analyzed to provide the effective optical depth of the wells. Fast Fourier Transform analysis may be used for the optical analysis. Entry of target elements into wells is detected by the change in the effective optical depths of the wells. Micro-organisms as large as bacteria and viruses having dimensions comparable with the wavelength of the illumination can thus be detected. Wells with an inner section impenetrable by the target cells enables compensation for environmental changes. The detection may be performed in real time, such that production line bacterial monitoring may be achieved.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: June 4, 2019
    Assignees: YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM LTD., TECHNION RESEARCH & DEVELOPMENT FOUNDATION LIMITED
    Inventors: Amir Sa'ar, Ester Segal
  • Patent number: 10242880
    Abstract: Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive. The first additive and the second additive are separately supplied to the process bath.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangsu Kim, Se-Ho Cha, Yongsun Ko, Keonyoung Kim, Kyunghyun Kim, ChangSup Mun, Choongkee Seong, Sunjoong Song, Jinwoo Lee, Hoon Han
  • Patent number: 10090158
    Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 2, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Yusaku Asano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 9925776
    Abstract: A method of manufacturing a plurality of semiconductor chips for a liquid discharge head from a substrate includes forming trenches of a linear form through etching from the second surface along intended cutting portions, forming modified portions in the substrate by irradiating a laser beam from the first surface side along the intended cutting portions, and splitting the substrate into the plurality of semiconductor chips for a liquid discharge head, by cutting the substrate with stress applied to the modified portions. The intended cutting portions include inclined portions extending in a direction inclined with respect to a crystal orientation plane of the substrate and uninclined portions extending in a direction along the crystal orientation plane of the substrate, and the trenches are formed at least along the inclined portions.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 27, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomohiro Takahashi, Toru Kawaguchi, Toshiyasu Sakai, Masataka Kato
  • Patent number: 9656291
    Abstract: Disclosed is a method of manufacturing a metal mask. A method of manufacturing a metal mask in accordance with an exemplary embodiment of the present invention includes forming through holes in a plate using a laser, by scanning the laser onto sequentially smaller overlapping portions of the plate.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 23, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Choong Ho Lee, Tong-Jin Park, Doh-Hyoung Lee, Sung Sik Yun, Da Hee Jeong, Jun Ho Jo
  • Patent number: 9324891
    Abstract: A solar cell (1) of the present invention includes a photoelectric conversion layer (2) and a photonic crystal provided inside the photoelectric conversion layer (2) in order to have a photonic band gap. The photonic crystal has defects (31) in order to provide a defect level in the photonic band gap. QV which is a Q value representing a magnitude of a resonance effect yielded by coupling between the photonic crystal and an outside is substantially equal to Q? which is a Q value representing a magnitude of a resonance effect yielded by a medium of the photoelectric conversion layer (2).
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 26, 2016
    Assignees: Sharp Kabushiki Kaisha, Kyoto University
    Inventors: Hiroaki Shigeta, Yuhji Yashiro, Yuhsuke Tsuda, Shintaro Miyanishi, Susumu Noda, Masayuki Fujita, Yoshinori Tanaka
  • Patent number: 9245889
    Abstract: A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate, which correspond to the dimensions of a sidewall pattern around a dummy pattern. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. N-type and P-type diffusion layers are in upper portions of the first and second fin-shaped layers, respectively, and in upper and lower portions of the first and second pillar-shaped layers, respectively. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: January 26, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9165833
    Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: October 20, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Michael J. Seddon
  • Patent number: 9165837
    Abstract: Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jody Fronheiser, Murat Kerem Akarvardar, Ajey P. Jacob, Steven Bentley
  • Patent number: 9152750
    Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 6, 2015
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 9012328
    Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Xuebin Li, Saurabh Chopra, Yihwan Kim
  • Patent number: 8999850
    Abstract: Methods and apparatus for etching materials using tetramethylammonium hydroxide (TMAH) are described. The methods may involve including an additive when applying the TMAH to the material to be etched. The additive may be a gas, and in some situations may be clean dry air. The clean dry air may be provided with the TMAH to minimize or prevent the formation of hillocks in the etched structure. Apparatus for performing the methods are also described.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Ying Yu, Tien Choy Loh, Shian Yeu Kam
  • Patent number: 8974691
    Abstract: A polishing composition for a silicon wafer and a rinsing composition for a silicon wafer according to the present invention contain a nonionic surfactant of a polyoxyethylene adduct. The HLB value of the polyoxyethylene adduct is 8 to 15. The weight-average molecular weight of the polyoxyethylene adduct is 1400 or less. The average number of moles of oxyethylene added in the polyoxyethylene adduct is 13 or less. The content of the polyoxyethylene adduct in each of the polishing composition and the rinsing composition is 0.00001 to 0.1% by mass.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 10, 2015
    Assignee: Fujimi Incorporated
    Inventors: Kohsuke Tsuchiya, Shuhei Takahashi
  • Publication number: 20150056818
    Abstract: Systems and methods for etching the surface of a substrate may utilize a thin layer of fluid to etch a substrate for improved anti-reflective properties. The substrate may be secured with a holding fixture that is capable of positioning the substrate. A fluid comprising an acid and an oxidizer for etching may be prepared, which may optionally include a metal catalyst. An amount of fluid necessary to form a thin layer contacting the surface of the substrate to be etched may be dispensed. The fluid may be spread into the thin layer utilizing a tray that the substrate is dipped into, a plate that is placed near the surface of the substrate to be etched, or a spray or coating device.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 26, 2015
    Applicant: Natcore Technology, Inc.
    Inventors: David Howard Levy, Theodore Zubil, Richard W. Topel, JR., Wendy G. Ahearn
  • Patent number: 8962492
    Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: February 24, 2015
    Assignee: Soitec
    Inventors: Patrick Reynaud, Ludovic Ecarnot, Khalid Radouane
  • Patent number: 8951430
    Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Matthew T. Dejarld, Jae Cheol Shin, Winston Chern
  • Patent number: 8940178
    Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 27, 2015
    Assignee: E I du Pont de Nemours and Company
    Inventors: Seung Jin Lee, Hee Soo Yeo
  • Patent number: 8940644
    Abstract: A method for manufacturing a semiconductor substrate product having: providing an etching liquid containing water, a hydrofluoric acid compound and an organic solvent, and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: January 27, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Mizutani, Tetsuya Kamimura, Akiko Yoshii, Tetsuya Shimizu
  • Patent number: 8932958
    Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lun Lu, Kuan-Wen Lin, Ching-Wei Shen, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 8916478
    Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: December 23, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8906772
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 9, 2014
    Assignee: UChicago Argonne, LLC
    Inventor: Anirudha V. Sumant
  • Patent number: 8900472
    Abstract: A liquid agent for the surface treatment of monocrystalline wafers, which contains an alkaline etching agent and also at least one low-volatile organic compound. Systems of this type can be used both for the cleaning, damage etch and texturing of wafer surfaces in a single etching step and exclusively for the texturing of silicon wafers with different surface quality, whether it now be wire-sawn wafers with high surface damage or chemically polished surfaces with minimum damage density.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: December 2, 2014
    Assignee: Fraunhofer-Gesellschaft zur Föerderung der angewandten Forschung E.V.
    Inventors: Kuno Mayer, Mark Schumann, Daniel Kray, Teresa Orellana Peres, Jochen Rentsch, Martin Zimmer, Elias Kirchgässner, Eva Zimmer, Daniel Biro, Arpad Mihai Rostas, Filip Granek
  • Patent number: 8901010
    Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: SunPower Corporation
    Inventors: Staffan Westerberg, Florito Dennis Tingchuy Vicente, Michael Cudzinovic, Princess Carmi Tomada, Jemellee Guiao
  • Patent number: 8894868
    Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Andy Hooper, Daragh Finn, Tim Webb, Lynn Sheehan, Kenneth Pettigrew, Yu Chong Tai
  • Patent number: 8894877
    Abstract: A liquid composition for wet etching has improved selectivity for polysilicon over silicon dioxide, even when the polysilicon is heavily doped and/or the silicon dioxide is a low temperature oxide. The composition comprises 0.05-0.4 percent by weight hydrofluoric acid, 15-40 percent by weight nitric acid, 55-85 percent by weight sulfuric acid and 2-20 percent by weight water. A method and apparatus for wet etching using the composition are also disclosed.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: November 25, 2014
    Assignee: Lam Research AG
    Inventor: Stefan Detterbeck
  • Patent number: 8889562
    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ying Zhang
  • Publication number: 20140332933
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface located on the surface of the substrate, a first end surface and a second end surface parallel to each other, and a front side surface and a rear side surface parallel to each other, in which the rear side surface of one of two adjacent convex structures and the front side surface of the other are located on a same plane to allow the plurality of convex structures to form a zigzag structure.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 13, 2014
    Inventors: Yuan Li, Lei Guo
  • Publication number: 20140308819
    Abstract: A method of producing a semiconductor substrate product, the method containing: a step of preparing an aqueous solution containing 7% by mass or more and 25% by mass or less of a quaternary alkyl ammonium hydroxide; a step of preparing a semiconductor substrate having a silicon film comprising a polycrystalline silicon film or an amorphous silicon film; and a step of heating the aqueous solution at 80° C. or higher and applying the resultant aqueous solution onto the semiconductor substrate to etch at least a part of the silicon film.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Applicant: FUJIFILM CORPORATION
    Inventors: Masashi ENOKIDO, Tadashi INABA, Atsushi MIZUTANI
  • Patent number: 8859334
    Abstract: An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips are subjected in one batch to barrel polishing. The method further includes an aligning step at which the polished chips are aligned so that front surfaces thereof face in an upward direction. The method further includes a bonding step at which the cut surfaces of the aligned chips are bonded together with an adhesive to thereby form a chip assembly. The method further includes a pattern forming step at which a circuit pattern is formed on each of the chips of the chip assembly and a melting step at which the adhesive on the chip assembly is melted to thereby separate the chip assembly into chips after pattern formation.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventors: Hajime Kubota, Masayuki Itoh, Masakazu Kishi
  • Patent number: 8852451
    Abstract: The present invention relates to a silicon etching solution which is used for selectively etching a dummy gate made of silicon in a process for producing a transistor including a laminate formed of at least a high dielectric material film and a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten by the method of removing the dummy gate made of silicon to replace the dummy gate with the metal gate and which includes 0.1 to 40% by weight of at least one alkali compound selected from the group consisting of ammonia, a diamine and a polyamine represented by the general formula (1), 0.01 to 40% by weight of at least one polyhydric alcohol selected from the group consisting of specific polyhydric alcohols and a non-reducing sugar, and 40 to 99.89% by weight of water, and a process for producing a transistor using the silicon etching solution.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 7, 2014
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kenji Shimada, Hiroshi Matsunaga
  • Patent number: 8852447
    Abstract: A method for simultaneously detecting and separating a target analyte such as a protein or other macromolecule that includes providing a porous silicon matrix on the silicon substrate, exposing the porous silicon matrix to an environment suspect of containing the target analyte, observing optical reflectivity of the porous silicon matrix; and correlating the changes in the silicon substrate to the target analyte.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 7, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael J. Sailor, Gaurav Abbi, Boyce E. Collins, Keiki-Pua S. Dancil
  • Publication number: 20140273501
    Abstract: An silicon-containing antireflective coating (SiARC) material is applied on a substrate. The SiARC material which includes a base polymer and may include a boron silicate polymer including silsesquioxane. An etch sequence is utilized, which includes a first wet etch employing a basic solution, a second wet etch employing an acidic solution, and a third wet etch employing another basic solution. The first wet etch can be employed to break up the boron silicate polymer, and the second wet etch can remove the base polymer material, and the third wet etch can remove the residual boron silicate polymer and other residual materials. The SiARC material can be removed from a substrate employing the etch sequence, and the substrate can be reused for monitoring purposes.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicants: SHIN-ETSU Chemical Company, Ltd., International Business Machines Corporation
    Inventors: Martin Glodde, Wu-Song Huang, Javier J. Perez, Takeshi Kinsho, Tsutomu Ogihara, Seiichiro Tachibana, Takeru Watanabe
  • Publication number: 20140273467
    Abstract: Polycrystalline silicon (poly-Si) can be thoroughly removed without significant effect on adjacent oxides by an aqueous solution of ammonium hydroxide with smaller concentrations of hydrogen peroxide than are normally used in ammonia-peroxide mixture (APM) formulations used for cleaning. The etching selectivity of poly-Si relative to oxides can be widely tuned by varying the hydrogen-peroxide concentration. Compared to other formulations used to remove poly-Si dummy gates in logic-node fabrication, such as TMAH, these aqueous solutions are less hazardous to workers and the environment.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: INTERMOLECULAR INC.
    Inventor: Gregory Nowling
  • Patent number: 8828260
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 9, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8828144
    Abstract: A process for cleaning a wafer having an uneven pattern at its surface. The process includes at least the steps of: cleaning the wafer with a cleaning liquid; substituting the cleaning liquid retained in recessed portions of the wafer with a water-repellent liquid chemical after cleaning; and drying the wafer, wherein the cleaning liquid contains 80 mass % or greater of a solvent having a boiling point of 55 to 200° C., and wherein the water-repellent liquid chemical supplied in the substitution step has a temperature of not lower than 40° C. and lower than a boiling point of the water-repellent liquid chemical thereby imparting water repellency at least to surfaces of the recessed portions.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: September 9, 2014
    Assignee: Central Grass Company, Limited
    Inventors: Soichi Kumon, Takashi Saio, Shinobu Arata, Masanori Saito, Hidehisa Nanai, Yoshinori Akamatsu
  • Patent number: 8822346
    Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Kurt Weiner
  • Patent number: 8815108
    Abstract: A method of depositing a non-continuous coating of a first material on a substrate, comprising: a) the formation of a mask on this substrate, by forming at least two mask layers, and etching of at least one cavity in these layers, this cavity having an outline such that a coating, deposited on the substrate, through the cavities of the mask, has at least one discontinuity over said outline of the cavity; b) the deposition of the first material on the substrate, through the cavities of the mask, the coating thus deposited having at least one discontinuity over the outline of said cavity; and c) the mask is removed.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: August 26, 2014
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bruno Remiat, Laurent Vandroux, Florent Souche
  • Publication number: 20140235064
    Abstract: This invention is concerning an etchant composition used to etch a silicon-containing film formed on a target substrate. The etchant composition includes at least one selected from the group consisting of an organic compound containing a hydroxyl group, an organic compound containing a carbonyl group, an inorganic acid and inorganic salt, hydrofluoric acid, ammonium fluoride and an organic acid.
    Type: Application
    Filed: August 17, 2012
    Publication date: August 21, 2014
    Applicant: HAYASHI PURE CHEMICAL IND., LTD.,
    Inventors: Atsushi Matsui, Mayumi Kimura, Tsuguhiro Tago
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Publication number: 20140227885
    Abstract: The invention relates to a method for the conditioning of flat objects such as silicon substrates. The objects, obtained by sawing from a block form a comb like structure by being fixed with one edge to a plate shaped fixation apparatus, are conditioned by conventional rinsing, separating and wet chemical treatment, wherein the treatment takes place before the separation of the sawed substrates from the fixation apparatus. An apparatus which is suitable for carrying out the method has two regions arranged parallel to the apparatus longitudinal axis (L) and above one another, wherein the upper region is configured as an adapter region (1). The lower region is formed as a holding region (2) which comprises a part, provided as a channel (11), of a circumferentially closed or closable channel system which can be supplied with liquid by means of closable supply openings (5).
    Type: Application
    Filed: June 1, 2012
    Publication date: August 14, 2014
    Applicant: RENA GMBH
    Inventor: Jens Moecke
  • Patent number: 8796157
    Abstract: Method of selectively etching a first material on a substrate with a high selectivity towards a second material by flowing a liquid etchant across a substrate surface at a flow sufficiently fast to generate a minimum mean velocity parallel to the substrate's surface, wherein the first material is selected from a group including materials with semiconducting properties based on at least two different chemical elements.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: August 5, 2014
    Assignee: Lam Research AG
    Inventor: Gerald Wagner
  • Patent number: 8772623
    Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Mark W. Wanlass, Jeffrey J. Carapella
  • Patent number: 8772174
    Abstract: A method for treating silicon to form pillars, especially for use as the active anode material in Li-ion batteries, is disclosed. The process is simple to operate on a commercial scale since it uses a solution containing only a small number of ingredients whose concentration needs to be controlled and it can be cheaper to operate than previous processes. The solution includes: 0.01 to 5M HF 0.002 to 0.2M of metal ions capable of nucleating on and forming a porous layer comprising regions of elemental metal on the silicon surface; 0.001 to 0.7M of an oxidant selected from the group O2, O3, H2O2, the acid, ammonium or alkali metal salt of NO3?, S2O82?, NO2?, B4O72? and ClO4? or a mixture thereof. The treated silicon is suitably removed from the solution.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Nexeon Ltd.
    Inventors: Mino Green, Feng-Ming Liu, Yuxiong Jiang, Valerie Elizabeth Dawn Stevens, Benjamin Odarkwei Mills-Lamptey
  • Patent number: 8772175
    Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 8, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8765001
    Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 1, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Michael P. Toben, Robert K. Barr, Corey O'Connor
  • Patent number: 8759229
    Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 24, 2014
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
  • Patent number: 8759231
    Abstract: The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. Processes for texturing a crystalline silicon substrate using these formulations are also described.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: June 24, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Zhi-Wen Sun, Sagar Vijay
  • Patent number: RE44995
    Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: July 8, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaefer