Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: A method for treating silicon to form pillars, especially for use as the active anode material in Li-ion batteries, is disclosed. The process is simple to operate on a commercial scale since it uses a solution containing only a small number of ingredients whose concentration needs to be controlled and it can be cheaper to operate than previous processes. The solution includes: 0.01 to 5M HF 0.002 to 0.2M of metal ions capable of nucleating on and forming a porous layer comprising regions of elemental metal on the silicon surface; 0.001 to 0.7M of an oxidant selected from the group O2, O3, H2O2, the acid, ammonium or alkali metal salt of NO3?, S2O82?, NO2?, B4O72? and ClO4? or a mixture thereof. The treated silicon is suitably removed from the solution.

Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption.

Abstract: The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. Processes for texturing a crystalline silicon substrate using these formulations are also described.

Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.

Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Abstract: The present invention relates to a method of preparing a porous silicon nanorod structure composed of columnar bundles having a diameter of 50-100 nm and a length of 2-5 ?m, and a lithium secondary cell using the porous silicon nanorod structure as an anode active material. The present invention provides a high-capacity and high-efficiency anode active material for lithium secondary cells, which can overcome the low conductivity of silicon and improve the electrode deterioration attributable to volume expansion because it is prepared by electrodepositing the surface of silicon powder with metal and simultaneously etching the silicon powder partially using hydrofluoric acid.

Abstract: Disclosed are a method for manufacturing a solar cell by processing a surface of a silicon substrate for a solar cell, a solar cell manufactured by the method, and a substrate processing system for performing the method. The method for manufacturing a solar cell comprises protrusion forming step including wet-etching process and for forming a plurality of minute protrusions on a light receiving surface of a crystalline silicon substrate, and planarization step of planarizing the bottom surface, the opposite surface to the light receiving surface of the substrate during or after the protrusion forming step.

Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and construct a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of less than 45° therebetween, and the modified spots are made align in a plurality of rows along the line.

Abstract: Disclosed are a liquid processing method, a liquid processing apparatus, and a recording medium that can prevent convex portions of a target substrate from collapsing when a rinsing liquid is dried. A base surface of a target substrate is hydrophilized and the surfaces of convex portions become water-repellent by surface-processing the target substrate which includes a main body, a plurality of convex portions protruding from the main body, and a base surface formed between the convex portions on the substrate main body. Next, a rinsing liquid is supplied to the target substrate which has been subjected to the surface processing. Thereafter, the rinsing liquid is removed from the target substrate.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.

Abstract: In some embodiments, the present invention discloses an etchant solution hydrochloric acid and nitric acid to etch doped polysilicon at low etch rates. The doped polysilicon can be doped with Ge, In, B and Ga. Preferably, the concentration of hydrochloric acid can be greater than 1 vol %, and the concentration of nitric acid is greater than 15 vol %.

Abstract: A method for manufacturing a substrate for liquid-ejecting heads includes etching a surface of a silicon substrate using a first etchant, with a silicon oxide layer as a mask, to form a depression as a part of a liquid supply port, and subsequently etching at least the silicon oxide layer and the thickness sandwiched between the depression and the etched surface of the silicon substrate with a second etchant to form the liquid supply port.

Abstract: In a method for manufacturing a micromechanical component, a cavity is produced in the substrate from an opening at the rear of a monocrystalline semiconductor substrate. The etching process used for this purpose and the monocrystalline semiconductor substrate used are controlled in such a way that a largely rectangular cavity is formed.

Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises a laser light converging step of converging the laser light at the object so as to form the modified region along a part corresponding to the through hole in the object; an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object after the laser light converging step; and an etching step of etching the object so as to advance the etching selectively along the modified region and form the through hole after the etch resist film producing step; while the laser light converging step exposes the modified region to the outer surface of the object.

Abstract: The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking.

Abstract: A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.

Abstract: This invention relates to a method for texturing a silicon surface and silicon wafers made by the method, where the method comprises immersing the wafers in an alkaline solution at pH>10, and applying a potential difference between the wafer and a platinum electrode in the electrolyte in the range of +10 to +85 V.

Abstract: A method of roughening a substrate surface includes forming an opening in a protection film formed on a surface of a semiconductor substrate, performing a first etching process using an acid solution by utilizing the protection film as a mask so as to form a first concave under the opening and its vicinity area, performing an etching process by using the protection film as a mask so as to remove an oxide film formed on a surface of the first concave, performing anisotropic etching by using the protection film as a mask so as to form a second concave under the opening and its vicinity area, and removing the protection film.

Abstract: In a method of treating a substrate according to the inventive concept, the substrate is treated using a buffer solution including carbon dioxide (CO2) water in combination with an alkaline solution.

Abstract: Provided is a polishing composition that does not contain abrasives and that is used for polishing a silicon wafer, the polishing composition including a pH buffer, a polishing accelerator, a water-soluble polymer, and a block-type compound. By polishing a silicon wafer by using the polishing composition, a polishing speed of greater than 0.1 ?m/min can be achieved.

Abstract: A method of removing an alumina layer around a main pole layer during perpendicular magnetic recording head fabrication is disclosed. The alumina etch sequence includes immersing a substrate in a series of aqueous solutions purged with an inert gas to remove oxygen thereby avoiding corrosion of the main pole. Initially, the substrate is soaked and heated in deionized (DI) water. Once heated, the substrate is immersed in an etching bath at about 80° C. and pH 10.5. Bath chemistry is preferably based on Na2CO3 and NaHCO3, and N2 purging improves etch uniformity and reduces residue. Thereafter, the substrate is rinsed in a second DI water bath between room temperature and 80° C., and finally subjected to a quick dump rinse before drying. Inert gas, preferably N2, may be introduced into the aqueous solutions through a purge board having a plurality of openings and positioned proximate to the bottom of a bath container.

Abstract: A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell's channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams.

Abstract: The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40° C., comprising placing in contact the silicon layer with a second solution containing water (H2O) diluted ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), in order to obtain a roughness of less than 0.100 nanometer on a 1 ?m×1 ?m area upon completion of the treatment cycles. The invention will be applied in the field of microelectronics for the production of transistors, of surfaces for photovoltaic panels or for direct molecular bonding.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: A method of forming a plurality of discrete, interconnected solar cells mounted on a carrier by providing a first semiconductor substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell structure; forming a metal back contact layer over the solar cell structure; mounting a carrier on top of the metal back contact; removing the first substrate; and lithographically patterning and etching the solar cell structure to form a plurality of discrete solar cells mounted on the carrier.

Abstract: A process for producing a micromachined tube (microtube) suitable for microfluidic devices. The process entails isotropically etching a surface of a first substrate to define therein a channel having an arcuate cross-sectional profile, and forming a substrate structure by bonding the first substrate to a second substrate so that the second substrate overlies and encloses the channel to define a passage having a cross-sectional profile of which at least half is arcuate. The substrate structure can optionally then be thinned to define a microtube and walls thereof that surround the passage.

Abstract: Systems and methods for detecting watermark formations on semiconductor wafers are described. In one embodiment, a method comprises providing a semiconductor wafer having at least one watermark sensitive region fabricated thereon, subjecting the wafer to a wet processing step, enhancing a susceptibility to detection of at least one watermark formation created on the at least one watermark sensitive region, and detecting the at least one watermark formation. In another embodiment, a method comprises growing a first oxide layer on a surface of a semiconductor wafer, patterning a watermark sensitive structure on the first oxide layer, depositing a silicon layer over the first oxide layer, doping a region of the silicon layer over the watermark sensitive structure with an impurity to create a watermark sensitive region that is prone to retaining watermark formations as result of a wet processing step, and growing a second oxide layer over the silicon layer.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

Abstract: A method for chemically treating a disc-shaped substrate having a bottom surface, a top surface and side surfaces by contacting a process medium that is fluid-chemically active with at least the bottom surface of the substrate. The substrate is moved relative to the process medium while forming a triple line between the substrate, the substrate medium and the atmosphere surrounding the substrate and medium. In order to chemically remove errors, particularly in the side surfaces, relative motion should be carried out while avoiding a contacting of the process medium with the top surface of the substrate, where the triple line is formed at a desired height of the side surface facing away from the process medium flow side in relation to the relative motion between the substrate and the process medium.

Abstract: In etching processing of silicon, in particular anisotropic etching processing of silicon in a manufacturing step of MEMS parts, an etching liquid having a long life of etching liquid and an etching method are provided by suppressing a lowering of an etching rate at the time of warming which is characteristic of a hydroxylamine-containing etching liquid. A silicon etching liquid which is an alkaline aqueous solution containing an alkali metal hydroxide, hydroxylamine and an inorganic carbonate compound and having a pH of 12 or more and which is able to anisotropically dissolve monocrystalline silicon therein, and an etching method of silicon using this etching liquid are provided.

Abstract: An apparatus for making an electrode of a dye-sensitized solar cell, includes a dye container, a number of nozzles, a roller and a number of holders. The dye container has a chamber for receiving a dye material, and the chamber has a top wall and a number of through holes formed through the top wall. The nozzles each have an opening facing toward a substrate to be formed into the electrode and configured for jetting a working material to the substrate. The roller rolls the working material on the substrate. The holders are rotatably mounted on the top wall and each hold a corresponding substrate to first receive the working material and then to be submerged into the dye material through one of the through holes of the dye container by rotation, thereby obtaining the electrode of a dye-sensitized solar cell.

Abstract: In a manufacture method for a photovoltaic module, a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel is simultaneously pasted on a solar cell. In particular, the manufacture method is implemented by performing the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Abstract: A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: A method for the wet-chemical etching of a solar cell emitter is provided. The method performs homogeneous etching using an alkaline etching solution containing at least one oxidizing agent selected from the group consisting of peroxodisulphates, peroxomonosulphates and hypochlorite.

Abstract: A method of fabricating a nanoporous membrane filter having a uniform array of nanopores etch-formed in a thin film structure (e.g. (100)-oriented single crystal silicon) having a predetermined thickness, by (a) using interferometric lithography to create an etch pattern comprising a plurality array of unit patterns having a predetermined width/diameter, (b) using the etch pattern to etch frustum-shaped cavities or pits in the thin film structure such that the dimension of the frustum floors of the cavities are substantially equal to a desired pore size based on the predetermined thickness of the thin film structure and the predetermined width/diameter of the unit patterns, and (c) removing the frustum floors at a boundary plane of the thin film structure to expose, open, and thereby create the nanopores substantially having the desired pore size.

Abstract: According to the present invention, there is provided an etching solution used for selectively etching a dummy gate made of silicon in a process for producing a transistor including a laminate formed of at least a high dielectric material film and an aluminum metal gate by the method of removing the dummy gate made of silicon to replace the dummy gate with the aluminum metal gate, and a process for producing a transistor using the etching solution. The present invention relates to a silicon etching solution used for etching the dummy gate made of silicon which includes 0.1 to 40% by weight of at least one alkali compound selected from the group consisting of ammonia, a diamine and a polyamine represented by the general formula (1), 5 to 50% by weight of at least one polyhydric alcohol represented by the general formula (2) and 40 to 94.9% by weight of water, and a process for producing a transistor using the silicon etching solution.

Abstract: A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.

Abstract: The present invention relates to a method for the wet-chemical edge deletion of solar cells. An etching paste is applied to the edge of a solar cell substrate surface and after the reaction is complete, the paste residue is removed. Optionally, the substrate surface is cleaned and dried. The etching paste comprises 85% H3PO4, NH4HF2 and 65% HNO3 in a ratio in the range from 7:1:1.5 to 10:1:3.5, based on the weight.

Abstract: A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.

Abstract: The present invention relates to a silicon etching solution which is used for selectively etching a dummy gate made of silicon in a process for producing a transistor including a laminate formed of at least a high dielectric material film and a metal gate containing hafnium, zirconium, titanium, tantalum or tungsten by the method of removing the dummy gate made of silicon to replace the dummy gate with the metal gate and which includes 0.1 to 40% by weight of at least one alkali compound selected from the group consisting of ammonia, a diamine and a polyamine represented by the general formula (1), 0.01 to 40% by weight of at least one polyhydric alcohol selected from the group consisting of specific polyhydric alcohols and a non-reducing sugar, and 40 to 99.89% by weight of water, and a process for producing a transistor using the silicon etching solution.

Abstract: An interposer includes grooves (310) for waveguides 104 (e.g. optical fiber cables) coupled to a transducer (120). The grooves are formed by etching a cavity (410) in a substrate (130), filling the cavity with some layer (520), then etching the layer to form the grooves. The grooves can be formed in a separate structure which is then inserted into a cavity in an interposer having electrical circuitry for the transducer. The cavity has outwardly or inwardly sloped sidewalls which can serve as minors (144) or on which the minors are later formed. The substrate can be monocrystalline silicon, in which the inwardly sloped (retrograde) sidewalls are formed by a combination of different etches at least one of which is selective to certain crystal planes. Other features, including non-optical embodiments, are also provided.

Abstract: There are provided a processing liquid for suppressing pattern collapse of a microstructure formed of polysilicon which includes at least one compound selected from the group consisting of pyridinium halides containing an alkyl group having 12, 14 or 16 carbon atoms, and water; and a method for producing a microstructure using the processing liquid.

Abstract: An aqueous acidic solution and an aqueous acidic etching solution suitable for texturizing the surface of single crystal and polycrystal silicon substrates, hydrofluoric acid; nitric acid; and at least one anionic polyether, which is surface active; a method for texturizing the surface of single crystal and polycrystal silicon substrates comprising the step of (1) contacting at least one major surface of a substrate with the said aqueous acidic etching solution; (2) etching the at least one major surface of the substrate for a time and at a temperature sufficient to obtain a surface texturization consisting of recesses and protrusions; and (3) removing the at least one major surface of the substrate from the contact with the aqueous acidic etching solution; and a method for manufacturing photovoltaic cells and solar cells using the said solution and the said texturizing method.

Abstract: A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.

Abstract: A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening.