Silicon Nitride Patents (Class 438/757)
  • Patent number: 9911631
    Abstract: Embodiments of the invention provide a processing system and a method for processing with a heated etching solution. In one example, tight control over temperature and hydration level of an acidic etching solution is provided. According to one embodiment, the method includes forming the heated etching solution in a first circulation loop, providing the heated etching solution in the process chamber for treating a substrate, forming an additional heated etching solution in a second circulation loop, and supplying the additional heated etching solution to the first circulation loop. According to one embodiment, the processing system includes a process chamber for treating the substrate with the heated etching solution, a first circulation loop for providing the heated etching solution into the process chamber, and a second circulation loop for forming an additional heated etching solution and supplying the additional heated etching solution to the first circulation loop.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 6, 2018
    Assignee: TEL FSI, INC.
    Inventors: Kevin L Siefering, William P Inhofer
  • Patent number: 9875907
    Abstract: Methods of etching silicon nitride faster than silicon oxide are described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent gas-phase etch using anhydrous vapor-phase HF may then be used to selectively remove silicon nitride much faster than silicon oxide because the SAM has been found to delay the etch and reduce the etch rate.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: January 23, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Fei Wang, Mikhail Korolik, Nitin K. Ingle, Anchuan Wang, Robert Jan Visser
  • Patent number: 9859128
    Abstract: Methods of etching silicon nitride faster than silicon or silicon oxide are described. Methods of selectively depositing additional material onto the silicon nitride are also described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent exposure to an etchant or a deposition precursor may then be used to selectively remove silicon nitride or to selectively deposit additional material on the silicon nitride.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 2, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Fei Wang, Mikhail Korolik, Nitin K. Ingle, Anchuan Wang, Robert Jan Visser
  • Patent number: 9691607
    Abstract: Disclosed is a process for producing an epitaxial single-crystal silicon carbide substrate by epitaxially growing a silicon carbide film on a single-crystal silicon carbide substrate by chemical vapor deposition. The step of crystal growth in the process comprises a main crystal growth step, which mainly occupies the period of epitaxial growth, and a secondary crystal growth step, in which the growth temperature is switched between a set growth temperature (T0) and a set growth temperature (T2) which are respectively lower and higher than a growth temperature (T1) used in the main crystal growth step. The basal plane dislocations of the single-crystal silicon carbide substrate are inhibited from being transferred to the epitaxial film. Thus, a high-quality epitaxial film is formed.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: June 27, 2017
    Assignee: NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Takashi Aigo, Hiroshi Tsuge, Taizo Hoshino, Tatsuo Fujimoto, Masakazu Katsuno, Masashi Nakabayashi, Hirokatsu Yashiro
  • Publication number: 20150111390
    Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; providing a mixture of phosphoric acid and a silicon-containing material; and delivering the mixture to the surface of the wafer to remove the silicon nitride. Single wafer etching apparatuses of selectively removing silicon nitride are also provided.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Hsueh CHANGCHIEN, Yu-Ming LEE, Chi-Ming YANG
  • Publication number: 20150093906
    Abstract: A substrate treatment apparatus which can more efficiently regenerate phosphoric acid which is able to be returned to etching treatment along with such etching treatment as much as possible without using a large facility, that is a substrate treatment apparatus which treats a silicon substrate W on which a nitride film is formed by a liquid etchant which contains phosphoric acid, which comprises an etching treatment unit (the spin treatment unit 30) which gives a suitable quantity of liquid, etchant to each substrate which is fed one at a time so as to etch the substrate and remove the nitride film, a phosphoric acid regenerating unit (the spin treatment unit 30) which mixes liquid etchant used for treatment of one substrate and a suitable quantity of liquid hydrofluoric acid for the amount of the used liquid etchant under a predetermined temperature environment to regenerate the phosphoric acid, and a phosphoric acid recovery unit (the pump 38, phosphoric acid recovery tank 50, and pump 52) which returns the
    Type: Application
    Filed: September 19, 2014
    Publication date: April 2, 2015
    Applicant: SHIBAURA MECHATRONICS CORPORATION
    Inventors: Nobuo KOBAYASHI, Koichi HAMADA, Yoshiaki KUROKAWA, Masaaki FURUYA, Hideki MORI, Yasushi WATANABE, Yoshinori HAYASHI
  • Patent number: 8993425
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Zhang
  • Patent number: 8969218
    Abstract: Disclosed is a technique for attaining high etching selectivity of a silicon nitride film to a silicon oxide film. The etching method includes a step of supplying a silylating agent to a substrate having a silicon nitride film and a silicon oxide film exposed on the surface thereof to thereby form a silylated film as a protective film over the surface of the silicon oxide film. After this step, an etching solution is supplied to the substrate. It is thus possible to selectively etch only the silicon nitride film.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Tsukasa Watanabe, Keisuke Egashira, Miyako Kaneko, Takehiko Orii
  • Patent number: 8912099
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: December 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichiro Kurahashi, Yoshitaka Kamo, Yoshitsugu Yamamoto
  • Patent number: 8883653
    Abstract: An inventive substrate treatment method includes a silylation step of supplying a silylation agent to a substrate, and an etching step of supplying an etching agent to the substrate after the silylation step. The method may further include a repeating step of repeating a sequence cycle including the silylation step and the etching step a plurality of times. The cycle may further include a rinsing step of supplying a rinse liquid to the substrate after the etching step. The cycle may further include a UV irradiation step of irradiating the substrate with ultraviolet radiation after the etching step. The method may further include a pre-silylation or post-silylation UV irradiation step of irradiating the substrate with the ultraviolet radiation before or after the silylation step.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: November 11, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Akio Hashizume
  • Patent number: 8883033
    Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
  • Patent number: 8877653
    Abstract: A solvent vapor containing a solvent material capable of dissolving hydrogen fluoride is supplied to a surface of a substrate, thereby covering the surface of the substrate with a liquid film containing solvent material. Thereafter an etching vapor containing a hydrogen fluoride is supplied to the surface of the substrate covered by the liquid film containing the solvent material, thereby etching the surface of the substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 4, 2014
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takahiro Yamaguchi, Akio Hashizume, Yuya Akanishi, Takashi Ota
  • Patent number: 8846536
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Patent number: 8822346
    Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Kurt Weiner
  • Publication number: 20140187052
    Abstract: Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as silicon nitride and/or silicon oxide structures. Etching solutions and processing conditions described herein provide high etching selectivity of hafnium oxide relative to these other materials. As such, the hafnium oxide structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching selectivity of hafnium oxide relative to silicon oxide is at least about 10 and even at least about 30. Etching rates of hafnium oxide may be between 3 and 100 Angstroms per minute. A highly diluted water based solution of hydrofluoric acid, e.g., having a dilution ratio of 1000:1 to 10,000:1, may be used for etching to achieve these etching rates and selectivity levels. The solution may be maintained at a temperature of 25° C. to 90° C. during etching.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Applicant: Intermolecular Inc.
    Inventor: Gregory Nowling
  • Publication number: 20140179107
    Abstract: Provided are methods for processing semiconductor substrates or, more specifically, methods for etching silicon nitride structures without damaging photoresist structures that are exposed to the same etching solutions. In some embodiments, a highly diluted hydrofluoric acid is used for etching silicon nitride. A volumetric ratio of water to hydrofluoric acid may be between 1000:1 and 10,000:1. This level of dilution results in a low etching selectivity of photoresist to silicon nitride. In some embodiments, this selectivity is less than 0.2 and even less than 0.02. The solution may be kept at a temperature of between 60° C. and 90° C. to increase silicon nitride etching rates and to maintain high selectivity. The process may proceed until complete removal of the silicon nitride structure, while the photoresist structure may remain substantially intact.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: INTERMOLECULAR INC.
    Inventor: Gregory Nowling
  • Patent number: 8759232
    Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joerg Hohage, Hartmut Ruelke, Ralf Richter
  • Patent number: 8753969
    Abstract: A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 8741168
    Abstract: According to one embodiment, an etching method includes: supplying an etching-resistant material; and etching the silicon nitride film. The supplying includes supplying the etching-resistant material to a processing surface including a surface of a silicon nitride film and a surface of a non-etching film, the non-etching film including a material different from the silicon nitride film. The etching includes etching the silicon nitride film using an etchant in a state of the etching-resistant material being formed relatively more densely on the surface of the non-etching film than on the surface of the silicon nitride film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Yoshimizu, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 8716136
    Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Berthold Reimer, Johannes von Kluge, Sven Beyer
  • Patent number: 8716146
    Abstract: Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: May 6, 2014
    Assignee: Intermolecular, Inc
    Inventors: Gregory Nowling, John Foster
  • Patent number: 8709886
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140113455
    Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Berthold Reimer, Johannes von Kluge, Sven Beyer
  • Patent number: 8703005
    Abstract: A method for removing a plurality of dielectric materials from a supporting substrate by providing a substrate with a plurality of materials, contacting the substrate at a first temperature with a solution to more quickly remove a first dielectric material than a second dielectric material at the first temperature, and then contacting the substrate at a second temperature with a solution to more quickly remove the second dielectric material than the first dielectric material at the second temperature. Thus, the dielectric materials exhibit different etch rates when etched at the first and second temperatures. The solutions to which the first and second dielectric materials are exposed may contain phosphoric acid. The first dielectric material may be silicon nitride and the second dielectric material may be silicon oxide. Under these conditions, the first temperature may be about 175° C., and the second temperature may be about 155° C.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8642479
    Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: February 4, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20140011367
    Abstract: Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 9, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Gregory Nowling, John Foster
  • Patent number: 8623231
    Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: George Liu, Kuei Shun Chen, Vencent Chang, Chih-Yang Yeh
  • Patent number: 8580133
    Abstract: Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Berthold Reimer, Claudia Wolf
  • Publication number: 20130217235
    Abstract: A method and apparatus for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.
    Type: Application
    Filed: April 1, 2013
    Publication date: August 22, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Co., Ltd.
  • Patent number: 8513086
    Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 20, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Niraj Rana
  • Patent number: 8476165
    Abstract: A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: July 2, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Douglas M Trickett, Atsushi Yamashita
  • Patent number: 8470717
    Abstract: Methods of making current tracks for semiconductors are disclosed. The methods involve selectively depositing a hot melt ink resist containing rosin resins and waxes on a silicon dioxide or silicon nitride layer coating a semiconductor followed by etching uncoated portions of the silicon dioxide or silicon nitride layer with an inorganic acid etch to expose the semiconductor and simultaneously inhibit undercutting of the hot melt ink resist. The etched portions may then be metallized to form a plurality of substantially uniform current tracks.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: June 25, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Robert K. Barr, Hua Dong
  • Patent number: 8455367
    Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 ?m to ±100 ?m. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 4, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Naoki Matsumoto
  • Publication number: 20130122716
    Abstract: Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 16, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Berthold Reimer, Claudia Wolf
  • Patent number: 8435903
    Abstract: In one embodiment, a method for treating a surface of a semiconductor substrate is disclosed. The semiconductor substrate has a first pattern covered by a resist and a second pattern not covered by the resist. The method includes supplying a resist-insoluble first chemical solution onto a semiconductor substrate to subject the second pattern to a chemical solution process. The method includes supplying a mixed liquid of a water repellency agent and a resist-soluble second chemical solution onto the semiconductor substrate after the supply of the first chemical solution, to form a water-repellent protective film on a surface of at least the second pattern and to release the resist. In addition, the method can rinse the semiconductor substrate using water after the formation of the water-repellent protective film, and dry the rinsed semiconductor substrate.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Ogawa, Shinsuke Kimura, Tatsuhiko Koide, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 8409997
    Abstract: A method and system for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: April 2, 2013
    Assignee: Taiwan Semiconductor Maufacturing Co., Ltd.
    Inventors: Zin-Chang Wei, Tsung-Min Huang, Ming-Tsao Chiang Chiang, Cheng-Chen Calvin Hsueh
  • Publication number: 20130065400
    Abstract: According to one embodiment, an etching method includes: supplying an etching-resistant material; and etching the silicon nitride film. The supplying includes supplying the etching-resistant material to a processing surface including a surface of a silicon nitride film and a surface of a non-etching film, the non-etching film including a material different from the silicon nitride film. The etching includes etching the silicon nitride film using an etchant in a state of the etching-resistant material being formed relatively more densely on the surface of the non-etching film than on the surface of the silicon nitride film.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 14, 2013
    Inventors: Yasuhito Yoshimizu, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 8372299
    Abstract: A method and apparatus for performing treatment of substrates with a treating liquid. A first storage unit stores an initial life count specifying an allowable number of treatments of substrates to be carried out with treating liquid after an entire liquid replacement with a new supply of the treating liquid; a second storage device stores a normal life count specifying an allowable number of treatments to be carried out with the treating liquid after reaching the initial life count and after a partial liquid replacement; and a control device repeats treatment of the substrates after the entire liquid replacement until the initial life count is reached; and after the initial life count has been reached and the partial liquid replacement has been made, repeats treatment of the substrates until the normal life count is reached, and makes the partial liquid replacement each succeeding time the normal life count is reached.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 12, 2013
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Yasunori Nakajima, Yusuke Mori
  • Publication number: 20130029495
    Abstract: A method to remove excess material during the manufacturing of semiconductor devices includes providing a semiconductor wafer comprising silicon nitride deposited thereon and applying a chemical solution to the semiconductor wafer, wherein the chemical solution comprises a combination of sulfuric acid and deionized water.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: INTERMOLECULAR, INC.
    Inventor: Edwin Adhiprakasha
  • Publication number: 20120289056
    Abstract: Methods and etchant solutions for etching silicon nitride on a workpiece are provided. One method generally includes exposing the workpiece to a chemistry mixture including phosphoric acid and a diluent, wherein the chemistry mixture has a water content of less than 10% by volume, and heating at least one of the workpiece and the chemistry mixture to a process temperature to etch silicon nitride from the workpiece.
    Type: Application
    Filed: April 20, 2012
    Publication date: November 15, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Eric J. Bergman, Jerry Dustin Leonhard
  • Publication number: 20120264308
    Abstract: Disclosed is a technique for attaining high etching selectivity of a silicon nitride film to a silicon oxide film. The etching method includes a step of supplying a silylating agent to a substrate having a silicon nitride film and a silicon oxide film exposed on the surface thereof to thereby form a silylated film as a protective film over the surface of the silicon oxide film. After this step, an etching solution is supplied to the substrate. It is thus possible to selectively etch only the silicon nitride film.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 18, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Tsukasa WATANABE, Keisuke Egashira, Miyako Kaneko, Takehiko Orii
  • Patent number: 8283260
    Abstract: A method for preparing an interlayer dielectric to minimize damage to the interlayer's dielectric properties, the method comprising the steps of: depositing a layer of a silicon-containing dielectric material onto a substrate, wherein the layer has a first dielectric constant and wherein the layer has at least one surface; providing an etched pattern in the layer by a method that includes at least one etch process and exposure to a wet chemical composition to provide an etched layer, wherein the etched layer has a second dielectric constant, and wherein the wet chemical composition contributes from 0 to 40% of the second dielectric constant; contacting the at least one surface of the layer with a silicon-containing fluid; optionally removing a first portion of the silicon-containing fluid such that a second portion of the silicon-containing fluid remains in contact with the at least one surface of the layer; and exposing the at least one surface of the layer to UV radiation and thermal energy, wherein the lay
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: October 9, 2012
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Scott Jeffrey Weigel, Mark Leonard O'Neill, Mary Kathryn Haas, Laura M. Matz, Glenn Michael Mitchell, Aiping Wu, Raymond Nicholas Vrtis, John Giles Langan
  • Patent number: 8221642
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8222153
    Abstract: A method for fabricating a textured single crystal including depositing pads made of metal on a surface of a single crystal. A protective layer is deposited on the pads and on the single crystal between the pads; and etching the surface with a first compound that etches the metal more rapidly than the protective layer is carried out. Processing continues with etching the surface with a second compound that etches the single crystal more rapidly than the protective layer; and etching the surface with a third compound that etches the protective layer more rapidly than the single crystal. The textured substrate may be used for the epitaxial growth of GaN, AlN or III-N compounds (i.e. a nitride of a metal the positive ion of which carries a +3 positive charge) in the context of the fabrication of LEDs, electronic components or solar cells.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: July 17, 2012
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Fabien Lienhart, Guillaume Lecamp, François-Julien Vermersch
  • Patent number: 8216434
    Abstract: A micromachined sensor for measuring vascular parameters, such as fluid shear stress, includes a substrate having a front-side surface, and a backside surface opposite the front-side surface. The sensor includes a diaphragm overlying a cavity etched within the substrate, and a heat sensing element disposed on the front-side surface of the substrate and on top of the cavity and the diaphragm. The heat sensing element is electrically couplable to electrode leads formed on the backside surface of the substrate. The sensor includes an electronic system connected to the backside surface and configured to measure a change in heat convection from the sensing element to surrounding fluid when the sensing element is heated by applying an electric current thereto, and further configured to derive from the change in heat convection vascular parameters such as the shear stress of fluid flowing past the sensing element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 10, 2012
    Assignee: University of Southern California
    Inventors: Tzung K. Hsiai, Gopikrishnan Soundararajan, Eun Sok Kim, Hongyu Yu, Mahsa Rouhanizadeh, Christina Tiantian Lin
  • Patent number: 8188447
    Abstract: A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: May 29, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ru Yang, Chyi Shyuan Chern, Soon Kang Huang
  • Patent number: 8187487
    Abstract: A method for removing (e.g., etching) different dielectric materials from a semiconductor substrate includes exposing the semiconductor substrate to a solution at temperatures below and at or above a set threshold. Below the threshold temperature, the solution removes one dielectric material (e.g., silicon nitride) faster than it removes another, different dielectric material (e.g., silicon oxide). At or above the threshold temperature, the selectivity of the solution is reversed.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Patent number: 8183163
    Abstract: An etching liquid used for selectively etching silicon nitride, the etching liquid includes: water; a first liquid that can be mixed with the water to produce a mixture liquid having a boiling point of 150° C. or more; and a second liquid capable of producing protons (H+). Alternatively, an etching liquid includes: water; phosphoric acid; and sulfuric acid, the phosphoric acid and the sulfuric acid having a volume ratio of 300:32 to 150:300.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Eguchi, Naoya Hayamizu, Hiroyuki Fukui
  • Patent number: 8173532
    Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Wong, Haining S. Yang
  • Patent number: 8148175
    Abstract: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisashi Okuchi