Abstract: A method of reducing the critical dimension (CD) of a hard mask by a wet etch method is described. An oxide hard mask is treated with a H2SO4/H2O2 (SPM) solution followed by treatment with a NH4OH/H2O2/H2O (APM) solution to trim the CD by 0 to 20 nm. With nitride or oxynitride hard masks, a buffered HF dip is inserted prior to the SPM treatment. For oxide hard masks, the SPM solution performs the etch while APM solution assists in removing plasma etch residues. With oxynitride hard masks, the APM performs the etch while BHF and SPM solutions remove plasma etch residues. The hard mask pattern can then be transferred with a dry etch into an underlying polysilicon layer to form a gate length of less than 150 nm while controlling the CD to within 3 to 5 nm of a targeted value.

Abstract: A semiconductor device manufacturing method that assures required size of flat areas at a wiring overlay nitride film, and forms an SAC structure wherein selectivity is not lowered at corners. A first etching process wherein an insulating film is etched under conditions for forming a vertical opening (vertical conditions) is used to open up the insulating film to a point near the wiring overlay nitride film 105. A second etching process is used wherein the insulating film is opened until the wiring overlay nitride film becomes exposed, by etching under conditions assuring a high ratio of selectivity relative to the wiring overlay nitride film (SAC conditions). Then, a third etching process is used wherein the insulating film located between first and second electrodes is removed by etching under conditions with a low ratio of selectivity relative to the wiring overlay nitride film (SAC conditions).

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: A method of manufacturing a semiconductor device includes providing a wafer substrate having a surface, forming a first nitride layer over the wafer substrate, providing a layer of photoresist over the first nitride layer, patterning and defining the photoresist layer, etching the first nitride layer unmasked by the photoresist to remove at least a portion of the first nitride layer to expose at least a portion of the substrate surface, removing the photoresist layer, and depositing a second nitride layer over the first nitride layer and the exposed substrate surface to form a nitride structure having a first thickness and a second thickness, wherein the first thickness includes a thickness of the first nitride layer.

Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: Methods and devices for mechanical and/or chemical-mechanical polarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of plagiarizing a micro electronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a plagiarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the plagiarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the plagiarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor, which can reduce the junction capacitance without degradation of transistor characteristics including forming a buffer oxide layer on a semiconductor substrate; successively conducting ion implantations for well formation and field stop formation in the substrate through the buffer oxide layer; removing the buffer oxide layer; forming and patterning a sacrificial layer to form a trench successively conducting ion implantations for threshold voltage adjustment and punch stop formation on the semiconductor substrate area exposed by the trench; forming a gate oxide layer on the exposed surface of the substrate; forming a polysilicon layer so as to completely fill the trench; polishing the polysilicon layer to form a gate electrode; removing the sacrificial layer; forming an LDD region in the substrate; forming spacers on side walls of the gate electrode; and forming source/drain regions.

Abstract: A method for forming a dielectric film in a PDP includes the steps of: reducing the ambient pressure of an insulating film including a dielectric material before the ambient temperature reaches the reaction temperature of the dielectric material; introducing heated gas to increase the ambient pressure up to the atmospheric pressure while maintaining the ambient temperature at the reaction temperature; and lowering the ambient temperature down to the solidifying temperature of the insulating film while maintaining the atmospheric ambient pressure.

Abstract: According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).

Abstract: A method for the production of semiconductor components which includes applying masking layers and components on epitaxial semiconductor substrates within the epitaxy reactor without removal of the substrate from the reactor. At least one of the masking layers is HF soluble such that a gas etchant may be introduced within the reactor so as to etch a select number and portion of masking layers. This method may be used for production of lateral integrated components on a substrate wherein the components may be of the same or different type. Such types include electronic and optoelectronic components. Numerous masking layers may be applied, each defining particular windows intended to receive each of the various components. In the reactor, the masks may be selectively removed, then the components grown in the newly exposed windows.

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

Abstract: In a method for removing a nitride layer of a semiconductor device, an etchant including about 15 to about 40 percent by volume of hydrofluoric acid, about 15 to about 60 percent by volume of phosphorous acid, and about 25 to about 45 percent by volume of deionized water is prepared. The etchant is provided onto a nitride layer that is formed on a bevel, a front side or a backside of a substrate to remove the nitride layer. The substrate is rinsed using deionized water, and then the substrate is dried. The etchant rapidly removes the nitride layer at a relatively low temperature to avoid damage to the substrate.

Abstract: Methods and apparatuses for forming an oxide film. The method includes depositing an oxide film on a substrate using a process gas mixture that comprises a silicon source gas, an oxygen gas, and a hydrogen gas, and a process temperature between 800° C. and 1300° C. During the deposition of the oxide film, the process gas mixture comprises less than 6% oxygen, silicon gas, and predominantly hydrogen.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.

Abstract: A method for removing a silicon nitride film from a wafer is described. A wafer is provided having a silicon nitride film formed thereon, wherein the silicon nitride film exposes portions of the wafer surface. To remove the silicon nitride film, the wafer is put into an etching tank, into which phosphoric acid and an additive containing an oxidant have been introduced. During the removing process, an oxidation film is simultaneously formed on the portion of the wafer exposed by the silicon nitride film to protect the exposed portion from being damaged.

Abstract: A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

Abstract: The invention concerns etching and doping substances free of hydrochloric/fluoride acid used for etching inorganic layers as well as for doping subjacent layers. The invention also concerns a method wherein said substances are used.

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching.

Abstract: A method for protecting a gate stack in an integrated circuit wafer involves the deposition of a thin nucleation or seed layer of silicon nitride on the gate stack. Following deposition of the nucleation layer, a second, primary layer of silicon nitride is formed on the nucleation layer using a BTBAS precursor to thereby form a spacer film. The primary layer may have carbon incorporated therein.

Abstract: A method of manufacturing a semiconductor device having a metal conducting layer is provided. A metal conducting layer pattern having the metal conducting layer is formed on a semiconductor substrate. A portion of the metal conducting layer is partially exposed on the semiconductor substrate. The semiconductor substrate having the metal conducting layer pattern is loaded into a reaction chamber. A first silicon source gas is flowed into the reaction chamber. A silicon oxide layer is formed on the semiconductor substrate having the metal conducting layer pattern by supplying a second silicon source gas and an oxygen source gas into the reaction chamber.

Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Abstract: A new method of creating a relatively thick layer of PE silicon nitride. A conventional method of creating a layer of silicon nitride applies a one-step process for the creation thereof. Film stress increases as the thickness of the created layer of PE silicon nitride increases. A new method is provided for the creation of a crack-resistant layer of PE silicon nitride by providing a multi-step process. The main processing step comprises the creation of a relatively thick, compressive film of PE silicon nitride, over the surface of this relatively thick layer of PE silicon nitride is created a relatively thin (between about 150 and 500 Angstrom) layer of tensile stress PE silicon nitride. This process can be repeated to create a layer of PE silicon nitride of increasing thickness.

Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A semiconductor device includes an n-type semiconductor substrate including a source region and a drain region in a main surface thereof, a high-permittivity insulator film including a high permittivity material and formed to cover an upper side of a region of the main surface of n-type semiconductor substrate, which region is interposed between source region and drain region. And the semiconductor device includes a boron-doped gate electrode formed above high-permittivity insulator film, and a high-permittivity nitride layer formed between high-permittivity insulator film and boron-doped gate electrode.

Abstract: A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. A photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor.

Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.

Abstract: A method for forming a shallow trench isolation using a SiON anti-reflective coating which eliminates water spot defects. The method begins by providing a substrate. A pad oxide layer is formed over the substrate. A silicon nitride layer is formed on the pad oxide layer. A silicon oxynitride layer is formed on the silicon nitride layer. A photoresist mask, having an opening, is formed over the silicon oxynitride layer. The silicon oxynitride layer, the silicon nitride layer, the pad oxide layer, and the substrate are etched through the opening, forming a trench. The photoresist mask is removed. In the key step, the silicon oxynitride layer is removed. Then, a thin silicon oxide layer is grown and a silicon oxide layer is deposited and planarized to form a shallow trench isolation.

Abstract: A method for forming aluminum bumps by first sputter aluminum and then chemical mechanical polishing to remove excess aluminum is disclosed. In the method, a pre-processed electronic substrate which has a plurality of I/O pads formed on top is first provided. An insulating material layer such as SiO2, Si3N4, SOG or polyimide is then deposited on the pads to a thickness that is essentially the thickness of the aluminum bumps to be formed. A plurality of openings with one on each of the plurality of I/O pads is then photolithographically formed, followed by a sputtering deposition to fill the plurality of openings with a metal that includes aluminum. A chemical mechanical polishing technique is then used to remove the excess aluminum so that a top surface of the aluminum bump is flush with the top surface of the insulating material layer, followed by the final step of removing at least partially a thickness of the insulating material layer by a wet etch process.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.

Abstract: Embodiments of the present invention are directed to a method of forming a bottom oxide layer in a trench on a semiconductor substrate. In one embodiment, a method for forming a bottom oxide layer in a trench on a semiconductor substrate comprises depositing an oxide layer along the surface of the sidewall and the bottom of a trench on a semiconductor substrate which has top layers, depositing a nitride layer along the surface of the said oxide layer, and forming a photo-resist filler in a trench. The top surface of the photo-resist filler is lower than the top surface of the substrate to expose a portion of the nitride layer uncovered by the photo-resist filler. The exposed portion of the nitride layer is removed to expose the oxide layer underneath. A portion of the oxide layer on the sidewalls of a trench is removed to form a bottom oxide layer in a trench.

Abstract: A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.

Abstract: A method of forming a shallow trench isolation type semiconductor device comprises forming an etch protecting layer pattern to define at least one active region on a substrate, forming at least one trench by etching the substrate partially by using the etch protecting layer pattern as an etch mask, forming a thermal-oxide film on an inner wall of the trench, filling the trench having the thermal-oxide film with a CVD silicon oxide layer to form an isolation layer, removing the etch protecting layer pattern from the substrate over which the isolation layer is formed, removing the thermal-oxide film formed on a top end of the inner wall of the trench to a depth of 100 to 350 Å, preferably 200 Å from the upper surface of the substrate, and forming a gate oxide film on the substrate from which the active region and the top end are exposed.

Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layer and a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed in a high temperature process after the trench is filled with an insulative material. The insulative material is provided in a low temperature process.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Nanopores for single-electron devices may be used as templates for placing of a desired number of nanoparticles at a desired location in the devices. Nanopores may be fabricated by providing on a substrate spaced apart electrode regions, a spacer region therebetween, and a cover layer on the spaced apart electrode regions and on the spacer region. A wet etching solution is contacted to the cover layer. At least one of the spaced apart electrode regions is energized, to selectively wet etch the cover layer adjacent the spacer region and define a nanopore in the cover layer adjacent the spacer region. At least one nanoparticle is placed in the nanopore. Accordingly, nanopores can be aligned to a buried spacer region.

Abstract: A semiconductor device and method for manufacturing the same in which the semiconductor device includes a substrate; an MOS transistor formed on the substrate; an interlayer dielectric provided on at least a portion of the MOS transistor; a hydrogen occluding material which is an interstitial hydrogen occluding compound, which is provided on the interlayer dielectric, and which is employed as a wire by being disposed in the vicinity of the top of the MOS transistor; and a ferroelectric capacitor which has a height which is greater than that of the MOS transistor, wherein the hydrogen occluding material is placed between the MOS transistor and the ferroelectric capacitor.

Abstract: A method of forming a dielectric structure for a flash memory cell includes forming a first layer of silicon dioxide, forming a layer of silicon nitride on the first layer of silicon dioxide, and pretreating the silicon nitride layer. Pretreatment of the silicon nitride layer includes nitridation. The method further includes depositing a second layer of silicon dioxide on the pretreated silicon nitride layer. Nitridation of the silicon nitride can occur in a batch process or in a single wafer tool, such as a single wafer rapid thermal anneal (RTA) tool. The nitriding pretreatment of the nitride layer improves the integrity of the ONO structure and enables the second layer of silicon dioxide to be deposited rather than thermally grown. Because the nitride layer undergoes less change after deposition of the second layer of silicon dioxide, the present method improves the overall reliability of the ONO structure.

Abstract: A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

Abstract: A multilayer semiconductor device that includes a metal-insulator-metal (MIM) capacitor including a first metal plate, a dielectric layer, and a second metal plate, a nitride etchstop layer formed above the MIM capacitor, a first interlayer dielectric formed on the nitride etchstop layer, and a first via and a second via that extend through at least the first interlayer dielectric to contact the nitride etchstop layer.

Abstract: To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

Abstract: A method of forming a trench type isolation layer is provide, wherein the method comprises: forming a trench by etching after forming a trench etching pattern on a substrate; forming a silicon nitride liner on an inner wall of the trench; filling the trench with a first buried oxide layer; exposing an upper part of the liner of the trench by recessing the first buried oxide layer using a wet process; removing the upper part of the silicon nitride liner using isotropic etching; and filling the recessed space of the trench with a second buried oxide layer. The method may further comprise: forming the trench etching pattern by depositing and patterning a silicon nitride layer, and forming a thermal oxide layer, preferably through annealing, for healing etching defects on an inner wall of the trench, between forming the trench and forming the liner.