Abstract: An etching liquid used for selectively etching silicon nitride, the etching liquid includes: water; a first liquid that can be mixed with the water to produce a mixture liquid having a boiling point of 150° C. or more; and a second liquid capable of producing protons (H+). Alternatively, an etching liquid includes: water; phosphoric acid; and sulfuric acid, the phosphoric acid and the sulfuric acid having a volume ratio of 300:32 to 150:300.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

Abstract: An apparatus and a method for stripping silicon nitride are disclosed that facilitate automatic, real-time, and exact measurement of etch rate and an ending time of the etching process when silicon nitride is stripped with phosphoric acid solution. The method for stripping silicon nitride includes the steps of: a) measuring initial concentration of a specific ion in a phosphoric acid solution contained in a reactor, b) dipping a silicon nitride-formed substrate into the phosphoric acid solution in the reactor, c) measuring instantaneous concentration of the specific ion in stripping solution extracted from the reactor when silicon nitride stripping is processed in the reactor, and d) finishing the silicon nitride stripping process if variation rate of the measured instantaneous concentration is not exceeding a predetermined standard, or returning to the step c) if the variation rate is more than the predetermined standard.

Abstract: A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: An isolation method in a semiconductor device is disclosed. The example method sequentially forms a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride and oxide layers to form an opening exposing a portion of the substrate, and forms a trench in exposed portion of the substrate. The example method also etches the patterned pad nitride layer to extend the opening, carries out SAC oxidation on the extended opening and the trench to provide a rounded corner to an upper corner of the substrate in the vicinity of the trench, and fills the trench with an insulating layer.

Abstract: A regeneration process is disclosed for an etching solution composed of a phosphoric acid solution and used in etching silicon nitride films in an etch bath. As a result of the etching, the etching solution contains a silicon compound. According to the regeneration process, the etching solution with a silicon compound contained therein is taken out of the etch bath. Water is then added to the taken-out etching solution to lower a concentration of phosphoric acid in the etching solution to 80 to 50 wt. %. By the lowing of the concentration of phosphoric acid, the silicon compound is caused to precipitate. The thus-precipitated silicon compound is removed from the etching solution. An etching process making use of the regeneration process and an etching system suitable for use in practicing the regeneration process and etching process are also disclosed.

Abstract: An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid or salt thereof, and at least one antimicrobial agent resulting in a cleaning composition in which microbial growth is inhibited. Examples of suitable antimicrobial agents include a benzoic acid or salt such as potassium or ammonium benzoate, and sorbic acid or salt such as potassium sorbate. The composition is useful for cleaning a wafer and particularly for removing residual particles after a conductive layer has been planarized to a dielectric layer under the conductive layer in a chemical mechanical planarization of a semiconductor wafer with abrasive slurry particles, particularly after a CMP of copper or aluminum films.

Abstract: A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.

Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. A minute pattern is formed using a hard mask film of a series of a nitride film as an etch mask. Before a hard mask film removal process is performed, the step of performing given etching using an oxide film etchant is added to remove an abnormal oxide film on the nitride film. It is thus possible to effectively remove the hard mask film. Generation of voids in a pattern below the hard mask film can be also effectively prevented using BOE in which the composition ratio of HF and NH4F and an etching temperature are optimized as an oxide film etchant.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.

Abstract: A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

Abstract: A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing the resist film so as to form a prescribed circuit pattern in the resist film. Then, the wafer W is etched so as to form a via hole in the porous low-k film, followed by processing the wafer with a hydrogen peroxide solution so as to denature the resist film. Further, the sacrificial film is dissolved in a pure water so as to strip the resist film and the antireflection film from the water. As a result, a via hole excellent in the accuracy of the shape is formed without doing damage to the dielectric film.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method of fabricating the same are disclosed. In a complementary metal-oxide semiconductor (CMOS) image sensor including a photodiode receiving irradiated light and generating electric charges, a plurality of conductive circuits each formed in different layers, a plurality of interlayer dielectrics insulating the conductive circuits, and a micro-lens formed of the interlayer dielectrics and focusing the irradiated light to the photodiode, the CMOS image sensor includes a lens formed in a dome shape on any one of the interlayer dielectrics and re-focusing the light focused by the micro-lens to the photodiode.

Abstract: A method and composition for removing silicon-containing sacrificial layers from Micro Electro Mechanical System (MEMS) and other semiconductor substrates having such sacrificial layers is described. The etching compositions include a supercritical fluid (SCF), an etchant species, a co-solvent, and optionally a surfactant. Such etching compositions overcome the intrinsic deficiency of SCFs as cleaning reagents, viz., the non-polar character of SCFs and their associated inability to solubilize polar species that must be removed from the semiconductor substrate. The resultant etched substrates experience lower incidents of stiction relative to substrates etched using conventional wet etching techniques.

Abstract: The present invention relates to a method for fabricating a semiconductor device. In more detail of the aforementioned method, a first mask layer covering a cell region is formed on an insulation layer in the cell region. Meanwhile, a second mask layer is formed in a peripheral circuit region with a predetermined distance from the first mask layer. The insulation layer is then etched with use of the first and the second mask layers as an etch mask to form a spacer at both sidewalls of each gate line pattern in the peripheral region and simultaneously form a guard beneath the second mask layer. The first and the second mask layers are removed thereafter. Next, a third mask layer opening the cell region but covering the whole regions including a guard region in the peripheral circuit region is formed. A wet etching process is performed to the insulation layer remaining in the cell region by using the third mask layer as an etch mask.

Abstract: In a method for removing a nitride layer of a semiconductor device, an etchant including about 15 to about 40 percent by volume of hydrofluoric acid, about 15 to about 60 percent by volume of phosphorous acid, and about 25 to about 45 percent by volume of deionized water is prepared. The etchant is provided onto a nitride layer that is formed on a bevel, a front side or a backside of a substrate to remove the nitride layer. The substrate is rinsed using deionized water, and then the substrate is dried. The etchant rapidly removes the nitride layer at a relatively low temperature to avoid damage to the substrate.

Abstract: A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1–30 atomic % of chlorine.

Abstract: The present invention relates to a gate structure of a flash memory cell and method of forming the same, and method of forming a dielectric film.

Abstract: A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32).

Abstract: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.

Abstract: An improved method of manufacturing a capacitor on a semiconductor substrate is disclosed. A portion of an insulation film on a semiconductor substrate is etched to form a first opening in the insulation film. A passivation film is formed on the insulation film and within the first opening thereof. A portion of the passivation film on a bottom of the first opening is thinner than portions of the passivation film on the insulation film and on a sidewall of the first opening. The passivation film is etched to expose the bottom of the first opening.

Abstract: A method of manufacturing a flash memory device includes the steps of forming a nitride film on an entire surface of a trench by means of an annealing process to prevent implanted ions for adjusting a threshold voltage from diffusing to a device isolation region, and forming a side wall oxide film on a surface of the nitride film. The nitride film plays a role of preventing ions implanted into a substrate for adjusting a threshold voltage from flowing into the side wall oxidation film.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.

Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.

Abstract: A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an oxide of aluminum. The silicon nitride and the oxide is exposed to an etching solution comprising HF and an organic HF solvent under conditions effective to etch the silicon nitride substantially selectively relative to the oxide. Other aspects and implementations are contemplated.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the dielectric layer. A patterned masking layer with an opening is formed overlying the polysilicon layer. Through the opening, the polysilicon layer is oxidized to form a first silicon oxide layer at the bottom of the opening. Thereafter the masking layer is removed and the polysilicon layer is exposed. The exposed polysilicon layer is then etched through using the first silicon oxide layer as a mask to form MOS floating gates. The first silicon oxide layer is then removed. A second conductor layer is then deposited overlying the MOS floating gates for forming control gates.

Abstract: A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semiconductor substrate is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate is greater than the etching amount with respect to the insulating layer, and the conductive portion is caused to project while covered by the insulating layer. At least a portion of the insulating layer formed on the bottom surface of the depression is etched with a second etchant having characteristics such that at least the insulating layer is etched without forming a residue on the conductive portion, to expose the conductive portion.

Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: A method for wet etching a metal nitride containing layer overlying a silicon oxide containing layer in a semiconductor device or micro-electro-mechanical device manufacturing process including providing a substrate including a silicon oxide containing layer and an overlying exposed metal nitride containing layer; providing a wet etching solution including phosphoric acid and water; adding a silicon containing compound which undergoes a hydrolysis reaction in the wet etching solution; and, contacting the exposed metal nitride containing layer with the wet etching solution for a period of time to remove the metal nitride containing layer.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.

Abstract: A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 ?.

Abstract: Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl?, NO3? and F?. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In a disclosed example, a multi-layered insulating structure is deposited on a semiconductor substrate, an opening is formed in the multi-layered insulating structure above the semiconductor substrate, and a trench is formed in the semiconductor substrate under the opening. Then, a groove is formed on an edge position of an intermediate layer of the multi-layered insulating structure by wet-etching the intermediate layer of the multi-layered insulating layer transversely using a pull back process. Then, a liner oxide layer is deposited on the groove and the trench. An oxide layer then fills the trench and the groove without generating voids or divots in the oxide layer of the trench.

Abstract: A process for fabricating a dual damascene structure of copper has been developed. This process uses a thin nitride spacer, approximately 100 Angstroms thick, at the bottom of the via, thus preventing recessed nitride during the resist stripping process.

Abstract: An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalline silicon and an underlying layer of silicon nitride. After being used to pattern the polycrystalline silicon and silicon nitride, the anti-reflective coating is removed in a solution of hot phosphoric acid with the removal taking place before the silicon oxynitride is exposed to any elevated temperatures.

Abstract: A plasma etching method is performed by plasma etching an SiN layer through a mask layer to form a first wiring portion and a second wiring portion, the first and the second wiring portions having different wiring densities in the etched SiN layer, the mask having two pattern portions respectively corresponding to the first and the second wiring portions. In the plasma etching step, by using an etching gas including fluorocarbon and C2H2F4, the line width variation between the first and the second wiring portions is restrained.

Abstract: A storage capacitor has a double cylinder type structure, with a small cylinder in a lower part thereof and a cylindrical lower electrode structure disposed on the cylindrical contact plug. A method of fabricating the storage capacitor includes: forming a contact hole for exposing an activation region of a transistor; depositing a conductive film to form within the contact hole a contact plug of the storage capacitor having a void therein; opening an upper part of the void of the contact plug; and covering a surface of the device with material to form the storage capacitor electrode, to obtain the storage capacitor electrode having a double cylindrical structure.

Abstract: An antireflective coating (ARC) layer for use in the manufacture of a semiconductor device. The ARC layer has a bottom portion that has a lower percentage of silicon than a portion of the ARC layer located above it. The ARC layer is formed on a metal layer, wherein the lower percentage of silicon of the ARC layer inhibits the unwanted formation of suicides at the metal layer/ARC layer interface. In some embodiments, the top portion of the ARC layer has a lower percentage of silicon than the middle portion of the ARC layer, wherein the lower percentage of silicon at the top portion may inhibit the poisoning of a photo resist layer on the ARC layer. In one embodiment, the percentage of silicon can be increased or decreased by decreasing or increasing the ratio of the flow rate of a nitrogen containing gas with respect to the flow rate of a silicon containing gas during a deposition process.

Abstract: A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure.

Abstract: The invention relates to a method of manufacturing a semiconductor device comprising the step of removing a silicon and nitrogen containing material by means of wet etching with an aqueous solution comprising hydrofluoric acid in a low concentration, the aqueous solution being applied under elevated pressure to reach a temperature above 100° C.

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized.