Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.

Abstract: A silicon oxide layer is produced by plasma enhanced oxidation of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. Films having low moisture content and resistance to cracking are deposited by introducing oxygen into the processing chamber at a flow rate of less than or equal to the flow rate of the organosilicon compounds, and generating a plasma at a power density ranging between 0.9 W/cm2 and about 3.2 W/cm2. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. The organosilicon compound preferably has 2 or 3 carbon atoms bonded to each silicon atom, such as trimethylsilane, (CH3)3SiH. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.

Abstract: A method of reproducibly manufacturing circuit carriers with very fine circuit structures, more specifically with structure widths of 50 &mgr;m and less, is described in which a substrate provided with a base metal surface is provided, a layer of varnish is applied onto the substrate by an electrophoretic method, the layer of varnish is ablated in at least parts of the regions that do not correspond to the metal pattern to be formed, the base metal surface being laid bare, the bare base metal surface is etched, the layer of varnish being ablated by means of ultraviolet irradiation, more specifically with an ultraviolet laser beam.

Abstract: A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.

Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

Abstract: A method of forming a frontside contact to a Silicon-On-Insulator (SOI) wafer is described. A connection polysilicon connects a silicon substrate layer to a contact plug. This connection provides a means to ground or bias the bottom substrate of the SOI wafer. Spacers may be added to provide additional doping.

Abstract: A process for improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: Methods are provided for removing edge beads from spin-on films. A spin-on film is removed from a region of a surface of a spin-coated substrate adjacent to an edge of the surface by spinning the spin-coated substrate, expanding a fluid through a nozzle to form a cryogenic aerosol stream, and directing the cryogenic aerosol stream against the spin-on film in the region as the substrate spins. In another aspect of the invention, a film is formed on a surface of a substrate by dispensing a liquid composition onto the surface, spinning the substrate to distribute the liquid composition to form a substantially uniform film on the surface, expanding a fluid through a nozzle to form a cryogenic aerosol stream, and directing the cryogenic aerosol stream against the film in a region of the surface adjacent to an edge of the surface as the substrate spins. The film may include an alkoxysilane and a low volatility solvent. The fluid may consists essentially of liquid carbon dioxide.

Abstract: Polymer features may be formed on a substrate by applying a polymer to a photoresist pattern which is subsequently removed to generate the desired polymer features.

Abstract: A switching element is formed by sequentially depositing on an insulating substrate a gate electrode, a gate insulating film made of an inorganic insulating film, a semiconductor layer, a channel protecting layer, an n+Si layer that will form a source electrode and a drain electrode. Next, a metal layer and a transparent conductive film are formed on edges of the source electrode and the drain electrode. The insulating substrate on which the above films have been deposited is cleaned with vacuum ultraviolet light, before further depositing an interlayer insulating film and a pixel electrode. A substrate for use in a display element obtained in this manner exhibits an excellent adhesion strength between the film processed with vacuum ultraviolet light and a film adjacent to the film processed with vacuum ultraviolet light.

Abstract: The present invention pertains to apparatus and methods for maintaining wafer back side, bevel, and front side edge exclusion during supercritical fluid processing. Apparatus of the invention include a pedestal and an exclusion ring. When the exclusion ring is engaged with the pedestal a channel is formed. A reactant-free supercritical fluid is passed through the channel and over a circumferential front edge of a wafer. The flow of reactant-free supercritical fluid protects the bevel and circumferential front edge of the wafer from exposure to reactants in a supercritical processing medium. The back side of the wafer is protected by contact with the pedestal and the flow of reactant-free supercritical fluid. Exclusion rings of the invention, when engaged with their corresponding pedestals make no or very little physical contact with the wafer front side.

Abstract: A method and a circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical polishing process. On the substrate, the circuit layout comprises a plurality of strips of first circuit structure and at least two strips of second circuit structure located on the substrate. Each of the strips of second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure for the purpose of averaging polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during the chemical mechanical polishing process for reducing defects.

Abstract: A method for decreasing the mass and increasing the strength of an IC wafer assembly involves adding a polymer coating to the frontside of the wafer assembly to protect and strengthen the assembly, and removing silicon material from the backside of the wafer assembly, reducing the overall thickness of the assembly. The removal can be by backgrinding or by many other removal techniques, and in some cases is removed to a thickness less than that of the polymer coating.

Abstract: Method of forming a metal pattern on a dielectric substrate A method of reproducibly manufacturing circuit carriers with very fine circuit structures, more specifically with structure widths of 50 &mgr;m and less, is described in which a substrate provided with a base metal surface is provided, a layer of varnish is applied onto the substrate by an electrophoretic method, the layer of varnish is ablated in at least parts of the regions that do not correspond to the metal pattern to be formed, the base metal surface being laid bare, the bare base metal surface is etched, the layer of varnish being ablated by means of ultraviolet irradiation, more specifically with an ultraviolet laser beam.

Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.

Abstract: Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Abstract: An organically modified dielectric network structure (208) and solid halide-containing material (206) are co-deposited using a chemical vapor deposition process. The solid halide-containing material (206) is then sublimated leaving a porous dielectric (212). An encapsulating layer (210) is formed over the porous dielectric (212) to seal any remaining halide-containing material Within the porous dielectric (212).

Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.

Abstract: A method for removing a photoresist layer on wafer edge is disclosed. The invention uses a light source located under a spin on coated wafer mounted on a supporting mean of a rotatable chuck to expose the photoresist material on the wafer edge. First of all, the spin on coated wafer is mounted on the supporting mean of the rotatable chuck. Then the rotatable chuck is rotated and the wafer is exposed to the light source. Finally, the wafer is developed.

Abstract: A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deoinized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H2O or,ammonium hydroxide NH4OH and water H2O is applied to the periphery of the spinning wafer.

Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.

Abstract: A method of fabricating a thin film transistor array substrate for a liquid crystal display includes the step of forming a gate line assembly with gate lines, gate electrodes and gate pads. After laying a plurality of layers on the substrate, a photoresist film is deposited onto the layers. The photoresist film is first exposed to light at a first light exposing unit, and secondly exposed to light at a second light exposing unit such that the photoresist film has three portions of different thickness. The photoresist pattern, and some of the underlying layers are etched to form a data line assembly, a semiconductor pattern, and an ohmic contact pattern. The data line assembly includes data lines, source and drain electrodes, and data pads. The remaining photoresist film is removed, and a protective layer is formed on the substrate.

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: This invention relates to a method of improving the fabrication of etched semiconductor devices by using a patterned adhesion promoter layer over a hydrocarbon planarization material. More specifically, the present invention improves the bonding of a metal interconnect layer to a hydrocarbon planarization material, such as polyimide, by inserting an adhesion promotion layer, such as silicon nitride, between the hydrocarbon planarization material and the metal interconnect layer. A process for improving the fabrication of etched semiconductor devices, comprises the steps of: (1) depositing a hydrocarbon planarization material over a substrate; (2) depositing an adhesion promoter over the hydrocarbon planarization material; (3) defining a first mask and etching back the adhesion promoter so as to form an adhesion promoter pad over a portion of the hydrocarbon planarization material; and (4) depositing a first metal over the adhesion promoter pad.

Abstract: The present invention is directed to a process for forming one or more lateral nanostructures on a substrate. The process comprises the steps of: providing a substrate; depositing a first layer on the substrate; forming at least one edge on the first layer; depositing at least one separation layer on the first layer; depositing a third layer on the separation layer; and removing a portion of the separation layer and the third layer from the substrate such that a substantially planar surface is formed exposing the first layer, the separation layer, and the third layer.

Abstract: The present invention provides a method of reducing micro-particle adsorption effects during a CMP process, to thereby reduce micro-particle adsorption effects on a surface of a semiconductor wafer comprising a silicon nitride layer. The method uses polishing slurry containing anionic surfactant to change the zeta potential of the silicon nitride. Therefore, during the CMP process, the surface of the silicon nitride layer and the micro-particles bare the same type of charges, so as to reduce micro-particle adsorption effects on the surface of the semiconductor wafer.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device (10) with a heat sink (30) is described. In one aspect, a thermally conducting filled gel elastomer material (50) or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface (18) to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material (38) which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material (70) is applied between a die surface and the inside attachment surface (46) of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A method for polishing wafers includes providing a wafer having a grating structure and a process layer formed over the grating structure; illuminating at least a portion of the process layer and the grating structure with a light source; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; and determining planarity of the process layer based on the reflection profile. A metrology tool adapted to receive a wafer having a grating structure and a process layer formed over the grating structure includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile.

Abstract: A method of manufacturing a semiconductor device includes the formation of a dielectric film on a substrate having an effective device area surrounded by a peripheral area. A resist pattern exposing part of the dielectric film in the peripheral area is formed, and the dielectric film is etched to reduce the thickness of the exposed part. After the resist pattern has been removed, the dielectric film is planarized by chemical-mechanical polishing. Good planarity is achieved because the etching step removes high parts of the dielectric film from the peripheral area. This method of achieving improved planarity is less expensive than conventional methods employing dummy devices.

Abstract: An integrated semiconductor device is formed from two fabricated semiconductor devices each having a substrate by placing an etch-resist on the substrate of the one semiconductor device, by bonding the conductors of one of the fabricated semiconductor devices to the conductors of the other fabricated semiconductor device, flowing an uncured cement (e.g. epoxy) between the etch-resist and the other substrate, allowing the cement to solidify, and removing the substrate from the one of the semiconductor devices. More specifically, a hybrid semiconductor device is formed from a GaAs/AlGaAs multiple quantum well modulator having a substrate and an IC chip having a substrate by placing an etch resist on the modulator substrate, bonding the conductors of the modulator to the conductors of the chip, wicking an uncured epoxy between the modulators and the chip, allowing the epoxy to cure, and removing the substrate from the modulator.

Abstract: The current invention teaches the use of e-beam patterning techniques for forming contact and via holes of diameter less than about 0.15 microns down to 0.05 microns. E-beam lithography has higher resolution (down to 30-50 nanometers) as compared to 130-150 nanometer when using deep ultra violet (DUV) photolithography patterning techniques. In addition the invention uses a mix and match approach by employing a conventional I-line, or deep UV, resist to form the trench pattern and e-beam lithography tools to form the contact and vial hole patterns. A simplified process scheme is developed where contact/via holes are formed first on solvent developable e-beam resist and the trench pattern is formed on aqueous developable photoresist coated on top of the e-beam resist.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device (10) with a heat sink (30) is described. In one aspect, a thermally conducting filled gel elastomer material (50) or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface (18) to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material (38) which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material (70) is applied between a die surface and the inside attachment surface (46) of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A method of manufacturing a semiconductor article comprises forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding the first article and a second article so as to produce a multilayer structure having the porous layer in the inside thereof, and separating the multilayer structure along the porous layer.

Abstract: A method of making a printed circuit board whereby a fine wiring pattern can be formed. A through hole is formed in a substrate, both surfaces of the substrate being covered with copper foil. The substrate is treated with a catalyst and plated with copper. The through hole is filled with an insulating material, and the copper layer on the substrate is etched so that the catalyst layer is not exposed, leaving a thinned copper layer. Then, the substrate surfaces are ground and leveled by removing any projecting insulating material. Thereafter, another copper layer is deposited on the surface of the substrate, including surface regions on the fill material and is circuitized to form a wiring pattern. Since the catalyst layer is not exposed when the copper layer on the substrate is thinned, a fine wiring pattern can be obtained without the problem of subsequent peeling of the wiring conductors, or the entrapment of air.

Abstract: A method for forming an interlayer insulating film is disclosed. This method comprises the steps of: forming an Si—C film or an Si—C—H film on an underlying insulating film by performing plasma polymerization for an Si and C containing compound; forming a porous SiO2 film by performing O (oxygen) plasma oxidation for the Si—C film or the Si—C—H film; and forming a cover insulating film on the porous SiO2 film by performing H (hydrogen) plasma treatment for the porous SiO2 film.

Abstract: The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first metal on the substrate; depositing a second metal on the initial nanowires of the first metal to form thickened nanowires that are more resistant to etching than the initial nanowires; and etching the substrate to form atomic ridges separated by grooves having a pitch of 0.94 to 5.35 nm. The present invention also provides a method for forming Au and other metal nanowires that may be used for electrical conductors and both positive and negative etch masks to form a plurality of ridges at a pitch of 0.94 to 5.35 nm containing at least two adjacent grooves with widths of 0.63 to 5.04 nm.

Abstract: A film of fluorine-doped silicon glass (“FSG”) is exposed to a nitrogen-containing plasma to nitride a portion of the FSG film. In one embodiment, the FSG film is chemically-mechanically polished prior to nitriding. The nitriding process is believed to scavenge moisture and free fluorine from the FSG film. The plasma can heat the FSG film to about 400° C. for about one minute to incorporate about 0.4 atomic percent nitrogen to a depth of nearly a micron. Thus, the nitriding process can passivate the FSG film deeper than a via depth.

Abstract: A method comprises steps of forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding said first article and a second article so as to produce a multilayer structure having said porous layer in the inside thereof, and separating said multilayer structure along said porous layer.

Abstract: In a method of filling a trench in a substrate, a substrate is placed in a process zone, the substrate comprising a trench. A first deposition process is performed by providing a first gas into the process zone, maintaining first process conditions to deposit a first silicon oxide material in the trench in the substrate, and exhausting the first gas. Thereafter, a second deposition process is performed by providing a second gas into the process zone, maintaining second process conditions to deposit a second silicon oxide material to fill the trench and optionally overfill the trench, and exhausting the second gas. The multiple process deposition process allows the trench to be filled and overfilled with different types of silicon oxide materials to render the trench filling process more economical.

Abstract: A method of forming a HDPCVD oxide layer over metal lines, the metal lines having gaps between the metal lines having an aspect ratio of two or more. The method comprises the steps of: forming a liner oxide layer over the metal lines; and forming an HDPCVD oxide layer over the liner oxide layer, the formation of the HDPCVD oxide layer being done such that the deposition-to-sputter ratio is increasing as the gaps are being filled.

Abstract: A method for achieving a uniform planar surface by a chemical mechanical polish includes surrounding an active area or array to be polished with a border of the active material such that the border is wider than a single active area within the array and is preferably spaced from the outermost active area by the same distance as the distance between active areas within the array.

Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film.

Abstract: In order to separate first and second base substrate without cracking them, and use a damaged base substrate again as a semiconductor substrate to enhance a yield, there is disclosed a preparation method of a semiconductor substrate comprising the steps of separating a composite member formed by bonding the first and second base substrates to each other via an insulating layer into a plurality of members at a separation area formed in a position different from a bonded face to transfer a part of one base substrate onto the other base. A mechanical strength of the separation area is non-uniform along the bonded face in the composite member.

Abstract: A silicon containing wafer is heated in a rapid thermal processing (RTP) system in a nitrogen containing gas to a temperature an time where a thin oxide film on the wafer surface at least partially decomposes and a thin nitride or oxynitride film grows.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: For forming a contact electrode to an n-type layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.

Abstract: A technique for manufacturing memory devices which can easily manufacture ROM semiconductors having various write patterns at lower cost in a short period of time is disclosed. Since a simple matrix structure in which each memory cell is formed at a cross-point of an upper and a lower linear electrode is employed, and an insulating material is selectively ejected to surfaces of electrodes at predetermined memory cell positions by using an inkjet head, the surfaces of the electrode at the predetermined memory cell positions are covered with the insulating material. A state is stored in accordance with the presence or the absence of the covering insulating film on the surface of the electrode at each memory cell position.

Abstract: A method of manufacturing a semiconductor article comprises forming a doped layer containing an element capable of controlling the conductivity type at least on one of the surfaces of a semiconductor substrate, modifying the surface of the doped layer into a porous state to obtain a porous layer thinner than the doped layer, forming a non-porous layer on the porous layer to prepare a first article, bonding the first article and a second article so as to produce a multilayer structure having the porous layer in the inside thereof, and separating the multilayer structure along the porous layer.