Abstract: A Rat IgG antibody film, formed on a p-type Si substrate, is selectively irradiated with ultraviolet rays, thereby leaving part of the Rat IgG antibody film, except for a region deactivated with the ultraviolet rays. Next, when the p-type Si substrate is immersed in a solution containing Au fine particles that have been combined with a Rat IgG antigen, the Rat IgG antigen is selectively combined with the Rat IgG antibody film. As a result, Au fine particles, combined with the Rat IgG antigen, are fixed on the Rat IgG antibody film. Thereafter, the p-type Si substrate is placed within oxygen plasma for 20 minutes, thereby removing the Rat IgG antibody film, the deactivated Rat IgG antibody film and the Rat IgG antigen. Consequently, dot elements can be formed at desired positions on the p-type Si substrate. If these dot elements are used for the floating gate of a semiconductor memory device, then the device has a structure suitable for miniaturization.

Abstract: A method of metallization wherein particle issues are avoided during pre-metal cleaning by the use of a unique IMD scheme is described. A semiconductor substrate is provided which may include semiconductor device structures. An etch stop layer is deposited overlying the semiconductor substrate. A low-dielectric constant material layer is deposited overlying the etch stop layer. A polish stop layer is deposited overlying the low-dielectric constant material layer. An oxide layer is deposited overlying the polish stop layer. An anti-reflective coating (ARC) layer is deposited overlying the oxide layer. An opening is etched through the ARC layer, oxide layer, polish stop layer, and low-dielectric constant material layer where they are not covered by a mask. The mask is removed during the etch. The etch stop layer is etched through within the opening whereby the ARC layer is removed. The opening is cleaned using an Argon sputtering method.

Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process the fully hermetic sealing of both sides and the edges of the semiconductor chip out the use of a separate package.

Abstract: A process for manufacturing a semiconductor arrangement (3), whereby in particular a wafer (1) with a large number of semiconductor arrangements forming chips (7) is manufactured, and the wafer is divided afterward, and in this way the semiconductor arrangements are separated. At least one region of a wafer side is covered by a passivation layer (9) during the etching of the remaining wafer area. After etching, the passivation layer (9) is removed. At least in an outer edge region of the wafer, if need be additionally in the shape of the wafer front side, outside the active chip surface and especially in the regions bounding the respective chip systems, adhesion zones (8) for the passivation layer (9) are created which enter into a sealing, and in particular a chemical combination with the material used for the passivation layer.

Abstract: A process is revealed whereby resistors can be manufactured integral with the printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are revealed as techniques for improving the uniformity and consistency of the plated resistors.

Abstract: A method for fabricating a passivation layer on a metal pad. A conformal first silicon dioxide layer is formed on a substrate having a metal pad. A conformal first silicon nitride layer is formed on the first silicon dioxide layer, and then a second silicon dioxide layer is formed on the first silicon nitride layer by high density plasma chemical vapor deposition. The second silicon dioxide layer is planarized to expose the first silicon nitride layer. A portion of the first silicon nitride layer aligned over the metal pad is removed to expose the first silicon dioxide layer. A second silicon nitride layer is formed to cover the first silicon dioxide layer and the second silicon dioxide layer. In the above process, a thickness of the first silicon dioxide layer and a thickness of the second silicon nitride layer are precisely controlled.

Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: A back lapping in-line system for semiconductor device fabrication carries out a vinyl covering, a back side grinding, and a vinyl removing for grinding the back side of a wafer in-line with one single process. The back lapping in-line system has a server connected to a network line, a program therein for controlling the in-line processes, and an in-line facility connected to the server by a standard communication line, wherein parts of the in-line facility are assembled in order, and each part carries out its corresponding process according to information communicated to and from the server, and unloads the wafer after it passes through all of the corresponding processes successively. The in-line facility uses a single loading and unloading, and needs no storage space between parts.

Abstract: A method of reducing dishing and erosion of surfaces of inlaid material on semiconductor wafers. The method includes forming a sacrificial deposit or layer over at least down features of the patterned surface of the fill layer, that has a lower rate of removal during chemical-mechanical polishing than the fill layer. Elevated caps of sacrificial deposit are formed over inlaid fill material prior to pattern clearing. In CMP pattern clearing, the caps are removed and polishing proceeds at a faster rate on the slightly elevated inlaid fill upper surfaces until they are coplanar with surrounding patterned substrate. Chemical-mechanical polishing can be carried out in a single step, or in multiple steps, to produce the desired result.

Abstract: A method of preparing a surface for and forming a thin film on a single-crystal silicon substrate is disclosed. One embodiment of his method comprises forming an oxidized silicon layer (which may be a native oxide) on at least one region of the substrate, and thermally annealing the substrate in a vacuum while supplying a silicon-containing flux to the oxide surface, thus removing the oxidized silicon layer. Preferably, the thin film is formed immediately after removal of the oxidized silicon layer. The silicon-containing flux is preferably insufficient to deposit a silicon-containing layer on top of the oxidized silicon layer, and yet sufficient to substantially inhibit an SiO-forming reaction between the silicon substrate and the oxidized silicon layer. The method of the invention allows for growth or deposition of films which have exceptionally smooth interfaces (less than 0.1 nm rms roughness) with the underlying silicon substrate at temperatures less than 800° C.

Abstract: A micro-scale gap fabrication process using a dry releasable dendritic material sacrificial layer. The fabrication process produces micro-scale gaps, such as those required between a suspended microstructure and an opposing surface in MEMS. The dendritic sacrificial layer is releasable by heating the dendritic material past its decomposition point after forming the microstructure. The sacrificial layer may be applied to a wafer, for example, by spin coating a solution including the dissolved dendritic material. The sacrificial layer, after being formed, may be patterned and prepared for accepting structural material for the microstructure. After a desired microstructure or microstructures are formed around the sacrificial layer, the layer is dry releasable by heating.

Abstract: The flexibility of a wiring design is improved by preventing any erosion from happening upon forming a buried wiring. An interlayer insulating film is formed on a silicon substrate, and then trenches are formed in the interlayer insulating film. Thereafter, the barrier layer is deposited on side surfaces and a bottom surface in the trenches and on an entire area on the interlayer insulating film, and a copper seed layer is formed over an entire area on the barrier layer. Fountain plating is performed using the copper seed layer as an electrode to deposit the copper plated layer on the trenches and on a peripheral area of the same the copper plated layer buries the trenches and has a protruded configuration. Thereafter, the surface of the copper plated layer is polished with a CMP method until the interlayer insulating film is exposed to form a buried wiring.

Abstract: After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less. Thereafter, the bottom surface of the sapphire substrate is processed by etching using an etchant of phosphoric acid or phosphoric acid/sulfuric acid mixed liquid to remove a strained layer by lapping. Then, after making a via hole by etching the bottom surface of the sapphire substrate by using a similar etchant, the GaN semiconductor layer at the bottom of the via hole is removed by RIE to expose a Au pad electrically connected to the source of GaN FET. Thereafter, a thick Au film electrically connected to the Au pad is made through the via hole.

Abstract: A method for processing semiconductor wafers, which provides planarized surface in a well controllable manner and with high accuracy by processing a film with uneven surface, formed over a semiconductor wafer, within the area of a working surface with a diameter larger than that of said semiconductor wafer by not more than two times, and by processing the film with a polishing liquid supplied from a supply unit disposed on a vertically arranged working surface is disclosed. Additionally, high quality dressing of the working surface can be easily performed by virtue of the smaller diameter of the working surface. Furthermore, the vertical arrangement of the working surface makes possible ready compatibility with semiconductor wafers of enlarged diameters.

Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

Abstract: A method for forming a semiconductor device with avoiding chemical mechanical polishing caused residue on uncompleted fields of wafer edge is disclosed. The method comprising removing all conductive layers and silicon nitride layers on the uncompleted fields, thereby the height of the uncompleted fields will not higher than the height of the semiconductor device.

Abstract: This invention provides a planarization method that solves the microscratch problem caused by chemical-mechanical polishing. This method comprises the following steps: providing a substrate with semiconductor devices, forming a SRO oxide on the substrate, forming a SOG layer on the SRO layer, performing a curing process, performing an implantation process during the curing process, forming an oxide layer on the SRO oxide, and planarizing the oxide layer by CMP. Another SOG layer is formed on the planarized oxide layer, a curing process is performed on the second SOG layer, and a cap oxide layer is formed on the second SOG layer to adjust the thickness of the dielectric layer. This invention can solve conventional problems such as microscratching and metal bridges.

Abstract: A process for avoiding dishing in a planarizing layer whose final thickness is reduced by Chem. Mech. Polishing, is described. The first step is to coat the surface to be planarized with a layer of a hard dielectric material, such as silicon nitride, prior to depositing the planarizing medium. After the latter has been reflowed, its thickness is reduced by means of CMP. While CMP is being applied, the etch rate is constantly sensed. When the etch front approaches the aforementioned hard layer a decrease in the etch rate is sensed and etching is terminated, thereby eliminating any dishing effects.

Abstract: A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposited and planarized using chemical mechanical polishing (CMP). The undoped oxide layer is denser than the phosphorous doped oxide layer, so the undoped oxide layer can be polished more uniformly than the phosphorous doped oxide layer and can serve as a polish stop for a subsequent tungsten plug polish. Also, the denser undoped oxide layer serves as a more effective moisture barrier than the doped oxide layer. Overall fabrication process complexity can be reduced by performing both oxide depositions in a single operation with no intervening densification or CMP steps.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: An object of the invention is to provide a preparation process of a semiconductor wafer, in which breakage of the wafer on grinding the back surface of the wafer and on peeling the adhesive tape is prevented, and the operation time can be reduced. The preparation process of a semiconductor wafer comprises the steps of: adhering an adhesive tape on a front surface of a semiconductor wafer; grinding a back surface of the semiconductor wafer by a grinding machine; peeling the adhesive tape; and cleaning the front surface of the semiconductor wafer, wherein an adhesive tape having heat shrinkability is used as the adhesive tape, and after grinding the back surface of the semiconductor wafer, warm water at a temperature of from 50 to 99.degree. C. is poured to peel the adhesive tape in a wafer cleaning machine, and the front surface of the semiconductor wafer is cleaned in the wafer cleaning machine.

Abstract: A method for manufacturing a low profile semiconductor chip, includes fabricating a semiconductor device on a semiconductor wafer, grinding, with a grinding tool, a backside of the semiconductor wafer to reduce a thickness thereof, and with the wafer in the grinding tool, providing a support structure on the ground backside of the wafer.

Abstract: In processing an object by irradiating it with laser light, a laser irradiation chamber is evacuated to a pressure value suitable for the intended laser light processing and the laser light processing is performed with the pressure in the chamber kept constant at the above value. Further, electrodes are provided in the laser irradiation chamber, and the inside of the chamber is cleaned by introducing an etching gas into the chamber during or immediately before the laser light irradiation and rendering the etching gas active.

Abstract: A technique for processing an integrated circuit is disclosed. This technique includes the formation of a polysilicon resistor without silicide next to a polysilicon transistor gate with silicide. Prior to silicidation, an oxide layer coats both polysilicon structures. A portion of the oxide layer is removed by chemical-mechanical polishing to define a generally planar surface from the remaining oxide layer and reexposed portions of each polysilicon structure. A metal layer is deposited on the surface. The portion of the metal layer over the polysilicon resistor structure is removed through a lithographic procedure. A self-aligned silicidation procedure is performed to form a silicide from the metal remaining over the polysilicon gate structure. The formation of both structures is then completed.

Abstract: A method of forming a HDPCVD oxide layer over metal lines, the metal lines having gaps between the metal lines having an aspect ratio of two or more. The method comprises the steps of: forming a liner oxide layer over the metal lines; and forming an HDPCVD oxide layer over the liner oxide layer, the formation of the HDPCVD oxide layer being done such that the deposition-to-sputter ratio is increasing as the gaps are being filled.

Abstract: The present invention relates to a method of cleaning a surface of a substrate employed prior to film formation by using the CVD method which uses a reaction gas containing an ozone containing gas which contains ozone (O.sub.3) in oxygen (O.sub.2) and tetraethylorthosilicate (TEOS). The substrate surface cleaning method comprises the steps of oxidizing particles 13 by contacting a pre-process gas containing ozone 15 to a surface 12 of a substrate 11 on which the particles 13 are present, and removing the particles 13 by heating the substrate 11 to exceed a decomposition point of oxide 13a of the particles 13.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conducting interface material of filled gel elastomer material or a silicone elastomeric material or other elastomeric material is applied to the die surface to which the heat sink is to be bonded. A protective elastomeric layer is then applied to the interface material (or bare die). During subsequent glob top application and curing steps, it is conventionally difficult to remove unwanted glob top material, that which may have been unintentionally misapplied to the die surface. In the practice of this invention, the misplaced encapsulant (glob top) material adheres to the upper surface of the protective layer. The protective layer of material is then removed by peeling to also remove the misplaced glob top material prior to adhesion bonding of the heat sink to the die.

Abstract: The use of HSQ as a dielectric interlayer without cracking is achieved by depositing HSQ on a planarized dielectric layer, such as a silicon oxide derived from TEOS or silane. Embodiments include depositing a first HSQ gap fill layer on a patterned metal layer for gap filling leaving a non-planar upper surface. Depositing a thin layer of silicon oxide and planarizing the upper surface as by CMP, and depositing the HSQ dielectric interlayer on the planarized upper surface of the oxide layer.

Abstract: A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

Abstract: A method of forming very small diameter metal lines in a dielectric layer 12 comprising forming an opening in the dielectric layer using photolithographic techniques, filling the opening with an insulating material 16 and planarizing the dielectric layer using chemical metal polishing techniques, which are continued so as to form small trenches 17 in the dielectric material on either side of the insulating material, filling in the trenches with metal and planarizing the metal layer using chemical metal polishing.

Abstract: Methods of forming electrically interconnected lines using organic compound cleaning agents include the steps of forming a first electrically conductive line on a substrate and then forming a first electrically insulating layer on the first electrically conductive line to electrically isolate the first conductive line from adjacent regions and lines. An organic spin-on-glass (SOG) passivation layer is then formed as a planarization layer on the first electrically insulating layer. The organic SOG layer is then etched-back to define a first etched surface thereon, using a carbon-fluoride gas which also preferably contains argon. The organic SOG layer may even be sufficiently etched back to expose an upper surface of the first electrically insulating layer. The first etched surface is then exposed to an organic compound cleaning agent so that organic residues can be removed from the etched surface so that layers subsequently formed on the etched surface are less susceptible to lift-off and flaking.

Abstract: A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.

Abstract: A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

Abstract: An apparatus for manufacturing a semiconductor device includes a wafer grinding section which grinds a wafer fixed on an ultraviolet sensitive tape and a drying section which dries the wafer after the wafer is ground. The drying section includes an ultraviolet irradiation device irradiating the ultraviolet sensitive tape with ultraviolet rays.

Abstract: A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad for providing a surface against which a surface of an integrated circuit substrate is polished during polishing; (ii) an anode on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source including a first electrical connection and a second electrical connection, the first electrical connection being connected to the anode and the second electrical connection being configured for connection to the integrated circuit substrate undergoing polishing such that when a voltage is applied from the voltage source in the presence of slurry admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate.

Abstract: A method of forming metal lines in a patterned dielectric layer. First, a thin (50 .ANG.-500 .ANG.) metal layer of a group VB metal, preferably niobium, is formed on a patterned dielectric layer. Next, an aluminum layer or an aluminum alloy layer is formed on the thin niobium layer. The aluminum layer is preferably formed by depositing a first thickness of collimated aluminum at low temperature followed by high temperature deposition of an equal thickness of aluminum. The aluminum layer is Chem-Mech polished (CMP) with an oxidizing acidic colloidal alumina slurry to expose and oxidize the thin niobium liner which acts as a polish stop. Then, the exposed thin niobium liner is removed using CMP. Alternatively, instead of niobium, the liner may be a thin layer of a group VB metal or an alloy thereof.

Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating.

Abstract: An improved planarization process for a trench dielectric is presented. A shallow trench isolation structure is formed into the semiconductor substrate. A thin oxide layer is grown upon the trench floor and upon the trench sidewalls, and then a trench dielectric, preferably TEOS deposited using a chemical-vapor deposition CVD process, is deposited into the trench dielectric and upon the semiconductor substrate. The upper surface of the trench dielectric conforms to the underlying contour defined by the shallow trench and the semiconductor substrate. Subsequent device formation requires a substantially planar semiconductor. Conventionally, a combination of masking and etching are used, prior to chemical-mechanical polishing ("CMP"), to aid the planarization process. The extra steps add cost and unnecessary complexity to the process. An alternative planarization process is proposed which uses hydrogen silsequioxane-based flowable oxide ("HSQ").

Abstract: A method of fabricating a semiconductor device includes the steps of protecting a front surface of a semiconductor substrate by an adhesive medium, grinding a rear surface of the semiconductor substrate in a state that the front surface is protected by the adhesive medium, removing the adhesive medium from the rear surface, and heating the semiconductor substrate, after the step of removing, to a temperature higher than a thermal decomposition temperature of an adhesive provided on the adhesive medium.

Abstract: The present invention is a process for making a nanochannel glass (NCG) rica, having the steps of: coating a face of an etched NCG with a replica material (with or without an intervening buffer layer), where the etched NCG face has a plurality of channels arranged in a desired pattern, to form a replica coating on the NCG conforming to the pattern; and removing the replica coating from the etched NCG. The present invention is also the replica made by this process.

Abstract: The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production.

Abstract: A method of manufacturing semiconductor devices that provides excellent controllability and workability in planarizing the isolation area. The novel method comprises the steps of: forming a filling material on a semiconductor substrate formed with a plurality of trenches such that the plurality of trenches are filled up with the filling material; forming a mask having a pattern obtained by inverting a pattern of the plurality of trenches onto the surface of the filling material; etching the filling material to a predetermined depth by use of the mask to leave a protruding portion composed of the filling material on each of the plurality of trenches; and removing the mask and then the protruding portion for planarization.

Abstract: A technique for self-aligned silicidation of semiconductor devices is disclosed. This technique includes the formation of polysilicon device features extending from a semiconductor substrate. A coating is deposited on the features and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a polysilicon surface of the features. A metallic layer is formed to contact the exposed polysilicon surface of each of the features. A silicide layer is formed for each feature from the polysilicon and the metallic layer in contact therewith.

Abstract: A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed onto the wafer. Preferably, the suction is applied simultaneously with the dispensing of the chemical. One specific version of the invention provides an edge bead removal system wherein suction is applied to the area immediately surrounding the solvent dispensing nozzle to remove dissolved coating material and excess solvent from the wafer. In one aspect of this system, an apparatus for removing the edge bead includes a mechanism for dispensing a solvent selectively onto the edge of the wafer, and a mechanism surrounding the dispensing mechanism for vacuuming excess solvent and dissolved coating material from the edge of the wafer.

Abstract: A glass ceramic substrate is formed on a glass ceramic insulating layer with a conductor connecting a plurality of circuit patterns which are to be independent of each other as to electrical function. Baking the glass-ceramic insulating layer with the conductor, and opening by cutting after baking, forms a plurality of independent circuits with improved electrical resistance between them.

Abstract: Healing of scratches created during CMP is achieved by reflowing the material containing the scratches and then depositing a top layer of material. The deposition of the top layer further enhances the healing of the scratches.

Abstract: Fabrication of atomic step-free regions on a substrate surface is achieved by first forming a two-dimensional pattern on the substrate. The pattern is preferably a grating comprising an array of troughs or mesas which are separated from one another by a plurality of ridges or trenches. Any atomic steps on the flat top surfaces of the troughs or mesas are moved into barrier regions formed by the ridge or trench sidewalls during a high temperature annealing or deposition step, thereby leaving the flat surfaces of the troughs and mesas free of atomic steps. Structures having step-free regions large enough to accommodate micron sized devices having nanometer sized features are thereby formed.

Abstract: A sculptured diaphragm of a sensor is fabricated by providing a semiconductor material, forming at least one cavity on the front side of the semiconductor material, forming a diaphragm layer over the semiconductor material, and the etching a cavity on the back side of the semiconductor material. If a sensor having a diaphragm with a central boss is desired, then the diaphragm layer is planarized to form a thick and a thin portion in the diaphragm layer.

Abstract: Global planarization of a non-planar substrate surface is accomplished using a sacrificial material in conjunction with an etching and chemical-mechanical polishing (CMP) technique. The sacrificial material has a greater rate of removal relative to the substrate during the CMP process and at a lesser rate relative to the material during the etching process. The use of the sacrificial material enables the etching process to substantially reduce the height of topographic features that occur in the non-planar surface. The CMP process is then performed on the etched material surface to produce a planarized material surface that is substantially free of feature dependent dishing. Such a process is useful for planarizing material layers in fabricating integrated circuit devices as well as for planarizing recessed structures in such devices.

Abstract: In a method of treating a semi-conductor wafer a short-chain polymer is deposited on the wafer to planarise surface features on the wafer and a diffusion layer is deposited on the surface of the polymer layer to allow moisture to be released from the polymer at a controlled rate.