Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Abstract: The present invention is a method for modifying a substrate in a predetermined pattern, comprising the steps of: (a) applying a material to the face of an etched nanochannel glass (NCG), where this face has a pattern of channels corresponding to the predetermined pattern, and (b) contacting the substrate with the etched NCG face having applied material, under conditions for transferring the material to the substrate.

Abstract: A process for producing a semiconductor substrate is provided which comprises steps of forming a porous layer on a first substrate, forming a nonporous monocrystalline semiconductor layer on the porous layer of the first substrate, bonding the nonporous monocrystalline layer onto a second substrate, separating the bonded substrates at the porous layer, removing the porous layer on the second substrate, and removing the porous layer constituting the first substrate.

Abstract: A method of fabricating vertically integrated microelectronic systems by CMOS-compatible standard semiconductor process technology, by independently processing individual component layers of at least two separate substrates, including the formation of via holes penetrating through all existing component layers and connecting together the front surfaces of the two substrates, thinning the reverse surface of one of the substrates down to the via holes, increasing the depth of the via holes to a metallization plane of the other substrate and forming electrically conductive connections between the two substrates through the via holes.

Abstract: A process for producing semiconductor devices using ultraviolet sensitive tape including the steps of forming a plurality of chips on a first surface of a semiconductor wafer, adhering an ultraviolet sensitive tape to the first surface of the semiconductor wafer, back lapping a second surface of the wafer, opposite to the first surface, and irradiating the ultraviolet sensitive tape with ultraviolet rays to release the ultraviolet sensitive tape from the wafer.

Abstract: A simplified crack stop formation compatible with shallow fuse etch processes which are utilized for modern low-cost redundancy designs using upper level metal fuses. A modified last level metallization (LLM) etch according to the invention allows a high-productivity single step bondpad/fuse/crack stop etch. The stack of metal films formed at the edge of the dicing channel is readily removed with a modified LLM etch prior to dicing causing the insulator films covering the dicing channel to be physically separated from the insulators coating the electrically active chip areas. The separation prevents cracks that could propagate through the insulators of the dicing channel in to the active chip.

Abstract: A method of manufacturing a semiconductor integrated circuit device employs a new reflowing process of an insulating film having contact holes and openings therethrough. A good step coverage of a wiring electrode at the contact holes of the insulating film can be obtained with reduced thermal cycles in the manufacturing of integrated circuit devices, and also with a reduced heat treatment temperature of the reflowing process. The process includes a step of depositing a silicon nitride film on the insulating film and on the contact holes by chemical vapor deposition at a temperature between 700.degree. C. and 800.degree. C. so as to deform edges of the contact holes in the insulating film to be rounded and smooth.

Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.

Abstract: A moat pattern (19) is formed in a first layer of material (11) to improve the profile of a planarization process. The presence of the moat pattern (19) in the periphery of a semiconductor substrate (10,30) moves the effects of the relaxation distance (13) away from the critical areas of the semiconductor substrate (30). The moat pattern (19) is formed during a photolithographic process by using a photolithographic mask (20) that has a portion (22) that defines and patterns the moat pattern (19). The moat pattern (19) is defined as edge dice (31) are patterned across the semiconductor substrate (30).

Abstract: A method of forming a trench isolation structure is provided in which a film is formed on a semiconductor substrate and a trench is formed in the semiconductor substrate through the film. A dielectric material is deposited in the trench and on the film. An etch resistant film is formed on the portions of the dielectric material in the trench and on exposed portions of the film at edge regions of the trench. The dielectric material on the film is selectively removed and the etch resistant film remaining on the dielectric material in the trench is selectively removed.

Abstract: A layer over a patterned semiconductor is polished and analyzed to determine a polishing endpoint. The analysis may be performed using reflected radiation beams or by a radiation scattering analyzer. The analysis may be performed on virtually any layer using a radiation source. The analysis may be performed with a liquid, such as an aqueous slurry, contacting the substrate. The polishing and analysis may be integrated such that both steps are performed on the same polisher.

Abstract: A process for detecting fine particles includes the steps of forming a sublimable thin film on an essential surface of a wafer on which fine particles are present, irradiating laser beam at the surface of the wafer, receiving a reflected beam from the surface which is scattered by the presence of the fine particles, and detecting the particles from the received scattered beam. The process may further include the step of accomplishing an etchback against the sublimable film to partially retain the sublimable film adjacent the surface of the fine particles. The film can be prepared from one or a mixture of gas including free sulfur generatable gas under discharge-dissociation conditions. Sulfur compounds or polythiazyl are preferable. Alternatively, the film can be made of a condensed film of organic solvent vapor. The sublimable film is sublimed by heating after the step of detecting the fine particles.

Abstract: A method of forming via holes in an organic insulation film or cutting the film includes the steps of exposing predetermined parts of the film to a laser beam to raise a temperature of the exposed parts of the film until the exposed parts are transformed or decomposed and subjecting the film to an ultra sonic wave so that the transformed or decomposed parts are dispersed.

Abstract: A layer planarizing method for a semiconductor device is provided to attain excellent controllability of a polishing amount to form a uniform and flat layer on a non-uniform wafer in polishing in a wafer surface. According to the method, a first layer is deposited over at least a top portion of a stepped portion formed on a surface of a body, the stepped portion covered with the first layer is covered with a second layer having a higher polishing rate than that of the first layer, and the second layer is polished until the first layer deposited on the top portion of the stepped portion is exposed.