Layers Formed Of Diverse Composition Or By Diverse Coating Processes Patents (Class 438/763)
  • Patent number: 10407773
    Abstract: Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed precursor by purging the processing chamber with a primary purge gas, and thereafter reacting adsorbed film precursor while a secondary purge gas is flowed into the processing chamber, resulting in the formation of a film layer on the substrate. The secondary purge gas may include a chemical species having an ionization energy and/or a disassociation energy equal to or greater than that of O2. Also disclosed are apparatuses which implement the foregoing processes.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 10, 2019
    Assignee: Lam Research Corporation
    Inventors: Adrien LaVoie, Hu Kang, Purushottam Kumar, Shankar Swaminathan, Jun Qian, Frank L. Pasquale, Chloe Baldasseroni
  • Patent number: 10366898
    Abstract: Techniques are disclosed for methods and apparatuses for performing continuous-flow plasma enhanced atomic layer deposition (PEALD). Plasma gas, containing one or more component gases, is continuously flowed to a planar inductive coupled plasma source attached at an upper end of a cylindrical chamber. Plasma is separated from the ALD volume surrounding a wafer/substrate in the lower end of the chamber by a combination of a grounded metal plate and a ceramic plate. Each plate has a number of mutually aligned holes. The ceramic plate has holes with a diameter less than 2 Debye lengths and has a large aspect ratio. This prevents damaging plasma flux from entering the ALD volume into which a gaseous metal precursor is also pulsed. The self-limiting ALD reaction involving the heated substrate, the excited neutrals from the plasma gas, and the metal precursor produce an ultra-uniform, high quality film on the wafer. A batch configuration to simultaneously coat multiple wafers is also disclosed.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Nano-Master, Inc.
    Inventor: Birol Kuyel
  • Patent number: 10361088
    Abstract: Techniques are disclosed for methods and apparatuses for performing continuous-flow plasma enhanced atomic layer deposition (PEALD). Plasma gas, containing one or more component gases, is continuously flowed to a planar inductive coupled plasma source attached at an upper end of a cylindrical chamber. Plasma is separated from the ALD volume surrounding a wafer/substrate in the lower end of the chamber by a combination of a grounded metal plate and a ceramic plate. Each plate has a number of mutually aligned holes. The ceramic plate has holes with a diameter less than 2 Debye lengths and has a large aspect ratio. This prevents damaging plasma flux from entering the ALD volume into which a gaseous metal precursor is also pulsed. The self-limiting ALD reaction involving the heated substrate, the excited neutrals from the plasma gas, and the metal precursor produce an ultra-uniform, high quality film on the wafer. A batch configuration to simultaneously coat multiple wafers is also disclosed.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 23, 2019
    Assignee: Nano-Master, Inc.
    Inventor: Birol Kuyel
  • Patent number: 10276363
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10229829
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 12, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshinobu Nakamura, Kiyohiko Maeda, Yoshiro Hirose, Ryota Horiike, Yoshitomo Hashimoto
  • Patent number: 10191338
    Abstract: An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: January 29, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chin-Yueh Liao, Yi-Chun Kao
  • Patent number: 10026745
    Abstract: A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Han Wang, Xian Feng Du
  • Patent number: 9997617
    Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Xia Li, Periannan Chidambaram
  • Patent number: 9947530
    Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Jo Tak, Sam Mook Kang, Mi Hyun Kim, Jun Youn Kim, Young Soo Park
  • Patent number: 9934962
    Abstract: A method of manufacturing a semiconductor device includes a process of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor containing a predetermined element to the substrate; supplying a first reactant containing nitrogen and carbon to the substrate; supplying a second reactant containing nitrogen to the substrate; and supplying a third reactant containing oxygen to the substrate, wherein in the cycle, a supply amount of the second reactant is set to be smaller than a supply amount of the first reactant.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 3, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Tatsuru Matsuoka
  • Patent number: 9917182
    Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Kohei Oasa, Takuo Kikuchi, Junji Kataoka, Tatsuya Shiraishi, Akira Yoshioka, Kazuo Saki
  • Patent number: 9892814
    Abstract: A method for forming an electrically conductive oxide film (1) on a substrate (2), the method comprising the steps of, bringing the substrate (2) into a reaction space, forming a preliminary deposit on a deposition surface of the substrate (2) and treating the deposition surface with a chemical. The step of forming the preliminary deposit on the deposition surface of the substrate (2) comprises forming a preliminary deposit of transition metal oxide on the deposition surface and subsequently purging the reaction space. The step of treating the deposition surface with a chemical comprises treating the deposition surface with an organometallic chemical and subsequently purging the reaction space, to form oxide comprising oxygen, first metal and transition metal. The steps of forming the preliminary deposit and treating the deposition surface being alternately repeated such that a film (1) of electrically conductive oxide is formed on the substrate (2).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 13, 2018
    Assignee: Beneq Oy
    Inventor: Jarmo Maula
  • Patent number: 9882022
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9842881
    Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: December 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Jong-Han Shin, Ki-Seon Park
  • Patent number: 9824895
    Abstract: A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 9816181
    Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: November 14, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9777370
    Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: October 3, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9761436
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9732426
    Abstract: According to the present disclosure, a film containing carbon added at a high concentration is formed with high controllability. A method of manufacturing a semiconductor device includes forming a film containing silicon, carbon and a predetermined element on a substrate by performing a cycle a predetermined number of times. The predetermined element is one of nitrogen and oxygen. The cycle includes supplying a precursor gas containing at least two silicon atoms per one molecule, carbon and a halogen element and having an Si—C bonding to the substrate, and supplying a modifying gas containing the predetermined element to the substrate.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: August 15, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Yoshiro Hirose, Atsushi Sano
  • Patent number: 9711348
    Abstract: The present invention increases controllability of a composition ratio of a multi-element film that contains a predetermined element and at least one element selected from the group consisting of boron, oxygen, carbon and nitrogen. There is provided a method of manufacturing a semiconductor device, including: forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming the first film being free of borazine ring structure and including a predetermined element and at least one element selected from the group consisting of oxygen, carbon and nitrogen; and (b) forming the second film having a borazine ring structure and including at least boron and nitrogen.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 18, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9685533
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: February 21, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9653319
    Abstract: Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 16, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Anton J. deVilliers, Kaushik Kumar
  • Patent number: 9537044
    Abstract: A method for manufacturing an optoelectric device comprising a semiconductor substrate, pads on a surface of the substrate; semiconductor elements, each element being in contact with a pad; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair, the method successively comprising the forming of the pads and the forming of the region, wherein the region is formed by nitriding of the substrate, the method comprising the successive steps of: depositing a layer on the substrate; forming portions on the layer; etching the parts of the layer which are not covered with the portions to form the pads; removing the portions; and nitriding the pads and the parts of the substrate which are not covered with the pads, wherein the nitriding step successively comprises: a first step of nitriding of the pads at a first temperature; and a second step of nitriding of the parts of the substrate which are not covered with
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: January 3, 2017
    Assignees: ALEDIA, Commissariat A L'Energie Atomique Et Aux Energies
    Inventors: Philippe Gilet, Xavier Hugon, David Vaufrey, Hubert Bono, Bérangère Hyot
  • Patent number: 9464351
    Abstract: A method of fabricating a light-scattering substrate, a light-scattering substrate fabricated by the same method, and an organic light-emitting device (OLED) including the same light-scattering substrate, in which a light-scattering layer of the light-scattering substrate can improve a light extraction efficiency. The method fabricates the light-scattering substrate by chemical vapor deposition, and includes loading a base substrate into a chamber, and forming a light-scattering layer on the base substrate by supplying a Ti source and an oxidizer including H2O into the chamber. In the process of forming the light-scattering layer, the mole ratio of the H2O with respect to the Ti is 10 or greater.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: October 11, 2016
    Assignee: CORNING PRECISION MATERIALS CO., LTD.
    Inventors: Gun Sang Yoon, Hyun Bin Kim, June Hyoung Park
  • Patent number: 9460916
    Abstract: An object of the present invention is to form a good thin film while suppressing generation of foreign substances in a low temperature region. Provided is a method of manufacturing a semiconductor device, including: (a) forming a thin film containing at least a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element and a halogen element to the substrate in a process container; and (a-2) supplying a reaction gas composed of carbon, nitrogen, and hydrogen to the substrate in the process container; and (b) modifying byproduct adhered to an inside of the process container by supplying a nitriding gas into the process container after (a).
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 4, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Yugo Orihashi, Yoshitomo Hashimoto, Yoshiro Hirose
  • Patent number: 9436080
    Abstract: The invention relates to a method for correcting at least one error on wafers processed by at least one photolithographic mask, the method comprises: (a) measuring the at least one error on a wafer at a wafer processing site, and (b) modifying the at least one photolithographic mask by introducing at least one arrangement of local persistent modifications in the at least one photolithographic mask.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 6, 2016
    Assignees: Carl Zeiss SMS GmbH, Carl Zeiss SMS Ltd.
    Inventors: Dirk Beyer, Vladimir Dmitriev, Ofir Sharoni, Nadav Wertsman
  • Patent number: 9425075
    Abstract: The present disclosure suppresses oxidation of a base film on a substrate surface during the formation of an oxide film. A method of manufacturing a semiconductor device according to the present disclosure includes forming an initial layer including a predetermined element and having a thickness of several atomic layers on a substrate in a process chamber by supplying a predetermined-element-containing gas to the substrate, and forming an oxide film including the predetermined element on the initial layer by performing a cycle a predetermined number of times, the cycle including supplying a precursor gas including the predetermined element to the substrate in the process chamber and supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in the process chamber under a pressure lower than an atmospheric pressure.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 23, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose, Naonori Akae
  • Patent number: 9425039
    Abstract: Provided is a technique of controlling a work function of a metal film. A composite metal nitride film is formed on a substrate present in a process chamber by alternately supplying a first source and a second source to the substrate, wherein the first source contains a first metal element, the second source contains an ethyl ligand and a second metal element that is different from the first metal element, and a bond between the second metal element and a nitrogen element in the composite metal nitride film has crystallinity.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 23, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuhiro Harada, Arito Ogawa
  • Patent number: 9385031
    Abstract: According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 5, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Rogalli, Wolfgang Lehnert
  • Patent number: 9379275
    Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
  • Patent number: 9330903
    Abstract: Provided a method including forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times under a condition where a borazine ring structure in a fourth process gas is maintained. The cycle includes: (a) forming the first film by performing a first set a predetermined number of times, wherein the first set includes supplying a first process gas and supplying a second process gas to the substrate; and (b) forming the second film by performing a second set a predetermined number of times, wherein the second set includes supplying a third process gas and supplying the fourth process gas to the substrate.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 3, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9287282
    Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ta Hsieh, Po-Wei Liu, Yong-Shiuan Tsair, Chieh-Fei Chiu
  • Patent number: 9287124
    Abstract: In one embodiment, a method is proposed for etching a boron dope hardmask layer. The method includes flowing a process gas comprising at least CH4 into a processing chamber. Forming a plasma in the process chamber from the process gas and etching the boron doped hardmask layer in the presence of the plasma. In other embodiments, the process gas utilized to etch the boron doped hardmask layer includes CH4, Cl2, SF6 and O2.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 15, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Byungkook Kong, Jun Wan Kim, Wonmo Ahn, Jeong Hyun Yoo, Hun Sang Kim
  • Patent number: 9231189
    Abstract: A sodium niobate powder includes sodium niobate particles having a shape of a cuboid and having a side average length of 0.1 ?m or more and 100 ?m or less, wherein at least one face of each of the sodium niobate particles is a (100) plane in the pseudocubic notation and a moisture content of the sodium niobate powder is 0.15 mass % or less. A method for producing a ceramic using the sodium niobate powder is provided. A method for producing a sodium niobate powder includes a step of holding an aqueous alkali dispersion liquid containing a niobium component and a sodium component at a pressure exceeding 0.1 MPa, a step of isolating a solid matter from the aqueous dispersion liquid after the holding, and a step of heat treating the solid matter at 500° C. to 700° C.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: January 5, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoaki Masubuchi, Toshiaki Aiba, Toshihiro Ifuku, Makoto Kubota, Takayuki Watanabe, Tatsuo Furuta, Jumpei Hayashi
  • Patent number: 9112012
    Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 18, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventor: Jianguang Chang
  • Patent number: 9105531
    Abstract: A first photosensitive organic insulating film (PO1) formed in contact with a passivation film (PL) covers the entire circumference of a stepped portion (TRE) at a surface of the passivation film PL formed by a topmost conductive layer (TCL) and has an outer circumferential edge (ED1) positioned, along the entire circumference, on the outer circumferential side with respect to the stepped portion (TRE). This can prevent the first photosensitive organic insulating film (PO1) from peeling off the passivation film (PL).
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 11, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuo Tomita
  • Patent number: 9087695
    Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: July 21, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Igor Agafonov, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Publication number: 20150147890
    Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.
    Type: Application
    Filed: December 23, 2013
    Publication date: May 28, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
  • Publication number: 20150137333
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Application
    Filed: December 8, 2014
    Publication date: May 21, 2015
    Inventor: Eugene P. Marsh
  • Publication number: 20150137331
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures.
    Type: Application
    Filed: January 26, 2015
    Publication date: May 21, 2015
    Inventors: Dan B. Millward, Donald L. Westmoreland
  • Publication number: 20150140765
    Abstract: A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.
    Type: Application
    Filed: December 30, 2014
    Publication date: May 21, 2015
    Inventors: Wei-Yang LEE, Xiong-Fei YU, Da-Yuan LEE, Kuang-Yuan HSU
  • Publication number: 20150140773
    Abstract: Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described.
    Type: Application
    Filed: January 13, 2015
    Publication date: May 21, 2015
    Inventors: Vassil Antonov, Jennifer K. Sigman, Vishwanath Bhat, Matthew N. Rocklein, Bhaskar Srinivasan, Chris Carlson
  • Patent number: 9034675
    Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Junichiro Sakata, Yoshiharu Hirakata, Norihito Sone
  • Publication number: 20150129972
    Abstract: Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventor: Kisik Choi
  • Publication number: 20150129989
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 14, 2015
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Publication number: 20150126029
    Abstract: There is provided a dry film photoresist including a substrate layer constituted by a certain substrate, a resist layer disposed over the substrate layer, the resist layer including a plurality of layers, and a protective film layer disposed over the resist layer, the protective film layer protecting the resist layer. A photosensitive layer is positioned on a side of the substrate layer of the resist layer, the photosensitive layer having a dissolution rate to a certain developer that decreases by being exposed to light, and a non-photosensitive layer is positioned on a side of the protective film layer of the resist layer, the non-photosensitive layer being soluble to the developer. A dissolution rate of the non-photosensitive layer to the developer is higher than a dissolution rate of an unexposed portion in the photosensitive layer to the developer.
    Type: Application
    Filed: September 26, 2014
    Publication date: May 7, 2015
    Inventors: Hideki Kimura, Nozomu Hoshi, Yoshihiko Takahashi, Kenji Katsumata
  • Patent number: 9018105
    Abstract: The invention relates to a device and a method for depositing semiconductor layers, in particular made of a plurality of components on one or more substrates (21) contacting a susceptor (2), wherein process gases can be introduced into the process chamber (1) through flow channels (15, 16; 18) of a gas inlet organ (8), together with a carrier gas, said carrier gas permeating the process chamber (1) substantially parallel to the susceptor and exits through a gas outlet organ (7), wherein the products of decomposition build up the process gases as a coating at least in regions on the substrate surface and on the surface of the gas outlet organ (7) disposed downstream of the susceptor (2) at a distance (D) from the downstream edge (21) thereof.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 28, 2015
    Assignee: Aixtron SE
    Inventor: Gerhard Karl Strauch
  • Patent number: 9013049
    Abstract: To provide a resin composition for sealing an optical semiconductor, which is a raw material for a sealing resin layer having good curability and excellent storage stability; preferably a raw material for a sealing resin layer further having excellent weather resistance. The surface sealant for an optical semiconductor of Embodiment 1 according to the present invention contains epoxy resin (a) having two or more epoxy groups in a molecule, and metal complex (b1) which contains at least one metal ion selected from the group consisting of Zn, Bi, Ca, Al, Cd, La and Zr, a tertiary amine capable of forming a complex with the metal ion and having no N—H bond and an anionic ligand having a molecular weight of 17 to 200, in which the surface sealant has a viscosity of 10 to 10000 mPa·s, as measured by E-type viscometer at 25° C. and 1.0 rpm.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 21, 2015
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Yugo Yamamoto, Jun Okabe, Setsuko Oike
  • Patent number: 9006064
    Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
  • Patent number: 9006051
    Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Masayuki Kajiwara, Masataka Nakada, Masami Jintyou, Shunpei Yamazaki