Layers Formed Of Diverse Composition Or By Diverse Coating Processes Patents (Class 438/763)
  • Patent number: 11222816
    Abstract: A method of filling structures on a substrate uses a semi-dynamic reflow process. The method may include depositing a metallic material on the substrate at a first temperature, heating the substrate to a second temperature higher than the first temperature wherein heating of the substrate causes a static reflow of the deposited metallic material on the substrate, stopping heating of the substrate, and depositing additional metallic material on the substrate causing a dynamic reflow of the deposited additional metallic material on the substrate. RF bias power may be applied during the dynamic reflow to facilitate in maintaining the temperature of the substrate.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 11, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lanlan Zhong, Shirish A. Pethe, Fuhong Zhang, Joung Joo Lee, Kishor Kalathiparambil, Xiangjin Xie, Xianmin Tang
  • Patent number: 11189778
    Abstract: An element 1 includes a pair of electrodes 2 and 3, and an intermediate layer 4 having deformability, arranged between the pair of electrodes 2 and 3, and containing, as a material, a silicon compound including an unpaired electron. The intermediate layer 4 may contain a particle including the unpaired electron. The intermediate layer 4 may have rubber elasticity. The intermediate layer 4 may have at least one peak at a g value between 2.070 and 2.001 when being measured at an environment temperature of ?150° C. by using an electron spin resonance (ESR) device. The intermediate layer 4 may have at least one peak at a g value between 2.070 and 2.001 when being measured at an environment temperature of ?150° C. by using the electron spin resonance (ESR) device.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 30, 2021
    Assignee: RICOH COMPANY, LTD.
    Inventors: Tomoaki Sugawara, Tsuneaki Kondoh, Yuko Arizumi, Junichiro Natori, Mizuki Otagiri, Mayuka Araumi, Megumi Kitamura, Takahiro Imai, Makito Nakashima, Hideyuki Miyazawa
  • Patent number: 11152306
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Patent number: 11065334
    Abstract: A method comprises providing a plurality of nanostructures comprising a base material. The plurality of nanostructures are exposed to a first material at a first deposition temperature. The plurality of nanoparticles are exposed to a second material at a second deposition temperature, and exposed to a Boron-10 (10B) containing material at a third deposition temperature so as to form a 10B-metal oxide based composite nanostructure.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 20, 2021
    Assignee: UChicago Argonne, LLC
    Inventors: Anil U. Mane, Jeffrey W. Elam
  • Patent number: 11011369
    Abstract: There is provided a method of forming a carbon film on a workpiece, which includes: loading the workpiece into a process chamber; supplying a gas containing a boron-containing gas into the process chamber to form a seed layer composed of a boron-based thin film on a surface of the workpiece; and subsequently, supplying a hydrocarbon-based carbon source gas and a pyrolysis temperature lowering gas containing a halogen element and which lowers a pyrolysis temperature of the hydrocarbon-based carbon source gas into the process chamber, heating the hydrocarbon-based carbon source gas to a temperature lower than the pyrolysis temperature to pyrolyze the hydrocarbon-based carbon source gas, and forming the carbon film on the workpiece by a thermal CVD.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 18, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Shimizu, Masayuki Kitamura, Yosuke Watanabe
  • Patent number: 10867923
    Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hoon Ahn, Tae Soo Kim, Jong Min Baek, Woo Kyung You, Thomas Oszinda, Byung Hee Kim, Nae In Lee
  • Patent number: 10840088
    Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Samuel E. Gottheim, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 10832905
    Abstract: A low pressure chemical vapor deposition (LPCVD) technique for nitride semiconductor materials includes steps of: setting a temperature in a furnace to be 750 to 900° C.; substituting an atmosphere in the furnace to ammonia (NH3); depositing a SiN film at an initial pressure by supplying di-chloro-silane (SiH2Cl2); and subsequently depositing the SiN film at a deposition pressure that is higher than the initial pressure. The invention has a feature that the initial pressure is at least higher than 60% of the deposition pressure.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 10, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 10626502
    Abstract: There is provided a technique that includes arranging a plurality of substrates inside a process container in a vertical direction; and forming a film on each of the plurality of substrates by supplying a process gas into the process container. The act of forming the film includes: supplying the process gas into the process container; and performing pressure control such that a pressure inside the process container becomes a process pressure. A start timing of the act of supplying the process gas is adjusted with respect to a start timing of the act of performing the pressure control to adjust a thickness of a film formed on a substrate arranged on an upper portion of the plurality of substrates.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 21, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Tatsuru Matsuoka
  • Patent number: 10529618
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first insulting layer on a substrate, forming a first conductor pattern in the first insulating layer, forming a second insulating layer on the first insulating layer, and forming a second wiring pattern and a contact via in the second insulating layer, wherein a top surface of the first insulating layer is higher than a top surface of the first conductor pattern.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Siqing Lu, Sang-Hoon Ahn, Xinglong Chen, Ki-Hyun Kim, Kyu-In Shim
  • Patent number: 10504723
    Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xuebin Li, Hua Chung, Flora Fong-Song Chang, Schubert S. Chu, Abhishek Dube
  • Patent number: 10451977
    Abstract: A method of reducing an aberration of a lithographic apparatus, the method including measuring the aberration, taking the measured aberration into account, estimating a state of the lithographic apparatus, calculating a correction using the estimated state, and applying the correction to the lithographic apparatus.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 22, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Nick Kant, Nico Vanroose, Johannes Jacobus Matheus Baselmans
  • Patent number: 10407773
    Abstract: Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed precursor by purging the processing chamber with a primary purge gas, and thereafter reacting adsorbed film precursor while a secondary purge gas is flowed into the processing chamber, resulting in the formation of a film layer on the substrate. The secondary purge gas may include a chemical species having an ionization energy and/or a disassociation energy equal to or greater than that of O2. Also disclosed are apparatuses which implement the foregoing processes.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 10, 2019
    Assignee: Lam Research Corporation
    Inventors: Adrien LaVoie, Hu Kang, Purushottam Kumar, Shankar Swaminathan, Jun Qian, Frank L. Pasquale, Chloe Baldasseroni
  • Patent number: 10366898
    Abstract: Techniques are disclosed for methods and apparatuses for performing continuous-flow plasma enhanced atomic layer deposition (PEALD). Plasma gas, containing one or more component gases, is continuously flowed to a planar inductive coupled plasma source attached at an upper end of a cylindrical chamber. Plasma is separated from the ALD volume surrounding a wafer/substrate in the lower end of the chamber by a combination of a grounded metal plate and a ceramic plate. Each plate has a number of mutually aligned holes. The ceramic plate has holes with a diameter less than 2 Debye lengths and has a large aspect ratio. This prevents damaging plasma flux from entering the ALD volume into which a gaseous metal precursor is also pulsed. The self-limiting ALD reaction involving the heated substrate, the excited neutrals from the plasma gas, and the metal precursor produce an ultra-uniform, high quality film on the wafer. A batch configuration to simultaneously coat multiple wafers is also disclosed.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Nano-Master, Inc.
    Inventor: Birol Kuyel
  • Patent number: 10361088
    Abstract: Techniques are disclosed for methods and apparatuses for performing continuous-flow plasma enhanced atomic layer deposition (PEALD). Plasma gas, containing one or more component gases, is continuously flowed to a planar inductive coupled plasma source attached at an upper end of a cylindrical chamber. Plasma is separated from the ALD volume surrounding a wafer/substrate in the lower end of the chamber by a combination of a grounded metal plate and a ceramic plate. Each plate has a number of mutually aligned holes. The ceramic plate has holes with a diameter less than 2 Debye lengths and has a large aspect ratio. This prevents damaging plasma flux from entering the ALD volume into which a gaseous metal precursor is also pulsed. The self-limiting ALD reaction involving the heated substrate, the excited neutrals from the plasma gas, and the metal precursor produce an ultra-uniform, high quality film on the wafer. A batch configuration to simultaneously coat multiple wafers is also disclosed.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 23, 2019
    Assignee: Nano-Master, Inc.
    Inventor: Birol Kuyel
  • Patent number: 10276363
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10229829
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 12, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshinobu Nakamura, Kiyohiko Maeda, Yoshiro Hirose, Ryota Horiike, Yoshitomo Hashimoto
  • Patent number: 10191338
    Abstract: An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: January 29, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chin-Yueh Liao, Yi-Chun Kao
  • Patent number: 10026745
    Abstract: A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Han Wang, Xian Feng Du
  • Patent number: 9997617
    Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Xia Li, Periannan Chidambaram
  • Patent number: 9947530
    Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Jo Tak, Sam Mook Kang, Mi Hyun Kim, Jun Youn Kim, Young Soo Park
  • Patent number: 9934962
    Abstract: A method of manufacturing a semiconductor device includes a process of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor containing a predetermined element to the substrate; supplying a first reactant containing nitrogen and carbon to the substrate; supplying a second reactant containing nitrogen to the substrate; and supplying a third reactant containing oxygen to the substrate, wherein in the cycle, a supply amount of the second reactant is set to be smaller than a supply amount of the first reactant.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 3, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Tatsuru Matsuoka
  • Patent number: 9917182
    Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Kohei Oasa, Takuo Kikuchi, Junji Kataoka, Tatsuya Shiraishi, Akira Yoshioka, Kazuo Saki
  • Patent number: 9892814
    Abstract: A method for forming an electrically conductive oxide film (1) on a substrate (2), the method comprising the steps of, bringing the substrate (2) into a reaction space, forming a preliminary deposit on a deposition surface of the substrate (2) and treating the deposition surface with a chemical. The step of forming the preliminary deposit on the deposition surface of the substrate (2) comprises forming a preliminary deposit of transition metal oxide on the deposition surface and subsequently purging the reaction space. The step of treating the deposition surface with a chemical comprises treating the deposition surface with an organometallic chemical and subsequently purging the reaction space, to form oxide comprising oxygen, first metal and transition metal. The steps of forming the preliminary deposit and treating the deposition surface being alternately repeated such that a film (1) of electrically conductive oxide is formed on the substrate (2).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 13, 2018
    Assignee: Beneq Oy
    Inventor: Jarmo Maula
  • Patent number: 9882022
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9842881
    Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: December 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Jong-Han Shin, Ki-Seon Park
  • Patent number: 9824895
    Abstract: A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 9816181
    Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: November 14, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9777370
    Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: October 3, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9761436
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9732426
    Abstract: According to the present disclosure, a film containing carbon added at a high concentration is formed with high controllability. A method of manufacturing a semiconductor device includes forming a film containing silicon, carbon and a predetermined element on a substrate by performing a cycle a predetermined number of times. The predetermined element is one of nitrogen and oxygen. The cycle includes supplying a precursor gas containing at least two silicon atoms per one molecule, carbon and a halogen element and having an Si—C bonding to the substrate, and supplying a modifying gas containing the predetermined element to the substrate.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: August 15, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Yoshiro Hirose, Atsushi Sano
  • Patent number: 9711348
    Abstract: The present invention increases controllability of a composition ratio of a multi-element film that contains a predetermined element and at least one element selected from the group consisting of boron, oxygen, carbon and nitrogen. There is provided a method of manufacturing a semiconductor device, including: forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming the first film being free of borazine ring structure and including a predetermined element and at least one element selected from the group consisting of oxygen, carbon and nitrogen; and (b) forming the second film having a borazine ring structure and including at least boron and nitrogen.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 18, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9685533
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: February 21, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9653319
    Abstract: Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 16, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Anton J. deVilliers, Kaushik Kumar
  • Patent number: 9537044
    Abstract: A method for manufacturing an optoelectric device comprising a semiconductor substrate, pads on a surface of the substrate; semiconductor elements, each element being in contact with a pad; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair, the method successively comprising the forming of the pads and the forming of the region, wherein the region is formed by nitriding of the substrate, the method comprising the successive steps of: depositing a layer on the substrate; forming portions on the layer; etching the parts of the layer which are not covered with the portions to form the pads; removing the portions; and nitriding the pads and the parts of the substrate which are not covered with the pads, wherein the nitriding step successively comprises: a first step of nitriding of the pads at a first temperature; and a second step of nitriding of the parts of the substrate which are not covered with
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: January 3, 2017
    Assignees: ALEDIA, Commissariat A L'Energie Atomique Et Aux Energies
    Inventors: Philippe Gilet, Xavier Hugon, David Vaufrey, Hubert Bono, Bérangère Hyot
  • Patent number: 9464351
    Abstract: A method of fabricating a light-scattering substrate, a light-scattering substrate fabricated by the same method, and an organic light-emitting device (OLED) including the same light-scattering substrate, in which a light-scattering layer of the light-scattering substrate can improve a light extraction efficiency. The method fabricates the light-scattering substrate by chemical vapor deposition, and includes loading a base substrate into a chamber, and forming a light-scattering layer on the base substrate by supplying a Ti source and an oxidizer including H2O into the chamber. In the process of forming the light-scattering layer, the mole ratio of the H2O with respect to the Ti is 10 or greater.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: October 11, 2016
    Assignee: CORNING PRECISION MATERIALS CO., LTD.
    Inventors: Gun Sang Yoon, Hyun Bin Kim, June Hyoung Park
  • Patent number: 9460916
    Abstract: An object of the present invention is to form a good thin film while suppressing generation of foreign substances in a low temperature region. Provided is a method of manufacturing a semiconductor device, including: (a) forming a thin film containing at least a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element and a halogen element to the substrate in a process container; and (a-2) supplying a reaction gas composed of carbon, nitrogen, and hydrogen to the substrate in the process container; and (b) modifying byproduct adhered to an inside of the process container by supplying a nitriding gas into the process container after (a).
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 4, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Yugo Orihashi, Yoshitomo Hashimoto, Yoshiro Hirose
  • Patent number: 9436080
    Abstract: The invention relates to a method for correcting at least one error on wafers processed by at least one photolithographic mask, the method comprises: (a) measuring the at least one error on a wafer at a wafer processing site, and (b) modifying the at least one photolithographic mask by introducing at least one arrangement of local persistent modifications in the at least one photolithographic mask.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 6, 2016
    Assignees: Carl Zeiss SMS GmbH, Carl Zeiss SMS Ltd.
    Inventors: Dirk Beyer, Vladimir Dmitriev, Ofir Sharoni, Nadav Wertsman
  • Patent number: 9425039
    Abstract: Provided is a technique of controlling a work function of a metal film. A composite metal nitride film is formed on a substrate present in a process chamber by alternately supplying a first source and a second source to the substrate, wherein the first source contains a first metal element, the second source contains an ethyl ligand and a second metal element that is different from the first metal element, and a bond between the second metal element and a nitrogen element in the composite metal nitride film has crystallinity.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: August 23, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuhiro Harada, Arito Ogawa
  • Patent number: 9425075
    Abstract: The present disclosure suppresses oxidation of a base film on a substrate surface during the formation of an oxide film. A method of manufacturing a semiconductor device according to the present disclosure includes forming an initial layer including a predetermined element and having a thickness of several atomic layers on a substrate in a process chamber by supplying a predetermined-element-containing gas to the substrate, and forming an oxide film including the predetermined element on the initial layer by performing a cycle a predetermined number of times, the cycle including supplying a precursor gas including the predetermined element to the substrate in the process chamber and supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in the process chamber under a pressure lower than an atmospheric pressure.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 23, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose, Naonori Akae
  • Patent number: 9385031
    Abstract: According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: July 5, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Rogalli, Wolfgang Lehnert
  • Patent number: 9379275
    Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
  • Patent number: 9330903
    Abstract: Provided a method including forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times under a condition where a borazine ring structure in a fourth process gas is maintained. The cycle includes: (a) forming the first film by performing a first set a predetermined number of times, wherein the first set includes supplying a first process gas and supplying a second process gas to the substrate; and (b) forming the second film by performing a second set a predetermined number of times, wherein the second set includes supplying a third process gas and supplying the fourth process gas to the substrate.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 3, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9287282
    Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ta Hsieh, Po-Wei Liu, Yong-Shiuan Tsair, Chieh-Fei Chiu
  • Patent number: 9287124
    Abstract: In one embodiment, a method is proposed for etching a boron dope hardmask layer. The method includes flowing a process gas comprising at least CH4 into a processing chamber. Forming a plasma in the process chamber from the process gas and etching the boron doped hardmask layer in the presence of the plasma. In other embodiments, the process gas utilized to etch the boron doped hardmask layer includes CH4, Cl2, SF6 and O2.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 15, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Byungkook Kong, Jun Wan Kim, Wonmo Ahn, Jeong Hyun Yoo, Hun Sang Kim
  • Patent number: 9231189
    Abstract: A sodium niobate powder includes sodium niobate particles having a shape of a cuboid and having a side average length of 0.1 ?m or more and 100 ?m or less, wherein at least one face of each of the sodium niobate particles is a (100) plane in the pseudocubic notation and a moisture content of the sodium niobate powder is 0.15 mass % or less. A method for producing a ceramic using the sodium niobate powder is provided. A method for producing a sodium niobate powder includes a step of holding an aqueous alkali dispersion liquid containing a niobium component and a sodium component at a pressure exceeding 0.1 MPa, a step of isolating a solid matter from the aqueous dispersion liquid after the holding, and a step of heat treating the solid matter at 500° C. to 700° C.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: January 5, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoaki Masubuchi, Toshiaki Aiba, Toshihiro Ifuku, Makoto Kubota, Takayuki Watanabe, Tatsuo Furuta, Jumpei Hayashi
  • Patent number: 9112012
    Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 18, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventor: Jianguang Chang
  • Patent number: 9105531
    Abstract: A first photosensitive organic insulating film (PO1) formed in contact with a passivation film (PL) covers the entire circumference of a stepped portion (TRE) at a surface of the passivation film PL formed by a topmost conductive layer (TCL) and has an outer circumferential edge (ED1) positioned, along the entire circumference, on the outer circumferential side with respect to the stepped portion (TRE). This can prevent the first photosensitive organic insulating film (PO1) from peeling off the passivation film (PL).
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 11, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuo Tomita
  • Patent number: 9087695
    Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: July 21, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Igor Agafonov, Jinwei Yang, Michael Shur, Remigijus Gaska