Abstract: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming access gates which are self-aligned with both side walls of the mask pattern, over a top of the gate oxide layer; removing the mask pattern; forming first dielectric spacers to be attached to side walls of the access gates; forming an insulating layer adapted to cover the access gates and the first dielectric spacers; and forming two cell gates, which are self-aligned with opposite side walls of the two access gates, respectively, each first dielectric spacer being interposed between a corresponding cell gate and a corresponding access gate, the cell gates separately arranged over a top of the insulating layer.

Abstract: Embodiments relate to forming a pre-metal dielectric (PMD) layer. According to embodiments, the method may include depositing material of which the pre-metal dielectric layer is made on a semiconductor substrate through a chemical vapor deposition (CVD) process employing a high frequency (HF) power in a range from about 2550 mW to about 2650 mW; and polishing the material to form the pre-metal dielectric layer.

Abstract: A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.

Abstract: A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress.

Abstract: One or more passivation layers are added to the end of a semiconductor process flow to provide additional protection for devices (e.g., transistors) formed during the process. An additional layer is then formed and/or an anneal is performed to mitigate threshold voltage shifting that may be induced by the passivation layers. Mitigation of threshold voltage shifting increases the life expectancy of devices (e.g., transistors) formed during the process, which in turn mitigates yield loss by facilitating predictable or otherwise desirable behavior of the devices (e.g., transistors).

Abstract: A method for manufacturing a semiconductor device featuring a high-stress dielectric layer is disclosed. The method involves the deposition of a comparatively thick liner layer that exerts increased strain on an underlying gate and active areas, resulting in enhanced carrier mobility through the transistor and heightened transistor performance. The method also involves the amelioration of fabrication problems that might arise from the deposition of a comparatively thick liner layer by forming such layer with at least a partially direction deposition process. Also disclosed are semiconductor devices manufactured in accordance with the disclosed methods.

Abstract: A method of manufacturing a semiconductor device for minimizing stress applied to a gate oxide layer or a tunnel oxide layer includes the steps of providing a semiconductor substrate in which a semiconductor device including a word line is formed, forming a capping layer including a first insulating layer having a compressive characteristic and a second insulating layer having a tensile characteristic on an entire surface of the substrate including the word line, and forming an interlayer insulating layer on the capping layer. In another aspect, the method also includes the steps of providing a semiconductor substrate in which a semiconductor device including a word line is formed, forming a capping layer on the entire surface including the word line by alternately forming a first insulating layer of a PECVD method and a second insulating layer of a LPCVD method, and forming an interlayer insulating layer on the capping layer.

Abstract: A semiconductor device including a first insulating layer having a hydroxyl radical formed over a semiconductor substrate; a line layer having a plurality of line patterns formed over the first insulating layer, the plurality if line patterns being arranged such that a spatial gap is provided therebetween; a fluorine-doped second insulating layer formed in the spatial gap between respective line patterns; and a multilayered diffusion prevention layer including a first oxide layer for suppressing an increase of a dielectric constant between the plurality of line patterns and a second oxide layer for preventing the diffusion of fluorine from the fluorine-doped second insulating layer into the first insulating layer.

Abstract: A method for manufacturing semiconductor device according to the present invention comprises a first film forming step of forming, on a concave and convex portion formed by an element on a semiconductor substrate, an oxidation preventive layer which prevents permeation of moisture into the element; a second film forming step of forming, on this oxidation preventive layer, an expansion layer which can be oxidized and expanded by a heat treatment in an oxidation atmosphere; a third film forming step of forming, on this expansion layer, an insulating film which can be fluidized by the heat treatment in the oxidation atmosphere; and an expansion step of subjecting, to the heat treatment in the oxidation atmosphere, the semiconductor substrate on which the oxidation preventive layer, the expansion layer and the insulating film have been formed, to fluidize the insulating film and to oxidize and expand the expansion layer, thereby eliminating bubbles generated in the insulating film.

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: A gate insulating layer in a semiconductor device and a method of forming the same. In one example embodiment, a gate insulating layer in a semiconductor device includes an oxide layer, a first oxynitride layer formed between a semiconductor substrate and the oxide layer, and a second oxynitride layer formed on the oxide layer.

Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.

Abstract: The invention relates to a laminated layer structure that includes a substrate and a stack of a plurality of layers of a material that includes at least two compounds A and B, wherein compound A has a crystalline structure being sufficient to allow a homo- or heteroepitaxial growth of compound A on the substrate, and wherein at least a part of the layers of the stack have a gradient composition AxB(1-xg), with x being a composition parameter within the range of 0 and 1 and with the composition parameter (1-xg) increasing gradually, in particular linearly, over the thickness of the corresponding layer. In order to improve the quality of the laminated layer structure with respect to the surface roughness and dislocation density, the composition parameter at the interface between the layer in the stack with the gradient composition and the subsequent layer in the stack is chosen to be smaller than the composition parameter (1-xg) of the layer with a gradient composition.

Abstract: Embodiments relate to a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and a method of fabricating a MOSFET. According to embodiments, a method of forming a MOSFET may include forming a first gate insulating layer on a semiconductor substrate, nitrifying the first gate insulating layer, forming a second gate insulating layer on the first gate insulating layer, injecting fluorine ions into the second gate insulating layer, and diffusing the fluorine ions into the first gate insulating layer.

Abstract: A method of forming a coating. The method includes: providing a substrate having a surface; forming a layer of water on the surface; and forming a layer of a material on the layer of water.

Abstract: Methods for forming compositions comprising a single-phase rare-earth dielectric disposed on a substrate are disclosed. In some embodiments, the method forms a semiconductor-on-insulator structure. Compositions and structures that are formed via the method provide the basis for forming high-performance devices and circuits.

Abstract: A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.

Abstract: Various semiconductor devices and method of manufacturing the same are provided. In one aspect, a method of manufacturing is provided that includes forming an insulating layer on a backside of a semiconductor chip and forming a metallic thermal interface material on the insulating layer. In another aspect, an integrated circuit is provided that includes a semiconductor chip that has a front side and a backside. An insulating layer is on the backside and a metallic thermal interface material is on the insulating layer.

Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.

Abstract: A method of forming a gate dielectric comprising silicon and oxygen is provided. The gate dielectric may also include nitrogen or another high k material. In one aspect, forming the gate dielectric includes annealing a substrate in an oxidizing atmosphere to form a silicon oxide layer, depositing a silicon nitride layer or a high k layer on the silicon oxide layer by a vapor deposition, oxidizing an upper surface of the silicon nitride layer or high k layer, and then annealing the substrate. The gate dielectric may be formed within an integrated processing system.

Abstract: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

Abstract: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion barrier layer (5). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer (5) and a diffusion solder layer is provided as the solder layer (6). All three layers are applied by sputtering in a process sequence.

Abstract: In one embodiment the present invention is a method of conducting multiple step multiple chamber chemical vapor deposition while avoiding reactant memory in the relevant reaction chambers. The method includes depositing a layer of semiconductor material on a substrate using vapor deposition in a first deposition chamber followed by evacuation of the growth chamber to reduce vapor deposition source gases remaining in the first deposition chamber after the deposition growth and prior to opening the chamber. The substrate is transferred to a second deposition chamber while isolating the first deposition chamber from the second deposition chamber to prevent reactants present in the first chamber from affecting deposition in the second chamber and while maintaining an ambient that minimizes or eliminates growth stop effects. After the transferring step, an additional layer of a different semiconductor material is deposited on the first deposited layer in the second chamber using vapor deposition.

Abstract: Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole.

Abstract: In the case of a chip (1) having an integrated circuit (2), a dielectric mirror coating (3) having at least two dielectric layers (6, 7, . . . H, I, H) is applied as light protection means for the at least one integrated circuit (2) on at least one portion of the surface of the chip (1).

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode includes an upper layer and a lower layer stacked on the gate insulating layer. The oxide layer is formed on the gate electrode. The lower layer and the upper layer can have different oxidation rates. The sidewalls are formed on the oxide layer.

Abstract: The method for avoiding polysilicon film over etch abnormal includes cleaning a semiconductor substrate. A dielectric layer is formed on the substrate. Subsequently, a first silicon source gas at a first flow rate is next performed injecting into a reaction chamber to form a first polysilicon film over the dielectric layer. Successively, a second silicon source gas at a second flow rate is performed injecting into the reaction chamber to form a second polysilicon film over the first polysilicon film, wherein the second silicon source gas having a different growth rate than the first silicon source gas. A patterned photoresist layer is then formed on the second polysilicon film. After the patterned photoresist layer is formed, a dry etching process by way of using the patterned photoresist layer as a etching mask is performed to etch through in turn the second polysilicon film and the first polysilicon film till exposing to the dielectric layer. Finally, the photoresist layer is removed.

Abstract: The present invention provides a coating process for patterned substrate surfaces, in which a substrate (101) is provided, the substrate having a surface (105) which is patterned in a substrate patterning region (102) and has one or more trenches (106) that are to be filled to a predetermined filling height (205), a catalyst layer (201) is introduced into the trenches (106) that are to be filled, a reaction layer (202) is deposited catalytically in the trenches (106) that are to be filled, the catalytically deposited reaction layer (202) is densified in the trenches (106) that are to be filled, and the introduction of the catalyst layer (201) and the catalytic deposition of the reaction layer (202) are repeated until the trenches (106) that are to be filled have been filled to the predetermined filling height (205).

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of memory cells and transistors over a substrate, forming a first stopping layer having tensile stress over the plurality of memory cells and transistors, forming a first insulation layer over the substrate and the first stopping layer, and forming a second stopping layer having compression stress over the first insulation layer.

Abstract: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to an alkyl silane, an alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an aryl silane, an acyl silane, a cyclo siloxane, a polysilsesquioxane (PSS), an aryl siloxane, an acyl siloxane, or a halo siloxane, or any combination thereof. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue.

Abstract: A method for forming a metal line of a semiconductor device forms an aluminum line having an excellent orientation. A specific resistance of a metal line is reduced, thereby enabling sufficient supply of a desired electric current. The method includes steps of forming a lower reflection preventing layer on a silicon wafer, forming a first aluminum layer on the lower reflection preventing layer, forming a second aluminum layer on the first aluminum layer, lowering a surface roughness of the second aluminum layer, forming an upper reflection preventing layer on the second aluminum layer, and forming an aluminum line.

Abstract: A method for protecting an alignment mark on a semiconductor substrate, includes forming a dielectric layer on the semiconductor substrate having the alignment mark, forming a cap oxide film on the dielectric layer, wherein the cap oxide film is formed to have a regular thickness and an additional thickness, etching a portion of the dielectric layer and the cap oxide film to expose the semiconductor substrate to thereby form a via hole, filling the via hole with a metal, and performing a chemical mechanical polishing process with the metal and the cap oxide film to form a via contact.

Abstract: Methods for improving an adhesive force between thin films of a semiconductor device. In one example embodiment, a method for improving an adhesive force between an HDP-CVD (High Density Plasma-Chemical Vapor Deposition) thin film and a nitride film includes forming a HDP-CVD thin film according to an HDP-CVD method in order to exert a compressive stress against a lower structure, and forming a nitride film on the HDP-CVD thin film that exerts a tensile stress that substantially cancels out the compressive stress.

Abstract: A method of manufacturing a semiconductor device, wherein an interlayer insulating layer, a lower barrier metal layer, a metal layer having a low resisvitity value, an upper barrier metal layer, a first oxynitride layer, a hard mask layer formed at low temperature, a second oxynitride layer, and an organic Bottom Anti-Reflective Coating (BARC) layer are formed over a semiconductor substrate. The BARC layer, the second oxynitride layer, and the hard mask layer are etched. The first oxynitride layer, the upper barrier metal layer, the metal layer, and the lower barrier metal layer are etched using the hard mask layer as a mask.

Abstract: The invention relates to a self-adjusting serial connection of thin layers and a method for the production thereof. The invention is characterized in that electrically conducting conductor tracks (20) are applied to a substrate (10), whereupon several main deposit layers (30, 40, 50) of conducting, semi-conducting or insulating materials are applied to the substrate. The application of the layers is carried out at various angles of incidence to the surface of the substrate.

Abstract: A semiconductor device capable of improving a mechanical strength of a porous silica film while inhibiting a film located on a lower layer of the porous silica film from deterioration is obtained. This semiconductor device includes an organic film formed on a semiconductor substrate, an ultraviolet light permeation suppressive film, formed on a surface of the organic film, composed of a material which is difficult to be permeable by ultraviolet light, and a first porous silica film formed on a surface of the ultraviolet light permeation suppressive film.

Abstract: A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer deposition.

Abstract: A method for forming a nitrogen-containing gate insulating film includes the steps of forming a silicon oxide film on a silicon substrate, nitriding the top portion of the silicon oxide film to form a thin silicon nitride layer, and forming a silicon nitride film on the silicon nitride layer by using an atomic layer deposition process, to obtain a gate insulating film having a higher nitrogen concentration, while suppressing the nitrogen concentration in the vicinity of the gate insulating film and the silicon substrate.

Abstract: A method of manufacturing a patterned electric circuit. The method comprises the steps of providing a cold gas-dynamic spraying (CGDS) device, providing a substrate, and depositing a pattern of electrically conductive material with the CGDS device on the substrate by relative movement between the CGDS device to the substrate.

Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device can include at least two gate structures spaced apart from each other on a semiconductor substrate, a silicon nitride layer covering the semiconductor substrate and the gate structures, an interlayer dielectric layer on the silicon nitride layer, and a buffer layer interposed between the silicon nitride layer and the interlayer dielectric layer to buffer stress between the silicon nitride layer and the interlayer dielectric layer. The buffer layer has a tensile stress characteristic, while the silicon nitride layer and the interlayer dielectric layer have a compressive stress characteristic. Therefore, the buffer layer buffers the compressive stress of both the silicon nitride layer and the interlayer dielectric layer. Accordingly, the delamination or the damage of the silicon nitride layer and the interlayer dielectric layer is inhibited.

Abstract: When microfabrication is done, a reliable semiconductor device is offered. A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.

Abstract: Methods for forming a gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a silicon substrate, depositing a silicon nitride layer on the silicon oxide layer by a thermal process, wherein the silicon oxide layer and the silicon nitride layer are utilized as a gate dielectric layer in a gate structure, and thermally annealing the substrate. In another embodiment, the method includes forming a silicon oxide layer on the silicon substrate with a thickness less than 15 ?, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer with a thickness less than 15 ? by a thermal process, wherein the silicon oxide layer and the silicon nitride layer are utilized as a gate dielectric layer in a gate structure, plasma treating the silicon nitride layer; and thermally annealing the substrate.

Abstract: A semiconductor assembly providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices is disclosed. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.

Abstract: The present invention relates to a method for fabricating a semiconductor device capable of preventing bridge formation caused by damages to a capacitor oxide structure including a phosphosilicate glass (PSG) layer and a tetraethylorthosilicate (TEOS) layer during a wet cleaning process. The method includes the steps of: forming a PSG layer on a substrate; forming a capping layer on the PSG layer; forming a TEOS layer on the capping layer; selectively etching the TEOS layer, the capping layer and the PSG layer to form a plurality of openings exposing predetermined portions of the substrate; cleaning the openings; forming a conductive layer on the openings; and removing the conductive layer until the TEOS layer is exposed, so that the conductive layer is isolated for each opening.

Abstract: The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.