Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 107 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.

Abstract: The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.

Abstract: The invention includes inserting an object to be processed into a processing vessel, which can be maintained vacuum, and making the processing vessel vacuum; performing a sequence of forming a ZrO2 film on a substrate by alternately supplying zirconium source and an oxidizer into the processing vessel for a plurality of times and a sequence of forming SiO2 film on the substrate by alternately supplying silicon source and an oxidizer into the processing vessel for one or more times, wherein the number of times of performing each of the sequences is adjusted such that Si concentration of the films is from about 1 atm % to about 4 atm %; and forming a zirconia-based film having a predetermined thickness by performing the film forming sequences for one or more cycles, wherein one cycle indicates that each of the ZrO2 film forming sequences and the SiO2 film forming sequences are repeated for the adjusted number of times of performances.

Abstract: A wirebond interconnect structure, having ground pads and signal pads, to which wirebonds are electrically coupled, disposed on a component, is provided and includes a first coating to insulate at least the wirebonds and the signal pads with at least the ground pads exposed, and a second coating, surrounding the first coating, in electrical communication with the ground pads. The first coating is sufficiently thick to achieve a consistent characteristic impedance when the second coating is applied.

Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.

Abstract: A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVB) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVA); and M?xOy, where M? is a second metal species selected from the group 3 (IIIA) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.

Abstract: To provide a manufacturing method of a semiconductor device for forming a diffusion layer by diffusing phosphorus atoms on a surface of a silicon substrate on which resist is applied, including the step of forming a diffusion layer, with a temperature of the silicon substrate maintained lower than a deterioration temperature of the resist.

Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.

Abstract: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or other silicon-containing materials. The photoexcitation process may expose the substrate and/or gases to an energy beam or flux prior to, during, or subsequent a deposition process. Therefore, the photoexcitation process may be used to pre-treat or post-treat the substrate or material, to deposit the silicon-containing material, and to enhance chamber cleaning processes.

Abstract: The major objective is to provide a fluorocarbon film wherein fine voids are formed by a step (SA1) for introducing a mixed gas containing a first carbon fluoride gas and a second carbon fluoride gas on a substrate placed inside a chamber, and depositing a fluorocarbon film on the substrate; and a step (SA2) for forming voids in the fluorocarbon film by selectively removing volatile components contained in the fluorocarbon film are included and especially in the step (SA2) for forming voids, it is preferable to include a step for cleaning the fluorocarbon film with a supercritical fluid.

Abstract: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: In one embodiment, a high voltage semiconductor device is formed with a first dielectric layer and a charge stabilization layer comprising a flowable glass formed over the first dielectric layer.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

Abstract: A method for forming an amorphous silicon thin film is disclosed. In some embodiments, a method includes loading a substrate into a reaction chamber; and conducting a plurality of deposition cycles on the substrate. Each of at least two of the cycles includes: supplying a silicon precursor to the reaction chamber during a first time period; applying radio frequency power to the reaction chamber at least partly during the first time period; stopping supplying of the silicon precursor and applying of the radio frequency power during a second time period between the first time period and an immediately subsequent deposition cycle; and supplying hydrogen plasma to the reaction chamber during a third time period between the second time period and the immediately subsequent deposition cycle. The method allows formation of an amorphous silicon film having an excellent step-coverage and a low roughness at a relatively low deposition temperature.

Abstract: The present invention relates to a method for fabricating thin film transistor, more particularly, to a method for fabricating thin film transistor which not only manufactures a polycrystalline silicon layer having large grain size and containing a trace of residual metal catalyst by heat treating thereby crystallizing the metal catalyst layer after forming an amorphous silicon layer on a substrate, forming a capping layer formed of nitride film having 1.78 to 1.90 of the refraction index when crystallizing the amorphous silicon layer and forming a metal catalyst layer on the capping layer, but also controls characteristics of the polycrystalline silicon layer by controlling the refraction index of the capping layer.

Abstract: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

Abstract: A method for fabricating a porous low-k dielectric film includes providing a substrate, performing a first CVD process by providing a back-bone precursor to form an interface dielectric layer, performing a second CVD process by providing a porogen precursor to form a back-bone layer, and removing the porogen material in the back-bone layer so that the back-bone layer becomes an ultra low-k dielectric layer. The interface dielectric layer and the ultra low-k dielectric layer compose a porous low-k dielectric film.

Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.

Abstract: Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.

Abstract: Variation in the thickness of the deposited films depending on number of the processed product wafers in the deposition process employing a batch type CVD apparatus is inhibited to provide a manufacture of the film having a predetermined thickness with an improved reproducibility. The deposition apparatus 100 comprises a deposition reactor 101 that is capable of containing product wafers 107 and dummy wafers 109, boat 105, on which product wafer 107 or the dummy wafer 109 is mounted, and a heater 111 provided outside of the deposition reactor 101 along a reactor wall 103. Further, the deposition apparatus 100 comprises a gas supplying system including a high-k source material supplying line 113 and SiO2 source material supplying line 115, and a controller 121 that provides a control to the supply of a gas from the gas supplying system to the deposition reactor 101.

Abstract: A film formation method for a semiconductor process performs a film formation process to form a silicon-containing insulating film doped with a metal on a target substrate, in a process field inside a process container configured to be selectively supplied with a silicon source gas and a metal source gas. The method includes forming a first insulating thin layer by use of a chemical reaction of the silicon source gas, while maintaining a shut-off state of supply of the metal source gas; then, forming a first metal thin layer by use of a chemical reaction of the metal source gas, while maintaining a shut-off state of supply of the silicon source gas; and then, forming a second insulating thin layer by use of the chemical reaction of the silicon source gas, while maintaining a shut-off state of supply of the metal source gas.

Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.

Abstract: A semiconductor memory device has a cover film (5), between a memory cell (gate electrode 4, and source and drain regions 2a and 2b) and an interlayer insulating film (6), the cover film covering the memory cell, wherein the cover film (5) has a hydrogen storage film (5a) that is a coating film on a surface of a silicon nitride film (5b), and in addition, has a hydrogen storage film (5c) on a bottom surface of the silicon nitride film (5b). The hydrogen storage films (5a and 5b) are silicon nitride oxide films that include Si2N2O. By suppressing diffusion of hydrogen atoms to a memory cell from an interlayer insulating film, reliability of operation of the memory cell is improved.

Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming a plurality of gate lines on a substrate by performing an etching process; forming an oxide layer on the gate lines and the substrate by employing an atomic layer deposition (ALD) method; and sequentially forming a buffer oxide layer and a nitride layer on the oxide layer.

Abstract: A method of forming a charge pattern includes treating a stamp layer with a plasma, applying the treated stamp layer to a surface of a substrate to thereby form a charge pattern on the surface of the substrate, and separating the stamp layer from the surface of the substrate. In one aspect, the method includes depositing nanoparticles on the surface of the substrate. An apparatus made in accordance with the method is also provided.

Abstract: A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the subsequent converting step includes oxidizing a metal atomic layer to form a metal oxide layer. The atomic layer deposition and oxidation step are then repeated to produce a metal oxide layer having sufficient thickness for use as a metal oxide layer in an integrated circuit. The subsequent converting step, in an embodiment, includes converting the atomic deposition layer by exposing it to one of nitrogen to form a nitride layer, carbon to form a carbide layer, boron to form a boride layer, and fluorine to form a fluoride layer. Systems and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method are also described.

Abstract: A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

Abstract: In this invention, it provides a method for forming a pattern, which is capable of improving position control after a drop, which was discharged from a drop discharge apparatus, was landed on a substrate. In addition, it provides a drop discharge apparatus which is capable of improving drop position accuracy after it was landed. Further, it provides a method for manufacturing a semiconductor device which uses the drop discharge apparatus of this invention. This invention is characterized in that a drop which was discharged from a discharge part, or a substrate on which a drop is landed, is irradiated with a laser beam, and a landing position of a drop is controlled. By this invention, it is possible to form a pattern, without using a photolithography process.

Abstract: Methods of forming an insulating layer in a semiconductor device are provided in which a metal oxide layer is formed on a semiconductor structure that includes a plurality of gap regions thereon. A spin-on-glass layer is formed on the metal oxide layer, and then the semiconductor structure is heated to a temperature of at least about 400° C. The spin-on-glass layer may comprise a siloxane-based material, a silanol-based material or a silazane-based material.

Abstract: A method of suppressing parasitic particle formation in a metal organic chemical vapor deposition process is described. The method may include providing a substrate to a reaction chamber, and introducing an organometallic precursor, a particle suppression compound and at least a second precursor to the reaction chamber. The second precursor reacts with the organometallic precursor to form a nucleation layer on the substrate. Also, a method of suppressing parasitic particle formation during formation of a III-V nitride layer is described. The method includes introducing a group III metal containing precursor to a reaction chamber. The group III metal precursor may include a halogen. A hydrogen halide gas and a nitrogen containing gas are also introduced to the reaction chamber. The nitrogen containing gas reacts with the group III metal precursor to form the III-V nitride layer on the substrate.

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: The present invention relates to an organic/inorganic hybrid thin film passivation layer comprising an organic polymer passivation layer prepared by a UV/ozone curing process and an inorganic thin film passivation layer for blocking moisture and oxygen transmission of an organic electronic device fabricated on a substrate and improving gas barrier property of a plastic substrate; and a fabrication method thereof. Since the organic/inorganic hybrid thin film passivation layer of the present invention converts the surface polarity of an organic polymer passivation layer into hydrophilic by using the UV/ozone curing process, it can improve the adhesion strength between the passivation layer interfaces, increase the light transmission rate due to surface planarization of the organic polymer passivation layer, and enhance gas barrier property by effectively blocking moisture and oxygen transmission.

Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.

Abstract: A method for measuring the thickness of a layer is provided, comprising (a) providing a structure (101) comprising a first layer disposed on a second layer; (b) impinging (103) the structure with a first ion beam comprising a first isotope, thereby sputtering off a portion of the first layer which contains a second isotope and exposing a portion of the second layer; and (c) determining (105) the thickness of the first layer by measuring the amount of the second isotope which is sputtered off.

Abstract: A method for manufacturing an alignment layer is provided, which includes the following steps. First, a substrate is provided. Next, an auxiliary layer is formed on the substrate. Then, an alignment solution is sprayed on the auxiliary layer through an inkjet printing process. The alignment solution includes an alignment material and a first solvent, and the auxiliary layer has the same polarity as the first solvent. Then, by performing a curing process, the alignment solution is cured to form an alignment layer. As mentioned above, the method for manufacturing an alignment layer may be applied to manufacture an alignment layer with preferred smoothness.

Abstract: A semiconductor memory in which a gate insulating film (tunnel insulating film) in a memory cell provides higher operational reliability. The semiconductor memory includes an insulating film 3 between a silicon substrate 1 and a gate electrode 4. The insulating film 3 is composed of a silicon oxide film 3f, a silicon nitride film 3d and a silicon oxide film 3b, stacked in this order between the silicon substrate and the gate electrode from the side of the silicon substrate 1. There are provided hydrogen occluding films 3a, 3c and 3e on an interface between the silicon oxide film 3f and the silicon nitride film 3d, on an interface between the silicon nitride film 3d and the silicon oxide film 3b and on an interface between the silicon oxide film 3b and the gate electrode 4 (FIGS. 1A and 1B).

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough H2 in the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the H2 in a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO2:H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by N2 annealing or Ar annealing.

Abstract: A pattern evaluation method using a circuit arrangement provided with N (N is a natural number of 2 or greater) circuit groups having wiring whose widths are different to each other, each circuit group including first to Mth circuits having first to Mth (M is a natural number of 2 or greater) wiring formed of a conductive layer, respectively, each of the first to the Mth wiring having the same width that is electrically measurable, the pattern evaluation method includes: arranging patterns to be evaluated so that the Mth wiring or a layer in the vicinity thereof is locally removed; electrically calculating a first characteristic value indicating a characteristic of the first circuit including at least the wiring width of the first wiring; electrically calculating an Mth characteristic value which is a value indicating the characteristic of the Mth circuit and dependent on a geometric relationship between the pattern to be evaluated and the Mth wiring; and evaluating the characteristic of the pattern to be

Abstract: A method of producing metallic nanocrystals (107) embedded in high-k dielectric material as well as a nonvolatile flash memory device (100) comprising a discrete charge carrier storage layer, the discrete charge carrier storage layer comprising metallic nanocrystals (107) embedded in high-k dielectric material. In the method described in this invention, firstly an ultra-thin metal film is deposited over a first (105) and a second (106) dielectric layer including high-k dielectric material provided on a substrate (101). Then, the ultra-thin metal film is annealed for forming the metallic nanocrystals (107) on the second dielectric layer (106). Finally, the second dielectric layer (106) and the metallic nanocrystals (107) are covered with a third dielectric layer (108) of high-k dielectric material for forming metallic nanocrystals (107) embedded in high-k dielectric material.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer; forming a second oxide layer pattern by wet etching the second oxide layer by using the first photoresist layer pattern as a mask; forming a nitride layer pattern by dry etching the nitride layer using the second oxide layer pattern as a mask; and forming a first oxide layer pattern by etching the first oxide layer using the nitride layer pattern as a mask.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: A method for manufacturing an active matrix substrate, comprises forming a first conductive layer across a first wiring line forming area and a second wiring line forming area on a substrate including a first wiring line and a second wiring line having a width narrower than a width of the first wiring line, and forming a second conductive layer on the first conductive layer formed in the first wiring line forming area in a layered state, and on the first conductive layer formed in the second wiring line forming area in a non-layered state.

Abstract: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the side wall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and an oxide film 115 formed between the sidewall spacer 116 and the sidewall spacer 144, and the semiconductor substrate 10. The film thickness of the oxide film 115 between the sidewall spacer 144 and the semiconductor substrate 10 is thinner than the film thickness of the oxide film 115 between the sidewall spacer 116 and the semiconductor substrate 10.

Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

Abstract: Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor gas into the process chamber during the ALD process to produce the target characteristic in the layer of material, and performing the ALD process that comprises a plurality of steps wherein the precursor gas is introduced into the chamber for the determined precursor pulse time to thereby form the layer of material.