Abstract: Dielectric layers containing a hafnium oxide hafnium oxide layer arranged as one or more monolayers and a lanthanide oxide layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

Abstract: The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.

Abstract: A variable temperature and/or reactant dose atomic layer deposition (VTD-ALD) process modulates ALD reactor conditions (e.g., temperature, flow rates, etc.) during growth of a film (e.g., metallic) on a wafer to produce different film properties a different film depths.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.

Abstract: Methods of forming metal nitride layers on a substrate include reacting a metal source gas with a nitrogen source gas in a process chamber to form a metal nitride layer on the substrate. The process chamber may have an atmosphere having a pressure of about 0.1 mTorr to about 5 mTorr and a temperature of about 200° C. to about 450° C. A ratio of the flow rate of the metal source gas to the flow rate of the nitrogen source gas may be “1” or more. An interlayer insulating layer may be formed on the semiconductor substrate prior to formation of the metal nitride layer.

Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.

Abstract: A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High E/D ratio maintains the gap openings without necking. In the second step, a lower argon concentration and lower E/D ratio are used. Since observed metal defects are caused by argon diffusion in the top 200-300 nm of the HDP-CVD film, by controlling argon concentration in the top part of the film (i.e. second step deposition) to a low value, a reduced number of metal defects are achieved.

Abstract: Sequential processes are conducted in a batch reaction chamber to form ultra high quality silicon-containing compound layers, e.g., silicon nitride layers, at low temperatures. Under reaction rate limited conditions, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. Trisilane flow is interrupted. A silicon nitride layer is then formed by nitriding the silicon layer with nitrogen radicals, such as by pulsing the plasma power (remote or in situ) on after a trisilane step. The nitrogen radical supply is stopped. Optionally non-activated ammonia is also supplied, continuously or intermittently. If desired, the process is repeated for greater thickness, purging the reactor after each trisilane and silicon compounding step to avoid gas phase reactions, with each cycle producing about 5-7 angstroms of silicon nitride.

Abstract: The invention relates to a method for the production of automatically adjusting serial connections of thick and/or thin layers. The method comprises the following process steps: applying electrically conductive strip conductors (20) to a substrate (10); applying a first main layer (30) at an angle a relative to the surface of the substrate; applying a second main layer which is made of granular-shaped particles (40) to the substrate (10); applying several layers in conjunction with material and process-dependent processing steps; applying a third main layer (70) at an angle ? relative to the surface of the substrate; and applying a fourth main layer (80) at an angle y relative to the surface of the substrate.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a solution processed device are described.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: An apparatus and method for forming an integrated barrier layer on a substrate is described. The integrated barrier layer comprises at least a first refractory metal layer and a second refractory metal layer. The integrated barrier layer is formed using a dual-mode deposition process comprising a chemical vapor deposition (CVD) step and a cyclical deposition step. The dual-mode deposition process may be performed in a single process chamber.

Abstract: An insulating layer is formed on a semiconductor substrate, and has a through hole for via. A porous silica layer has a trench for interconnection communicating to the through hole for via, and is formed on the insulating layer in contact therewith. A conductive layer is formed in the through hole for via and in the trench for interconnection. The insulating layer is formed from a material containing carbon, hydrogen, oxygen, and silicon, and having absorption peak attributed to Si—CH3 bond in a range from at least 1260 cm?1 to at most 1280 cm?1 (around 1274 cm?1) when measured with FT-IR. Thus, a semiconductor device having a porous insulating layer in which depth of the trench for interconnection is readily controlled, a dielectric constant is low, and increase in leakage current is less likely, as well as a manufacturing method thereof can be obtained.

Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.

Abstract: A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is deposited in the presence of low frequency RF power from a gas mixture including an organosilicon compound and an oxidizing gas. The low frequency RF power is terminated after the deposition of the low dielectric constant film. The oxide rich cap is deposited on the low dielectric constant film in the absence of low frequency RF power from another gas mixture including the organosilicon compound and the oxidizing gas used to deposit the low dielectric constant film.

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12 and 1E15 ions/cc and more preferably between 1E14 and 1E15 ions/cc. The high bias has sufficient energy to break the F—Si bonds in the FSG. The high bias has sufficient energy to break the H—Si bonds in the silicon nitride. Whereby the FSG layer has less F and the SiN layer has less H that increases the FSG/SiN interface reliability. The embodiments can be used on smooth surfaces (non-gap fill applications).

Abstract: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

Abstract: A process for forming a patterned thin film structure on a substrate is disclosed. A pattern is printed with a material, such as a masking coating or an ink, on the substrate, the pattern being such that, in one embodiment, the desired thin film structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structures.

Abstract: Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling material. In the methods, the gas flow and RF bias are selected to provide a high etch to deposition ratio, while the trenches are partially filled. The gas flow and RF bias are then selected to provide a low etch to deposition ratio while the trenches are completely filled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method of forming isolated features of semiconductor devices is disclosed. A first hard mask is deposited over a material layer to be patterned, and a second hard mask is deposited over the first hard mask. The second hard mask is patterned with a pattern for an array of features using an off-axis lithography method. A portion of the pattern for the array of features is transferred to the first hard mask. The first hard mask is then used as a mask to pattern the material layer.

Abstract: It is an object of the present invention to improve the surface planarity of a film by uniforming the thickness of an insulating layer. Further, it is another object of the invention to provide a technology for manufacturing an electronic device typified by a high-definition and high-quality display device with high yield at low cost with the use of the insulating layer. In a method for manufacturing a semiconductor device according to the invention, a semiconductor layer is formed; an insulating layer is formed over the semiconductor layer; a wiring layer connected to the semiconductor layer is formed in an opening provided in the insulating layer; and an electrode layer connected to the wiring layer is formed. The insulating layer is formed by spin coating with a composition containing an insulating material, which has a viscosity of from 10 mPa·s to 50 mPa·s.

Abstract: A method of growing a crystal (for example, a GaN system compound semiconductor crystal) on a substrate at least includes forming a first crystalline layer (a GaN system buffer layer), forming a second crystalline layer (a GaN system intermediate layer) and forming a third crystalline layer (a GaN system thick film layer). The three crystalline layers are respectively reared on conditions different from one another.

Abstract: A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method of depositing tensile or compressively stressed silicon nitride on a substrate is described. Silicon nitride having a tensile stress with an absolute value of at least about 1200 MPa can be deposited from process gas comprising silicon-containing gas and nitrogen-containing gas, maintained in an electric field having a strength of from about 25 V/mil to about 300 V/mil. The electric field is formed by applying a voltage at a power level of less than about 60 Watts across electrodes that are spaced apart by a separation distance that is at least about 600 mils. Alternatively, silicon nitride having a compressive stress with an absolute value of at least about 2000 MPa can be formed in an electric field having a strength of from about 400 V/mil to about 800 V/mil.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 ?m is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.

Abstract: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to semiconductor manufacturing using a vacuum chamber. In one example, a method for semiconductor manufacturing includes: providing a photoresist layer for a wafer; removing solvent residues from the photoresist layer by using a vacuum chamber; and exposing the wafer.

Abstract: Embodiments relate to a passivation layer for a semiconductor device that may be formed in a substrate having a plurality of semiconductor devices. The passivation layer may includes a first passivation layer, a second passivation layer, and a third passivation layer, and the passivation layer may have a laminated triple layer structure.

Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.

Abstract: A method for forming a semiconductor device includes placing a Si substrate and an Sc2O3 powder source in an oxide chamber, and vaporizing the Sc2O3 powder source in the oxide chamber so as to form a single crystal Sc2O3 film on the Si substrate through electron beam evaporation techniques.

Abstract: Disclosed are a method of manufacturing a semiconductor device and a structure of a semiconductor device. A method of forming a passivation film of a semiconductor device comprises the steps of forming metal wires on a semiconductor substrate, forming a buffer oxide film being a first passivation film on the metal wires, wherein the buffer oxide film can mitigate damage by plasma, forming a high density plasma film being a second passivation film on the buffer oxide film, and forming a third passivation film on the second passivation film. According to the present invention, it is possible to significantly reduce the leakage current between a select source line and a common source line.

Abstract: The present invention discloses an improved shallow trench isolation process. A semiconductor substrate having a pad oxide disposed thereon and a pad nitride disposed directly on the pad oxide is provided. A trench is etched, through the pad oxide and the pad nitride, into the semiconductor substrate. A thermal oxide liner is then grown in the trench. A silicon nitride liner is deposited into the trench, wherein the silicon nitride liner covering the pad nitride and the thermal oxide liner has a first stress status. A stress alteration process is performed to alter the silicon nitride liner from the first stress status to a second stress status. A trench fill dielectric having the second stress status is deposited into the trench.

Abstract: A fabrication method for a multi-layered thin film protective layer, which is applicable on a substrate having a peripheral circuit area and a pixel cell area, is described. Metal layers and pixel cells are formed on the peripheral circuit area and the pixel cell area, respectively. A first oxide layer, a silicon nitride layer and a second oxide layer are sequentially formed on the pixel cells and the metal layers. The second oxide layer is then patterned to define a pre-determined position of a pad spacer in the pixel cell area and the peripheral circuit area. The silicon nitride layer and the first oxide layer are further defined to form a first protective layer in the peripheral circuit area and to from a pad spacer in the pixel cell area exposing the pixel cells. A second protective layer is then formed on the exposed pixel cells.

Abstract: A method for fabricating a pattern on a substrate, includes the steps of forming banks according to formation areas of the pattern on the substrate, disposing a first function liquid between the banks, disposing a second function liquid on the first function liquid, and applying predetermined treatments to the first and the second function liquids which are disposed between the banks so as to form the pattern with plural materials stacked one on the other.

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

Abstract: When exposing a sample to be oxidized 10 to ozone gas so as to form an oxide film on the surface of the sample, an area to be oxidized is heated locally. Local heating is carried out with a light source 23 for irradiating infrared light the area to be oxidized of the sample on the susceptor 21, and heating means for heating the susceptor. Moreover, when exposing the sample to be oxidized to ozone gas, ozone gas is supplied to the sample while heating the sample under a given pressure. Said pressure is adjusted at 100–44,000 Pa, for example. The flow rate of ozone gas is adjusted, preferably, so that flow of ozone gas in a furnace 20 forms laminar flow. Moreover, it is desirable to provide a light source for emitting ultraviolet light. The light source for emitting ultraviolet light is arranged to irradiate the upstream side of the susceptor 21, for example.

Abstract: The present invention provides a process for forming a silica-based coating film, characterized by heating a reaction mixture comprising a silicon compound (A) represented by Si (OR)4 and/or a silicon compound (B) represented by R1nSi (OR2)4?n (wherein n is an integer of from 1 to 3), an alcohol (C) represented by R3CH2OH and oxalic acid (D) in specific ratios, at a temperature of from 50 to 180° C. in the absence of water, to form a solution of a polysiloxane having a number average molecular weight, as calculated as polystyrene, of from 2,000 to 15,000, applying a coating fluid containing such a solution on a substrate surface, and thermally curing a coating film obtained by such coating, at a temperature of from 80 to 600° C., and such a coating film having a film thickness of from 0.5 to 5 ?m, a coating fluid to be used for such a coating film, and a process for producing such a coating fluid.

Abstract: Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.

Abstract: A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor deposition is performed to form a gate dielectric layer on the surface of the trench.

Abstract: Methods are provided for treating germanium surfaces in preparation for subsequent deposition, particularly gate dielectric deposition by atomic layer deposition (ALD). Prior to depositing, the germanium surface is treated with plasma products or thermally reacted with vapor reactants. Examples of surface treatments leave oxygen bridges, nitrogen bridges, —OH, —NH and/or —NH2 terminations that more readily adsorb ALD reactants. The surface treatments avoid deep penetration of the reactants into the germanium bulk but improve nucleation.

Abstract: An method employing atomic layer deposition (ALD) and rapid vapor deposition (RVD) techniques conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant and a high degree of surface smoothness. The method includes the following three principal operations: exposing a substrate surface to an aluminum-containing precursor gas to form a saturated layer of aluminum-containing precursor on the substrate surface; exposing the substrate surface to an oxygen-containing gas to oxidize the layer of aluminum-containing precursor; and exposing the substrate surface to a silicon-containing precursor gas to form the dielectric film. Generally an inert gas purge is employed between the introduction of reactant gases to remove byproducts and unused reactants. These operations can be repeated to deposit multiple layers of dielectric material until a desired dielectric thickness is achieved.

Abstract: A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The HfSiON layer thickness is controlled by repeating for a number of cycles a sequence including pulsing a hafnium containing precursor into a reaction chamber, pulsing an oxygen containing precursor into the reaction chamber, pulsing a silicon containing precursor into the reaction chamber, and pulsing a nitrogen containing precursor until a desired thickness is formed. Dielectric films containing atomic layer deposited HfSiON are thermodynamically stable such that the HfSiON will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.

Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.

Abstract: A method for process optimization to extend the utility of the HDP CVD gap fill technique modifies the characteristics of the HDP process (deposition and sputter components) in a dynamic mode in the course of filling a trench with dielectric material. As a result, the amount of dielectric deposited on the sidewall of the trench relative to that deposited at its bottom can be reduced and optimally minimized, thus improving the gap fill capability of the process. The dynamic modification of process characteristics provides enhanced process performance, since the optimization of these characteristics depends upon structure geometry, which is constantly changing during a gap fill operation. During the course of the gap fill operation, either at one or more discrete points or continuously, the evolution of the feature geometry is determined, either by direct measurement or in accordance with a growth model.

Abstract: In forming a high density plasma oxide film, a projection shaped like the mesa, the peaked roof, the cone or the like is formed on an element formation region. This projection gives rise to a problem of producing a polishing scar when the CMD (Chemical Mechanical Polishing) with a ceria slurry is performed. A film having a polishing rate equivalent to the one of the high density plasma oxide film is formed on the high density plasma oxide film to reinforce a projection in the shape of a triangular prism, a cone or such, and, thereafter, the polishing is carried out, using a ceria slurry. In another method, after the first CMP polishing is performed, using a silica slurry containing grains of small particle size which make no aggregation, the second CMP polishing is performed, using a ceria slurry.