With Substrate Handling During Coating (e.g., Immersion, Spinning, Etc.) Patents (Class 438/782)
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Patent number: 12237271Abstract: A module is provided that includes a substrate having a first main surface, a component mounted on the first main surface, a first sealing resin disposed so as to cover the first main surface and the component, and a shield film covering at least an upper surface of the first sealing resin. The shield film includes a protective layer exposed to the outside and a conductive layer covered by the protective layer. The color of a surface of the conductive layer closer to the protective layer is different from the color of the protective layer. Moreover, the laser absorption coefficient of a material of the protective layer is higher than the laser absorption coefficient of a material forming the surface of the conductive layer closer to the protective layer. The module includes a marking section that is not covered by the protective layer and from which the conductive layer is exposed.Type: GrantFiled: September 29, 2021Date of Patent: February 25, 2025Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tadashi Nomura, Toru Komatsu
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Patent number: 12227848Abstract: A substrate processing apparatus includes: a rotation support table capable of supporting and rotating a substrate; a chemical liquid nozzle that is arranged above an outer edge portion of the substrate that is supported by the rotation support table, and through which a chemical liquid is applied to the outer edge portion; and a solidified film forming unit that is arranged at least either on an upper side or on a lower side of the outer edge portion of the substrate that is supported by the rotation support table, and on a downstream side, in a direction of rotation of the substrate, of a position where the chemical liquid nozzle is arranged, and solidifies the chemical liquid applied to the outer edge portion, to form a solidified film that forms a part of an annular film.Type: GrantFiled: August 24, 2021Date of Patent: February 18, 2025Assignee: Kioxia CorporationInventor: Takanori Fukusumi
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Patent number: 12216407Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: GrantFiled: February 27, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsuan Chuang, Po-Sheng Lu, Shou-Wen Kuo, Cheng-Yi Huang, Chia-Hung Chu
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Patent number: 12205817Abstract: A method for depositing a silicon oxide film is provided. In the method, a silicon oxide film is deposited on a substrate by Atomic Layer Deposition with plasma while heating the substrate to a first temperature of 600° C. or higher. The silicon oxide film is annealed at a second temperature higher than the first temperature after completing the depositing the silicon oxide film.Type: GrantFiled: January 5, 2022Date of Patent: January 21, 2025Assignee: Tokyo Electron LimitedInventors: Hitoshi Kato, Toru Ishii, Yuji Seshimo, Yuichiro Sase
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Patent number: 12170199Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.Type: GrantFiled: July 31, 2023Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Je-Ming Kuo, Yen-Chun Huang, Chih-Tang Peng, Tien-I Bao
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Patent number: 12166135Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.Type: GrantFiled: July 5, 2023Date of Patent: December 10, 2024Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Kazufumi Watabe, Tomoyuki Ariyoshi, Osamu Karikome, Ryohei Takaya
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Patent number: 12154797Abstract: A substrate processing method capable of suppressing corrosion of a conductive material on a surface of a substrate by supplying a liquid having a reduced concentration of dissolved oxygen onto the substrate. The substrate processing method includes: dissolving an inert gas in a liquid at not less than a saturation solubility to replace oxygen dissolved in the liquid with the inert gas; generating bubbles of the inert gas in the liquid by depressurizing the liquid in which the inert gas is dissolved; and processing the substrate while supplying the liquid containing the bubbles to the surface of the substrate.Type: GrantFiled: August 1, 2022Date of Patent: November 26, 2024Assignee: EBARA CORPORATIONInventors: Itsuki Kobata, Yosuke Himori
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Patent number: 12105301Abstract: A method for manufacturing a multi-stage compound eye lens includes the steps of manufacturing a micropillar array using a photoetching method, then sputtering ZnO on the surface of the micropillar array, jet printing an ultraviolet curing adhesive onto gaps in the micropillar array using a micro jet printing machine, and controlling the morphology of microlens using the number of droplet dropping instances to obtain a microlens array; further respectively dissolving hexamethyl tetramine and zinc nitrate in deionized water, then pouring the hexamethyl tetramine solution into the zinc nitrate solution to obtain a mixed solution, placing the microlens array into the mixed solution, and placing is in a water bath kettle for a water bath, and finally, removing the microlens array from the mixed solution, rinsing it with deionized water, and drying same to obtain the multi-stage compound eye lens.Type: GrantFiled: August 28, 2020Date of Patent: October 1, 2024Inventors: Xuesong Mei, Wenjun Wang, Jiang Li, Aifei Pan, Bin Liu, Jianlei Cui
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Patent number: 12087623Abstract: A method of improving interfacial adhesion of a copper-glass interface in a Through Glass Via (TGV) of an electronic device includes coating an internal wall of a TGV with a curable polymer material having a viscosity less than 30 Poise. The coating is cured to form a dielectric liner having a tensile strength greater than about 8 Mpa and a dielectric loss less than about 0.002. A layer of copper may then be deposited on the dielectric liner.Type: GrantFiled: January 25, 2024Date of Patent: September 10, 2024Assignee: YIELD ENGINEERING SYSTEMS, INC.Inventors: Ramakanth Alapati, M Ziaul Karim, Christopher Lane
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Patent number: 12032293Abstract: A composition for forming an organic film contains a polymer having a partial structure shown by the following general formula (1A), and an organic solvent. The polymer is crosslinked by dehydrogenative coupling reaction involving hydrogen atoms located at the trityl position on the fluorene ring in each partial structure.Type: GrantFiled: April 7, 2020Date of Patent: July 9, 2024Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Daisuke Kori, Takayoshi Nakahara, Yasuyuki Yamamoto, Hironori Satoh, Tsutomu Ogihara
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Patent number: 12020932Abstract: The invention provides a photoresist coating method, which comprises the following steps: providing a wafer with a pattern on the wafer, placing the wafer on a spinner, injecting a photoresist on a central region of the wafer from a nozzle, and carrying out a spin coating step, the spin coating step comprises: turning on the spinner to rotate the spinner to a first rotation speed, and raising the first rotation speed to a second rotation speed, and performing a plurality of brakes during the process of maintaining the second rotation speed, so that the second rotation speed instantly drops to a third rotation speed, and then rises to the second rotation speed again.Type: GrantFiled: September 19, 2022Date of Patent: June 25, 2024Assignee: United Semiconductor (Xiamen) Co., Ltd.Inventors: Shi Teng Zhong, Ching-Shu Lo, Yuan-Chi Pai, Wen Yi Tan
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Patent number: 12011871Abstract: A method of forming a porous structure involves mixing a solvent with a curable material which disperses in the solvent such that the mixture has greater than 50% solvent content. The mixture is deposited on a substrate and viscosity of the mixture is increased. The curable material in the mixture is cured while a shape of the curable material is maintained by the solvent. After curing, the solvent is removed from the structure.Type: GrantFiled: September 23, 2022Date of Patent: June 18, 2024Assignee: Xerox CorporationInventors: Junhua Wei, Gabriel Iftime, Jessica Louis Baker Rivest, Anne Plochowietz
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Patent number: 11854795Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: GrantFiled: March 21, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 11848330Abstract: A display device is provided.Type: GrantFiled: May 15, 2020Date of Patent: December 19, 2023Assignee: Samsung Display Co., Ltd.Inventors: June Hwan Kim, Tae Young Kim, Jong Woo Park, Young Tae Choi, Hyun Cheol Hwang, Ki Ju Im
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Patent number: 11742430Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.Type: GrantFiled: June 15, 2021Date of Patent: August 29, 2023Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Kazufumi Watabe, Tomoyuki Ariyoshi, Osamu Karikome, Ryohei Takaya
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Patent number: 11678480Abstract: The present application discloses a method for fabricating the semiconductor device with the porous decoupling features. The method includes providing a substrate; integrally forming a first conductive line and a bottom contact on the substrate; integrally forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact; and forming a porous insulating layer between the first conductive line spacer and the bottom contact spacer.Type: GrantFiled: November 30, 2021Date of Patent: June 13, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11672189Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.Type: GrantFiled: March 8, 2021Date of Patent: June 6, 2023Assignee: Hefei Reliance Memory LimitedInventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
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Patent number: 11652106Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.Type: GrantFiled: May 6, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yu Chou, Yi-Ting Fu, Ting-Gang Chen, Tze-Liang Lee
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Patent number: 11592748Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: GrantFiled: November 14, 2019Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsuan Chuang, Po-Sheng Lu, Shou-Wen Kuo, Cheng-Yi Huang, Chia-Hung Chu
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Patent number: 11587888Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.Type: GrantFiled: December 13, 2019Date of Patent: February 21, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Asli Sahin, Thomas F. Houghton, Jennifer A. Oakley, Jeremy S. Alderman, Karen A. Nummy, Zhuojie Wu
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Patent number: 11566176Abstract: A semiconductor nanocrystal particle including a core including a first semiconductor nanocrystal including zinc (Zn) and sulfur (S), selenium (Se), tellurium (Te), or a combination thereof; and a shell including a second semiconductor nanocrystal disposed on at least a portion of the core, wherein the core includes a dopant of a Group 1A element, a Group 2A element, or a combination thereof, and the semiconductor nanocrystal particle exhibits a maximum peak emission in a wavelength region of about 440 nanometers (nm) to about 470 nm.Type: GrantFiled: April 17, 2020Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Hee Lee, Hyo Sook Jang, Sung Woo Kim, Jin A Kim, Tae Hyung Kim, Yuho Won, Eun Joo Jang, Yong Seok Han
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Patent number: 11515145Abstract: Methods for forming a SiBN film comprising depositing a film on a feature on a substrate. The method comprises in a first cycle, depositing a SiB layer on a substrate in a chamber using a chemical vapor deposition process, the substrate having at least one feature thereon, the at least one feature comprising an upper surface, a bottom surface and sidewalls, the SiB layer formed on the upper surface, the bottom surface and the sidewalls. In a second cycle, the SiB layer is treated with a plasma comprising a nitrogen-containing gas to form a conformal SiBN film.Type: GrantFiled: September 11, 2020Date of Patent: November 29, 2022Assignee: Applied Materials, Inc.Inventors: Chuanxi Yang, Hang Yu, Deenesh Padhi
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Patent number: 11387099Abstract: A spin coating method includes dispensing a coating material including a nonvolatile film material and a volatile solvent over a substrate, and spin coating the coating material over the substrate by spinning the substrate while applying ultrasound waves to the coating material to reduce a viscosity of the coating material during the spin coating.Type: GrantFiled: November 18, 2020Date of Patent: July 12, 2022Assignee: SANDISK TECHNOLOGIES LLCInventor: Yutaka Ishiguro
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Patent number: 11201122Abstract: A trench is formed through a plurality of layers that are disposed over a first substrate. A first deposition process is performed to at least partially fill the trench with a first dielectric layer. The first dielectric layer delivers a tensile stress. A second deposition process is performed to form a second dielectric layer over the first dielectric layer. A third deposition process is performed to form a third dielectric layer over the second dielectric layer. The third dielectric layer delivers a first compressive stress.Type: GrantFiled: February 7, 2019Date of Patent: December 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsu Yen, Yu Chuan Hsu, Chen-Hui Yang
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Patent number: 11099139Abstract: A photolithography method includes dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer; capturing an image of the first liquid on the first target layer; patterning the first target layer after capturing the image of the first liquid; comparing the captured image of the first liquid to a first reference image to generate a first comparison result; responsive to the first comparison result, positioning the nozzle and a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer; dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; and patterning the second target layer after dispensing the second liquid.Type: GrantFiled: June 1, 2020Date of Patent: August 24, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Hung Liao, Wei Chang Cheng
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Patent number: 11101388Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane, a second plane, and a through hole penetrating from the first plane to the second plane; an insulating layer on a side of the second plane of the semiconductor layer; a first conductive layer in the insulating layer; a silicon oxide layer on a side of the first plane and in the through hole; a silicon nitride layer provided on the side of the first plane and in the through hole, the silicon oxide layer being interposed between the silicon nitride layer and the semiconductor layer; and a second conductive layer on the side of the first plane and in the through hole, the silicon oxide layer and the silicon nitride layer being interposed between the second conductive layer and the semiconductor layer, and the second conductive layer electrically connected to the first conductive layer.Type: GrantFiled: September 16, 2019Date of Patent: August 24, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Hirofumi Baba
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Patent number: 10985010Abstract: A composition and method for using the composition in the fabrication of an electronic device are disclosed. Compounds, compositions and methods for depositing a high quality silicon nitride or carbon doped silicon nitride.Type: GrantFiled: August 27, 2019Date of Patent: April 20, 2021Assignee: Versum Materials US, LLCInventors: Haripin Chandra, Xinjian Lei, Moo-Sung Kim
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Patent number: 10923351Abstract: A coating method of coating a substrate with a chemical includes a solvent supplying step and a chemical supplying step. In the solvent supplying step, a solvent is supplied to the substrate. After the solvent supplying step, the chemical is supplied to the substrate in the chemical supplying step. The solvent supplying step includes a first step. The first step causes the substrate to rotate at a first rotation speed, causes a solvent nozzle to move between a central position above a center portion of the substrate and a peripheral position above a peripheral portion of the substrate, and causes the solvent nozzle to dispense the solvent.Type: GrantFiled: February 10, 2020Date of Patent: February 16, 2021Inventors: Shogo Yoshida, Hiroyuki Ogura, Ryuichi Yoshida
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Patent number: 10854726Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.Type: GrantFiled: November 8, 2019Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 10811288Abstract: A system for retaining a spin-coating fluid when forming a thin film includes a rotatable chuck; a substrate on the rotatable chuck, the substrate having an interior area and an outer perimeter edge; and a fluid retention wall on the outer perimeter edge of the substrate, the fluid retention wall being configured to retain a spin-coating fluid deposited on the interior area of the substrate during rotation of the rotatable chuck.Type: GrantFiled: August 30, 2019Date of Patent: October 20, 2020Assignee: Carbon, Inc.Inventors: Bob E. Feller, James M. Ian Bennett
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Patent number: 10714331Abstract: A method for forming a thermally stable spacer layer is disclosed. The method includes first disposing a substrate in an internal volume of a processing chamber. The substrate has a film formed thereon, the film including silicon, carbon, nitrogen, and hydrogen. Next, high pressure steam is introduced into the processing chamber. The film is exposed to the high pressure steam to convert the film to reacted film, the reacted film including silicon, carbon, oxygen, and hydrogen.Type: GrantFiled: March 15, 2019Date of Patent: July 14, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Mihaela Balseanu, Srinivas D. Nemani, Mei-Yee Shek, Ellie Y. Yieh
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Patent number: 10579478Abstract: Techniques herein make and use a pluggable database archive file (AF). In an embodiment, a source database server of a source container database (SCD) inserts contents into an AF from a source pluggable database (SPD). The contents include data files from the SPD, a listing of the data files, rollback scripts, and a list of patches applied to the SPD. A target database server (TDS) of a target container database (TCD) creates a target pluggable database (TPD) based on the AF. If a patch on the list of patches does not exist in the TCD, the TDS executes the rollback scripts to adjust the TPD. In an embodiment, the TDS receives a request to access a block of a particular data file. The TDS detects, based on the listing of the data files, a position of the block within the AF. The TDS retrieves the block based on the position.Type: GrantFiled: August 23, 2016Date of Patent: March 3, 2020Assignee: Oracle International CorporationInventors: Prashanth Shanthaveerappa, Giridhar Ravipati, Margaret Susairaj, Kumar Rajamani
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Patent number: 10438827Abstract: A system for retaining a spin-coating fluid when forming a thin film includes a rotatable chuck; a substrate on the rotatable chuck, the substrate having an interior area and an outer perimeter edge; and a fluid retention wall on the outer perimeter edge of the substrate, the fluid retention wall being configured to retain a spin-coating fluid deposited on the interior area of the substrate during rotation of the rotatable chuck.Type: GrantFiled: June 30, 2017Date of Patent: October 8, 2019Assignee: Carbon, Inc.Inventors: Bob E. Feller, James M. Ian Bennett
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Patent number: 10424486Abstract: A manufacturing process of an elemental chip comprises steps of preparing a substrate held on the holding tape, the substrate including first and second sides opposite each other and the second side thereof being held on the holding tape, and the substrate further including a plurality of element regions and a plurality of segmentation regions defining each of the element regions; spraying a resist solution to form droplets of the resist solution, the resist solution containing a resist constituent and a solvent; forming a resist layer by vaporizing the solvent from the droplets and depositing the resist constituent on the first side of the substrate that is held on the holding tape; patterning the resist layer to expose the first side of the substrate in the segmentation regions; and plasma-etching the first side of the substrate exposed in the segmentation regions thereof.Type: GrantFiled: August 22, 2017Date of Patent: September 24, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Noriyuki Matsubara
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Patent number: 10229828Abstract: In a method of treating a semiconductor substrate, a plurality of active regions and a plurality of trench isolation regions are formed by selectively etching the semiconductor substrate. The semiconductor substrate is washed by providing deionized water to the semiconductor substrate. A silicon-based solution is provided to the semiconductor substrate by replacing the deionized water disposed on the semiconductor substrate with the silicon-based solution. A silicon oxide material is formed from the silicon-based solution by performing a heat treatment on the silicon-based solution and the semiconductor substrate. The silicon oxide material fills the trench isolation regions.Type: GrantFiled: May 2, 2017Date of Patent: March 12, 2019Assignee: SK HYNIX INC.Inventors: Yong Soo Choi, Ho Jin Jeong
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Patent number: 10153252Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.Type: GrantFiled: September 20, 2016Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventor: Ming-Tse Lin
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Patent number: 10120285Abstract: A developing apparatus including a horizontal substrate holder, a rotating mechanism to rotate the substrate holder, a developer nozzle to supply a developer onto a part of the substrate to form a liquid puddle, a moving mechanism to move the developer nozzle in a radial direction of the rotating substrate, a contact part that moves with the developer nozzle and has a surface opposed to the substrate, which is smaller than the surface of the substrate, and a control unit to output a control signal such that a supply position of the developer on the substrate is moved in the radial direction of the substrate so that the liquid puddle is spread out on a whole surface of the substrate while the contact part is in contact with the liquid puddle.Type: GrantFiled: December 9, 2016Date of Patent: November 6, 2018Assignee: Tokyo Electron LimitedInventors: Kousuke Yoshihara, Hideharu Kyouda, Koshi Muta, Taro Yamamoto, Yasushi Takiguchi, Masahiro Fukuda
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Patent number: 10023956Abstract: Methods and apparatuses for conditioning chambers using a two-stage process involving a low bias and a high bias stage are provided. Methods also involve clamping a protective electrostatic chuck cover to a pedestal by applying a bias to the electrostatic chuck during the high bias stage while cooling the protective electrostatic chuck cover, such as by flowing helium to the backside of the cover.Type: GrantFiled: April 9, 2015Date of Patent: July 17, 2018Assignee: Lam Research CorporationInventors: Lin Cui, Jason Daejin Park
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Patent number: 9929008Abstract: A substrate processing method is provided. In the method, a plurality of substrates is placed on a plurality of substrate holding areas provided in a surface of a turntable at predetermined intervals in a circumferential direction, the turntable being provided in a processing chamber. Next, the turntable on which the plurality of substrates is placed is rotated. Then, a fluid is supplied to the surface of the turntable while rotating the turntable. Here, the fluid is supplied to an area between the plurality of substrate holding areas in response to an operation of changing a flow rate of the fluid.Type: GrantFiled: October 7, 2015Date of Patent: March 27, 2018Assignee: Tokyo Electron LimitedInventors: Yu Wamura, Fumiaki Hayase, Masahiko Kaminishi, Yu Sasaki, Kosuke Takahashi
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Patent number: 9818604Abstract: Provided is a method of depositing an insulation layer on a trench in a substrate, in which the trench having an aspect ratio of 5:1 or more is formed, including: an insulation layer deposition step of performing an adsorption step of adsorbing silicon to the substrate by injecting a silicon precursor into the inside of a chamber into which the substrate is loaded, a first purge step of removing the unreacted silicon precursor and reaction byproducts from the inside of the chamber, a reaction step of forming the adsorbed silicon as an insulation layer including silicon by supplying a first reaction source to the inside of the chamber, and a second purge step of removing the unreacted first reaction source and reaction byproducts from the inside of the chamber; and a densification step of forming a plasma atmosphere in the inside of the chamber by applying an radio frequency (RF) power and densifying the insulation layer including silicon by using the plasma atmosphere, wherein a frequency of the RF power is iType: GrantFiled: June 16, 2015Date of Patent: November 14, 2017Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai-Won Kim, Chang-Hun Shin, Seok-Yun Kim, Choon-Sik Jeong
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Patent number: 9793118Abstract: Disclosed are a method and an apparatus for applying a liquid onto a substrate. The method for treating a substrate, the method includes: a liquid supplying step of supplying a treatment liquid for forming a liquid film on the substrate while rotating the substrate; and a liquid diffusing step of diffusing the treatment liquid discharged to the substrate by rotating the substrate, after the liquid supplying step. The liquid diffusing step includes: a primary diffusion step of rotating the substrate at a first diffusion speed; and a secondary diffusion step of rotating the substrate at a second diffusion speed, after the primary diffusion step. The second diffusion speed is higher than the first diffusion speed. Accordingly, the treatment liquid can be applied to the substrate again by performing the secondary diffusion step, making it possible to adjust the thickness of a photosensitive film.Type: GrantFiled: March 23, 2016Date of Patent: October 17, 2017Assignee: Semes Co., Ltd.Inventors: Eun Saem Ahn, Choongki Min, Jung Yul Lee, Min Jung Park
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Patent number: 9738787Abstract: Disclosed is a composition for a silica-based insulation layer including hydrogenated polysilazane or hydrogenated polysiloxzane, wherein a concentration of a cyclic compound having a weight average molecular weight of less than 400 is less than or equal to 1,200 ppm. The composition for a silica-based insulation layer may reduce a thickness distribution during formation of a silica-based insulation layer, and thereby film defects after chemical mechanical polishing (CMP) during a semiconductor manufacturing process may be reduced.Type: GrantFiled: August 16, 2013Date of Patent: August 22, 2017Assignee: CHEIL INDUSTRY, INC.Inventors: Hui-Chan Yun, Taek-Soo Kwak, Mi-Young Kim, Sang-Hak Lim, Kwen-Woo Han, Go-Un Kim, Bong-Hwan Kim, Sang-Kyun Kim, Yoong-Hee Na, Eun-Su Park, Jin-Hee Bae, Hyun-Ji Song, Han-Song Lee, Seung-Hee Hong
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Patent number: 9536771Abstract: The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.Type: GrantFiled: April 11, 2013Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chang Chen, Po-Hsiung Leu, Ding-I Liu
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Patent number: 9484393Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises a base substrate and a thin-film transistor (TFT) unit, a color filter and a planarization protective layer disposed on the base substrate. The planarization protective layer is electrically connected with a drain electrode of the TFT unit and is conductive. The array substrate has the advantages of simplifying the layer structures of the array substrate, reducing the manufacturing difficulty of the array substrate, and improving the production yield of the array substrate.Type: GrantFiled: May 26, 2014Date of Patent: November 1, 2016Assignee: BOE Technology Group Co., Ltd.Inventors: Yonglian Qi, Shi Shu, Ming Zhao
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Patent number: 9278373Abstract: In one embodiment, a spin coating apparatus includes a coating liquid feeding module to drop a coating liquid onto a substrate, and a motor to rotate the substrate. The module drops a first drop amount of the coating liquid onto the substrate at a first discharge rate, while the motor rotates the substrate at a first number of rotations. The module drops a second drop amount of the coating liquid onto the substrate at a second discharge rate larger than the first discharge rate, while the motor rotates the substrate at a second number of rotations smaller than the first number of rotations, after the first drop amount of the coating liquid is dropped. The module discharges the coating liquid onto the substrate at a third discharge rate smaller than the second discharge rate, after the coating liquid is discharged onto the substrate at the second discharge rate.Type: GrantFiled: September 4, 2013Date of Patent: March 8, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Keisuke Nakazawa
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Patent number: 9269581Abstract: A method of producing a solar cell, including: a first coating step in which a pre-wet composition is spin-coated on a surface of a semiconductor substrate; a second coating step in which a diffusing material including a solvent and a diffusing agent containing a first impurity element is spin-coated on the surface where the pre-wet composition has been spin-coated, so as to form a coating film of the diffusing agent; and a first impurity diffusion layer forming step in which the semiconductor substrate having the coating film formed thereon is heated, so as to form a first impurity diffusion layer in which the impurity element contained in the diffusing agent is diffused.Type: GrantFiled: October 23, 2014Date of Patent: February 23, 2016Assignee: PVG SOLUTIONS INC.Inventors: Seiji Ohishi, Katsuya Tanitsu, Shinji Goda, Takayuki Ogino, Futoshi Kato, Ayumu Imai, Yasuyuki Kano
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Patent number: 9057639Abstract: Spin coating a mixture of graphene oxide platelets, water, and an organic solvent by placing a drop of the mixture on a spinning substrate while blowing a drying gas onto the substrate and allowing the water and the organic solvent on the substrate to evaporate; and repeating the spin coating one or more times to form a graphene oxide film in contact with the substrate. An about 1-100 nm thick film of overlapping platelets of reduced graphene oxide.Type: GrantFiled: April 25, 2012Date of Patent: June 16, 2015Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Jeremy T. Robinson, Eric S Snow
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Patent number: 9028915Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.Type: GrantFiled: September 4, 2012Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wei Chang, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
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Patent number: 9023693Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.Type: GrantFiled: December 23, 2013Date of Patent: May 5, 2015Assignee: Industrial Technology Research InstituteInventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
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Patent number: 8987147Abstract: A method of depositing a film on substrates using an apparatus including a turntable mounting substrates, first and second process areas above the upper surface of the turntable provided with gas supplying portions, a separation gas supplying portion between the first and second process areas, and a separation area including depositing a first oxide film by rotating the turntable first turns while supplying a first reaction gas, the oxidation gas from the second gas supplying portion, and the separation gas; rotating at least one turn while supplying the separation gas from the first gas supplying portion and the separation gas supplying portion, and the oxidation gas from the second gas supplying portion; and rotating at least second turns to deposit a second oxide film while supplying a second reaction gas from the first gas supplying portion, the oxidation gas from the second gas supplying portion, and the separation gas.Type: GrantFiled: December 17, 2013Date of Patent: March 24, 2015Assignee: Tokyo Electron LimitedInventors: Hiroaki Ikegawa, Masahiko Kaminishi, Kosuke Takahashi, Masato Koakutsu, Jun Ogawa