With Substrate Handling During Coating (e.g., Immersion, Spinning, Etc.) Patents (Class 438/782)
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Patent number: 8053376Abstract: In a method of making a polymer structure on a substrate a layer of a first polymer, having a horizontal top surface, is applied to a surface of the substrate. An area of the top surface of the polymer is manipulated to create an uneven feature that is plasma etched to remove a first portion from the layer of the first polymer thereby leaving the polymer structure extending therefrom. A light emitting structure includes a conductive substrate from which an elongated nanostructure of a first polymer extends. A second polymer coating is disposed about the nanostructure and includes a second polymer, which includes a material such that a band gap exists between the second polymer coating and the elongated nanostructure. A conductive material coats the second polymer coating. The light emitting structure emits light when a voltage is applied between the conductive substrate and the conductive coating.Type: GrantFiled: June 26, 2009Date of Patent: November 8, 2011Assignee: Georgia Tech Research CorporationInventors: Zhong L. Wang, Xudong Wang, Jenny R. Morber, Jin Liu
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Patent number: 8048725Abstract: A method of forming a pattern and a method of producing an electronic element are characterized by including a first step of forming an electrically conductive film (D) by applying a liquid composition onto a first plate (10), and heating the first plate (10); a second step of forming an electrically conductive pattern (D?) on the first plate (10) by pressing a second plate (20) having a projection-and-recess pattern on a surface side thereof onto a surface side of the first plate (10), on which the electrically conductive film (D) is formed, to transfer an unwanted pattern of the electrically conductive film (D) to top faces of projections (20a) of the second plate (20), thereby removing the unwanted pattern; and a third step of transferring the electrically conductive pattern (D?) to a surface of a transfer-receiving substrate (30) by pressing the surface side of the first plate (10), on which the electrically conductive pattern (D?) is formed, onto the surface of the transfer-receiving substrate (30), wherType: GrantFiled: December 21, 2007Date of Patent: November 1, 2011Assignee: Sony CorporationInventors: Toshio Fukuda, Akihiro Nomoto
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Publication number: 20110250765Abstract: A coating treatment method includes: a first step of discharging a coating solution from a nozzle to a central portion of a substrate while acceleratingly rotating the substrate, to apply the coating solution over the substrate; a second step of then decelerating the rotation of the substrate and continuously rotating the substrate; and a third step of then accelerating the rotation of the substrate to dry the coating solution on the substrate. In the first step, the acceleration of the rotation of the substrate is changed in the order of a first acceleration, a second acceleration higher than the first acceleration, and a third acceleration lower than the second acceleration to acceleratingly rotate the substrate at all times.Type: ApplicationFiled: March 23, 2011Publication date: October 13, 2011Applicant: Tokyo Electron LimitedInventors: Kousuke YOSHIHARA, Katsunori ICHINO
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Patent number: 8012886Abstract: A method is provided for treating a leadframe comprising copper or copper alloy to enhance adhesion of molding compound to it. The leadframe is oxidized in an oxidation treatment bath to form copper oxide on the surface of the leadframe. It is then dipped in a complexing or chelating agent to enhance the purity of the copper oxide formed. Thereafter, the leadframe is cleaned with an acid to remove any contaminants remaining on the leadframe.Type: GrantFiled: March 7, 2007Date of Patent: September 6, 2011Assignee: ASM Assembly Materials LtdInventors: Yiu Fai Kwan, Tat Chi Chan, Wai Chan, Chi Chung Lee
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Publication number: 20110204490Abstract: According one embodiment, a film forming apparatus includes a stage, a coating section, a vapor supply section, a blower section, and a controller. On the stage, an coating target is placed. The coating section applies a material to a predetermined region on the coating target placed on the stage to form a coating film. The vapor supply section generates solvent vapor capable of dissolving the coating film. The blower section blows the solvent vapor generated by the vapor supply section onto the coating film on the coating target placed on the stage. The controller controls an amount of the solvent vapor to be blown by the blower section so that: the coating film is dissolved; viscosity in a part of the coating film on a surface layer side is lower than that in a part thereof on the coating target side; and the viscosity in the part on the surface layer side and the viscosity of the coating target side take such values that prevent the coating film on the coating target from spreading.Type: ApplicationFiled: March 15, 2011Publication date: August 25, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuyoshi SATO, Hiroyasu Kondo, Naoaki Sakurai, Katsuyuki Soeda, Kenichi Ooshiro, Shuichi Kimura
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Patent number: 8003547Abstract: A substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of confirming an operation of a liquid flowrate control device are provided. The substrate processing apparatus comprises: a process chamber accommodating a substrate; a liquid source supply system supplying a liquid source into the process chamber; a solvent supply system supplying a solvent having a vapor pressure greater than that of the liquid source into the process chamber; a liquid flowrate control device controlling flowrates of the liquid source and the solvent; and a controller controlling the liquid source supply system, the solvent supply system, and the liquid flowrate control device so that the solvent is supplied into the liquid flowrate control device than the solvent supply system to confirm an operation of the liquid flowrate control device before the liquid source supply system supplies the liquid source into the process chamber.Type: GrantFiled: August 5, 2010Date of Patent: August 23, 2011Assignee: Hitachi Kokusai Electric, Inc.Inventor: Masanori Sakai
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Patent number: 8003522Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.Type: GrantFiled: December 3, 2008Date of Patent: August 23, 2011Assignee: Fairchild Semiconductor CorporationInventors: Hui Chen, Ihsiu Ho, Stacy W. Hall, Briant Harward, Hossein Paravi
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Patent number: 7977254Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.Type: GrantFiled: June 27, 2007Date of Patent: July 12, 2011Assignee: Tekcore Co., Ltd.Inventors: Lung-Han Peng, Han-Ming Wu, Jing-Yi Lin
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Publication number: 20110143553Abstract: Methods and systems for handling a substrate through processes including an integrated electroless deposition process includes processing a surface of the substrate in an electroless deposition module to deposit a layer over conductive features of the substrate using a deposition fluid. The surface of the substrate is then rinsed in the electroless deposition module with a rinsing fluid. The rinsing is controlled to prevent de-wetting of the surface so that a transfer film defined from the rinsing fluid remains coated over the surface of the substrate. The substrate is removed from the electroless deposition module while maintaining the transfer film over the surface of the substrate. The transfer film over the surface of the substrate prevents drying of the surface of the substrate so that the removing is wet. The substrate, once removed from the electroless deposition module, is moved into a post-deposition module while maintaining the transfer film over the surface of the substrate.Type: ApplicationFiled: December 10, 2010Publication date: June 16, 2011Applicant: Lam Research CorporationInventors: Yaxin Wang, Shijian Li, Fritz Redeker, John Parks, Artur Kolics, Hyungsuk Alexander Yoon, Tarek Suwwan de Felipe, Mikhail Korolik
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Patent number: 7960291Abstract: The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks.Type: GrantFiled: August 28, 2008Date of Patent: June 14, 2011Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 7960296Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.Type: GrantFiled: November 12, 2008Date of Patent: June 14, 2011Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
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Patent number: 7923382Abstract: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits.Type: GrantFiled: February 10, 2009Date of Patent: April 12, 2011Assignee: ASM International N.V.Inventors: Hannu Huotari, Suvi Haukka
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Patent number: 7923383Abstract: This invention relates to a method of treating a semiconductor wafer and in particular, but not exclusively, to planarisation. The method consists of depositing a liquid short-chain polymer formed from a silicon containing bas or vapour. Subsequently water and OH are removed and the layer is stabilised.Type: GrantFiled: March 28, 2003Date of Patent: April 12, 2011Assignee: Tokyo Electron LimitedInventors: Knut Beekmann, Guy Patrick Tucker
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Patent number: 7919359Abstract: A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.Type: GrantFiled: October 17, 2007Date of Patent: April 5, 2011Assignee: Panasonic CorporationInventors: Junichi Kimura, Hideki Niimi, Yuji Fuwa, Tsuyoshi Sakaue
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Patent number: 7915058Abstract: The present invention provides a method for manufacturing a substrate having a pattern that is capable of controlling the distance between adjacent film patterns, and also provides a method for manufacturing a substrate, particularly, having a pattern with a narrow width and a thickness that is capable of controlling the width between the film patterns. The present invention provides a method for manufacturing a substrate having a conductive film that serves as an antenna with a little variation in inductance and has a large electromotive force, and provides a method for manufacturing a semiconductor device with high yield. After forming a film in which silicon and oxygen are combined and an inactive group is combined with the silicon over a substrate, an insulating film, or a conductive film, a composition is printed by the printing method thereover, and is baked to form a film pattern.Type: GrantFiled: January 19, 2006Date of Patent: March 29, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoyuki Aoki, Koji Dairiki
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Patent number: 7906441Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.Type: GrantFiled: October 31, 2007Date of Patent: March 15, 2011Assignee: Texas Instruments IncorporatedInventors: Malcolm J. Bevan, Haowen Bu, Hiroaki Niimi, Husam N. Alshareef
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Publication number: 20110059620Abstract: A protective film forming method for forming a protective film of resin on the front side of a wafer to be laser-processed.Type: ApplicationFiled: September 1, 2010Publication date: March 10, 2011Applicant: DISCO CORPORATIONInventor: Nobuyasu Kitahara
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Patent number: 7892878Abstract: Provided are a method of manufacturing an organic light emitting device. The method includes forming an electron injection layer by vacuum co-depositing an organic semiconductor material having an electron mobility of about 1×10?6 cm2/V·s or more in an electric field of about 1×106 V/m and a metal azide.Type: GrantFiled: June 9, 2009Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-woo Lee, Tae-yong Noh, Haa-jin Yang, Byoung-ki Choi, Myeong-suk Kim, Dong-woo Shin
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Patent number: 7893538Abstract: An insulating-film-forming composition for a semiconductor device comprising an organic silica sol with a carbon atom content of 11 to 17 atom % and an organic solvent is disclosed. The organic silica sol comprises a hydrolysis-condensation product P1 and a hydrolysis-condensation product P2. The hydrolysis-condensation product P1 is obtained by hydrolyzing and condensing (A) a silane monomer comprising a hydrolyzable group and (B) a polycarbosilane comprising a hydrolyzable group in the presence of (C) a basic catalyst, and the hydrolysis-condensation product P2 is obtained by hydrolyzing and condensing (D) a silane monomer comprising a hydrolyzable group.Type: GrantFiled: January 31, 2007Date of Patent: February 22, 2011Assignee: JSR CorporationInventors: Hisashi Nakagawa, Tatsuya Yamanaka, Masahiro Akiyama, Terukazu Kokubo, Youhei Nobe
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Publication number: 20110034038Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).Type: ApplicationFiled: June 29, 2010Publication date: February 10, 2011Applicant: NANOSYS, Inc.Inventors: Jian Chen, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
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Patent number: 7884033Abstract: An apparatus for processing microelectronic topographies, a method of use of such an apparatus, and a method for passivating hardware of microelectronic processing chambers are provided. The apparatus includes a substrate holder configured to support a microelectronic topography and a rotatable case with sidewalls arranged on opposing sides of the substrate holder. The method of using such an apparatus includes positioning a microelectronic topography upon a substrate holder of a processing chamber, exposing the microelectronic topography to a fluid within the processing chamber, and rotating a case of the processing chamber. The rotation is sufficient to affect movement of the fluid relative to the surface of the microelectronic topography. A method for passivating hardware of a microelectronic processing chamber includes exposing the hardware to an organic compound and subsequently exposing the hardware to an agent configured to form polar bonds with the organic compound.Type: GrantFiled: November 11, 2009Date of Patent: February 8, 2011Assignee: Lam ResearchInventor: Igor C. Ivanov
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Publication number: 20110014796Abstract: This invention relates to a dipping solution used in a process for producing a siliceous film. The present invention provides a dipping solution and a siliceous film-production process employing the solution. The dipping solution enables to form a homogeneous siliceous film even in concave portions of a substrate having concave portions and convex portions. The substrate is coated with a polysilazane composition, and then dipped in the solution before fire. The dipping solution comprises hydrogen peroxide, a foam-deposit inhibitor, and a solvent.Type: ApplicationFiled: March 3, 2009Publication date: January 20, 2011Inventor: Masanobu Hayashi
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Patent number: 7867559Abstract: This invention provides a photoresist coating liquid supplying apparatus and a photoresist coating liquid supplying method, for supplying a photoresist coating liquid having a low particle content to a photoresist coating apparatus, and a photoresist coating apparatus using such a photoresist coating liquid supplying apparatus, which can realize coating without causing significant defects in a cost-effective manner. The photoresist coating liquid supplying apparatus comprises a buffer vessel for a photoresist coating liquid, a circulation filtering apparatus for drawing a part of the coating liquid from the buffer vessel, filtering the coating liquid, and then returning the filtered coating liquid to the buffer vessel, and a pipe for supplying the coating liquid from the buffer vessel or the circulation apparatus to a coating apparatus. The photoresist coating liquid supplying method uses the photoresist coating liquid supplying apparatus.Type: GrantFiled: November 25, 2005Date of Patent: January 11, 2011Assignee: AZ Electronic Materials USA Corp.Inventors: Katsuto Taniguchi, Kazuhiro Kojima, Atsuko Noya
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Patent number: 7855121Abstract: Provided are a method of forming an organic semiconductor thin film and a method of manufacturing a semiconductor device using the. According to example embodiments, a method of forming an organic semiconductor thin film at least may include exposing a lower substrate coated with an organic semiconductor solution using a method of generating a shearing stress to the portion of the lower substrate coated with the organic semiconductor solution. A guide structure may be formed adjacent to the organic semiconductor solution.Type: GrantFiled: March 27, 2009Date of Patent: December 21, 2010Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Laland Stanford Junior UniversityInventors: Do Hwan Kim, Sangyoon Lee, Hector Alejandro Becerril Garcia, Mark Roberts, Zhenan Bao, Zihong Liu
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Patent number: 7816276Abstract: In the present invention, a plurality of heat treatment plates are provided side by side in a linear form on a base of a heat treatment apparatus in a coating and developing treatment system. In the heat treatment apparatus, three transfer member groups are provided which transfer a substrate in zones between adjacent heat treatment plates. At the time when performing a pre-baking treatment in the heat treatment apparatus, the substrate is transferred in order to the heat treatment plates at the same temperature, whereby the heat treatment is dividedly performed on the heat treatment plates. According to the present invention, substrates are subjected to heat treatment along the same route, so that the thermal histories are made uniform among the substrates.Type: GrantFiled: January 26, 2007Date of Patent: October 19, 2010Assignee: Tokyo Electron LimitedInventors: Takahisa Otsuka, Tsuyoshi Shibata
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Patent number: 7816280Abstract: A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.Type: GrantFiled: January 15, 2009Date of Patent: October 19, 2010Assignee: NEC Electronics CorporationInventor: Tatsuya Usami
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Patent number: 7816168Abstract: A method for forming a color filter is provided. A substrate having a passivation layer thereon is provided. The passivation layer has at least one trench therein within a peripheral region of the substrate. A first color filter layer is formed over the passivation layer to fill the trench by performing a first spin-on coating process with a first spin rate. Thereafter, the first color filter layer is patterned so as to form a plurality of first color filter blocks in a display region of the substrate and expose a portion of the passivation layer. A second color filter layer is formed over the passivation layer by performing a second spin-on coating process with a second spin rate, which is larger than the first spin rate. Next, the second color filter layer is patterned to form a plurality of second color filter blocks between the first color filter blocks respectively.Type: GrantFiled: June 13, 2008Date of Patent: October 19, 2010Assignee: United Microelectronics Corp.Inventor: Hsin-Ping Wu
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Patent number: 7811946Abstract: The present invention provides a semiconductor device having a coating film of a predetermined thickness provided along the circumference of a semiconductor light emitting element, and provide a method for easily manufacturing the semiconductor device. A semiconductor light emitting element 2 that emits blue light is mounted face down on the top face of a pedestal 1, and a coating film 3 containing a YAG fluorescent material 6 that emits yellow light is placed so as to cover the top face and side face of the semiconductor light emitting element 2 and the top face of the pedestal 1. With the semiconductor light emitting element 2 and other elements placed between a first film 8 and a second film 9, the films are laminated in vacuum, thereby to fasten the coating film 3 onto the semiconductor light emitting element 2.Type: GrantFiled: March 27, 2009Date of Patent: October 12, 2010Assignee: Nichia CorporationInventors: Kunihiro Izuno, Shinsuke Sofue
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Patent number: 7803688Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.Type: GrantFiled: March 2, 2009Date of Patent: September 28, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
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Patent number: 7803720Abstract: A coating system and method of coating semiconductor wafers is disclosed that is able to maintain a wet condition on the outer portion of the semiconductor wafer to provide ease of spreading for a photo-resist or anti-reflective coating (ARC) that is being dispensed. The system can include a plurality of nozzles on a movable arm. A first nozzle dispenses a pre-wet solvent onto the semiconductor wafer. A second nozzle then dispenses the photo-resist or ARC coating onto the semiconductor wafer. A third nozzle dispenses additional pre-wet solvent onto the outer edge of the semiconductor wafer as the photo-resist or ARC coating is being dispensed. The nozzles dispense solutions onto the semiconductor wafer as it rotates. The system produces semiconductor wafers with few coating defects and uses less photo-resist or ARC coating.Type: GrantFiled: January 25, 2008Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Seiji Nakagawa
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Patent number: 7790626Abstract: The present invention relates to a technology for depositing a thin metal film by using a plasma sputtering technique on a top surface of a target object, e.g., a semiconductor wafer or the like, and on a surface of a recess opened at the top surface. The film deposition method is characterized in that a film deposition process to deposit a metal film on a sidewall of the recess by generating metal ions by way of making a metal target sputter with a plasma generated from a discharge gas in the processing container and by applying to the mounting table a bias power to cause a metal film deposition based on a metal ion attraction and a sputter etching based on the plasma generated from the discharge gas simultaneously on the top surface of the target object.Type: GrantFiled: October 18, 2005Date of Patent: September 7, 2010Assignee: Tokyo Electron LimitedInventors: Taro Ikeda, Kenji Suzuki, Tatsuo Hatano, Yasushi Mizusawa
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Patent number: 7785998Abstract: Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands, and the first coordination complexes are dispersed within a non-polar solvent. While the first coordination complexes are within the non-polar solvent, the ligands are reacted with one or more reactants to convert the first coordination complexes into second coordination complexes that contain hydrophilic ligands. The second coordination complexes are then extracted from the non-polar solvent into water, to form a mixture of the second coordination complexes and the water. In some embodiments, the mixture may be dispersed across a semiconductor substrate to form a uniform distribution of the nanoparticles across the substrate. In some embodiments, the nanoparticles may then be incorporated into flash memory devices as charge-trapping centers.Type: GrantFiled: February 21, 2008Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventor: Dan Millward
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Publication number: 20100210106Abstract: A method for fabricating a semiconductor includes the steps of forming a porous insulation film and wires on a substrate, the wires embedded in the porous insulation film having a portion adjacent to the wires and a remote portion spaced apart from the wires; and applying an energy beam to the remote portion to change the structure of the porous insulation film such that an Young's modulus of the porous insulation film increased so as to substantially reinforce the strength of the porous insulation film.Type: ApplicationFiled: April 28, 2010Publication date: August 19, 2010Applicant: FUJITSU LIMITEDInventors: Shoichi SUDA, Shino TOKUYO, Yoshihiro NAKATA, Azuma MATSUURA
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Patent number: 7776703Abstract: Reduction of damage to a semiconductor device due to a marking process while inhibiting deterioration of a mark can not be achieved in conventional processes for manufacturing semiconductor devices. A process for manufacturing the semiconductor device 100 involves irradiating the marking film 21 with an energy beam through the transparent protective film 31 after the protective film 31 is formed, and such irradiation causes a chemical modification of the material of the marking film 21 to create the marks. According to the above-described process for manufacturing the semiconductor device 100, the region for the marking or the upper surface of the marking film 21 is sheathed by the protective film 31, so that a damage to the semiconductor chip 11 due to the generations of dust, exothermic heat, gas, stress or the like during the marking operation can be reduced. This allows achieving the process for manufacturing the semiconductor device 100 that provides a manufacture of better quality of the marks.Type: GrantFiled: November 25, 2008Date of Patent: August 17, 2010Assignee: NEC Electronics CorporationInventor: Kazuhiro Fukuchi
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Patent number: 7776623Abstract: A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, the method includes depositing a cap layer on a magnetic tunnel junction (MTJ) structure, depositing a first spin-on material layer over the cap layer, and etching the first spin-on material layer and at least a portion of the cap layer.Type: GrantFiled: June 30, 2008Date of Patent: August 17, 2010Assignee: QUALCOMM IncorporatedInventors: Xia Li, Seung H. Kang, Xiaochun Zhu
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Patent number: 7763309Abstract: A method for controlling a chemical solution applying apparatus is disclosed. The method includes setting at least two dummy dispense rates for dummy dispensation which is periodically carried out by the chemical solution applying apparatus, and switching the dummy dispense rates so that the amount of chemical solution dispensed during a first predetermined period is kept over a predetermined value.Type: GrantFiled: October 5, 2006Date of Patent: July 27, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Hirokazu Kato
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Patent number: 7754619Abstract: A method of forming a liquid coating on a substrate that reduces the amount of consumption of the coating liquid and achieves a more even distribution of the thickness of the liquid coating film. The method may include supplying a solvent to a surface of a substrate, starting a supply of a coating liquid to the surface of the substrate while rotating the substrate at a first rotation speed, stopping a rotation of the substrate by decelerating the rotation of the substrate at a deceleration larger than 30000 rpm/sec at a point of time when the supply of the coating liquid is stopped, and then rotating the substrate at a second rotation speed. Accordingly, the dispense amount of the coating liquid is reduced and the film thickness of the coating liquid is flatten.Type: GrantFiled: July 2, 2007Date of Patent: July 13, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tomoaki Muramatsu, Yuko Kaimoto, Ichiro Omata
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Patent number: 7745351Abstract: Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.Type: GrantFiled: October 15, 2008Date of Patent: June 29, 2010Assignee: Applied Materials, Inc.Inventors: Xiaolin Chen, Srinivas D. Nemani, DongQing Li, Jeffrey C. Munro, Marlon E. Menezes
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Patent number: 7737055Abstract: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed.Type: GrantFiled: November 17, 2008Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventors: Paul D. Shirley, Hiroyuki Mori
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Patent number: 7727902Abstract: There is provided an underlayer coating that causes no intermixing with photoresist layer, can be formed by a spin-coating method, and can be used as a hard mask in lithography process of manufacture of semiconductor device. Concretely, it is an underlayer coating forming composition used in manufacture of semiconductor device including metal nitride particles having an average particle diameter of 1 to 1000 nm, and an organic solvent. The metal nitride particles contain at least one element selected from the group consisting of titanium, silicon, tantalum, tungsten, cerium, germanium, hafnium, and gallium.Type: GrantFiled: December 22, 2004Date of Patent: June 1, 2010Assignee: Nissan Chemical Industries, Ltd.Inventors: Satoshi Takei, Yasushi Sakaida
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Patent number: 7723218Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.Type: GrantFiled: April 11, 2005Date of Patent: May 25, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
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Patent number: 7723244Abstract: A method for internal electrical insulation of a substrate for a power semiconductor module having a framelike insulating housing with a cap and having an insulating substrate. The substrate has conductor tracks and power semiconductor components mounted thereon. The power semiconductor components are connected to connection elements, e.g., further conductor tracks or power semiconductor components, by means of bond connections. The method is characterized by the following steps: a) forming the substrate; b) coating the substrate with a viscous dielectric insulation compound in a casting process or immersion process; c) initiating the cross-linking of the insulation compound; d) with the substrate in a suspended position, permitting excess insulation compound to drip off, and securely enveloping the bond connections with insulation compound; and e) placing the substrate in the housing.Type: GrantFiled: May 4, 2005Date of Patent: May 25, 2010Assignee: SEMIKRON Elektronik GmbH & Co. KGInventors: Karlheinz Augustin, Christian Göbl
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Patent number: 7718551Abstract: A method for forming a photoresist layer is provided. The method includes following steps. A wafer is provided in a semiconductor machine. The wafer is spun at a first spin speed. A pre-wet solvent is dispensed on the spinning wafer by using a nozzle disposed at a fixed position. The pre-wet solvent then stops dispensing. The spin speed of the wafer is adjusted from the first spin speed to a second spin speed which is faster than the first spin speed. Thereafter, a photoresist layer is coated on the wafer.Type: GrantFiled: March 7, 2008Date of Patent: May 18, 2010Assignee: United MIcroelectronics Corp.Inventors: Yu-Huan Liu, Chih-Jung Chen, Chih-Chung Huang
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Patent number: 7718550Abstract: The present invention involves a method and apparatus for depositing a silicon oxide onto a substrate from solution at low temperatures in a manner that produces homogeneous growth of the silicon oxide. The method generally comprises the following steps: (a) Chemically treating a substrate to activate it for growth of the silicon oxide. (b) Immersing the treated substrate into a bath with a reactive solution. (c) Regenerating the reactive solution to allow for continued growth of the silicon oxide. In another embodiment of the present invention, the apparatus includes a first container holding a reactive solution, a substrate on which the silicon oxide is deposited, a second container holding silica, and a means for adding silica to the reactive solution.Type: GrantFiled: November 18, 2003Date of Patent: May 18, 2010Assignee: William Marsh Rice UniversityInventors: Andrew R. Barron, Elizabeth Anne Whitsitt
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Patent number: 7704895Abstract: A method for depositing a high-k dielectric material on a semiconductor substrate is disclosed. The method includes applying a chemical bath to a surface of a substrate, rinsing the surface, applying a co-reactant bath to the surface of the substrate, and rinsing the surface. The chemical bath includes a metal precursor which includes at least a hafnium compound, an aluminium compound, a titanium compound, zirconium compound, a scandium compound, a yttrium compound or a lanthanide compound.Type: GrantFiled: April 2, 2008Date of Patent: April 27, 2010Assignee: Intel CorporationInventors: Adrien R. Lavoie, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Mansour Moinpour
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Patent number: 7687406Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.Type: GrantFiled: July 17, 2006Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventors: Jon Daley, Yoshiki Hishiro
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Publication number: 20100075509Abstract: A manufacturing method for a semiconductor device, including: loading a wafer into a reaction chamber; placing the wafer on a push-up shaft moved up; preheating the wafer under controlling an in-plane temperature distribution of the wafer to be a recess state under a state of placing the wafer on the push-up shaft moved up; lowering the push-up shaft with the wafer kept in the recess state to hold the wafer on a wafer holding member; heating the wafer to a predetermined temperature; rotating the wafer; and supplying a process gas onto the wafer.Type: ApplicationFiled: September 21, 2009Publication date: March 25, 2010Inventors: Hironobu Hirata, Masayoshi Yajima, Yoshikazu Moriyama
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Patent number: 7678408Abstract: A method compensates film height modulations in spin coating of a resist film layer. From a desired layout pattern, a substrate topography as a result of lithographically structuring in image fields is determined. A spin coating model is provided to determine a modeled resist film height based on the substrate topography during spin coating of a resist film. A nominal resist film height by using the spin coating model with an unperturbed substrate topography having a flat surface is determined. Next, film height modulations based on a difference are determined for test points and the desired layout pattern is optimized by implementing further structural elements in order to form an optimized mask pattern by minimizing the film height modulations.Type: GrantFiled: September 9, 2005Date of Patent: March 16, 2010Assignee: Qimonda AGInventor: Thomas Mülders
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Patent number: 7674725Abstract: A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapor, and is used in a cleaning apparatus employing a Marangoni dryer.Type: GrantFiled: May 25, 2005Date of Patent: March 9, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Janos Farkas, Sebastien Petitdidier
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Patent number: 7674671Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.Type: GrantFiled: December 12, 2005Date of Patent: March 9, 2010Assignee: Optomec Design CompanyInventors: Michael J. Renn, Marcelino Essien, Bruce H. King, Jason A. Paulsen