Insulative Material Having Impurity (e.g., For Altering Physical Characteristics, Etc.) Patents (Class 438/783)
  • Patent number: 10199211
    Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 10023958
    Abstract: Provided are methods for the deposition of films comprising SiCN. Certain methods involve exposing a substrate surface to a silicon precursor, wherein the silicon precursor is halogenated with Cl, Br or I, and the silicon precursor comprises a halogenated silane, a halogenated carbosilane, an halogenated aminosilane or a halogenated carbo-sillyl amine. Then, the substrate surface can be exposed to a nitrogen-containing plasma or a nitrogen precursor and densification plasma.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: July 17, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Victor Nguyen, Ning Li, Mihaela Balseanu, Li-Qun Xia, Mark Saly, David Thompson
  • Patent number: 10008428
    Abstract: Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 26, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Hu Kang, Shankar Swaminathan, Adrien LaVoie, Jon Henri
  • Patent number: 9887082
    Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 6, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Gido Van Der Star, Toshiya Suzuki
  • Patent number: 9837263
    Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 5, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 9613819
    Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ming-Ching Chang, Yuan-Sheng Huang, Jui-Ming Chen, Chao-Cheng Chen
  • Patent number: 9362107
    Abstract: Methods are described for forming a flowable low-k dielectric film on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. Shortly after deposition, the silicon-carbon-oxygen layer is treated by exposure to a hydrogen-and-nitrogen-containing precursor such as ammonia prior to curing. The treatment may remove residual moisture from the silicon-carbon-oxygen layer and may make the lattice more resilient during curing and subsequent processing. The treatment may reduce shrinkage of the silicon-carbon-oxygen layer during subsequent processing.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 7, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Kiran V. Thadani, Abhijit Basu Mallick, Sanjay Kamath
  • Patent number: 9053927
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer; and modifying a surface of the second layer by supplying a hydrogen-containing gas to the substrate.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: June 9, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Atsushi Sano
  • Patent number: 9054046
    Abstract: A thin film including characteristics of low permittivity, high etching resistance and high leak resistance is to be formed. A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; and forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: June 9, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Atsushi Sano, Yugo Orihashi, Yoshitomo Hashimoto, Satoshi Shimamoto
  • Publication number: 20150140836
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. Methods are disclosed that discuss the use of blocking species that bind to the surface of the dielectric and retard the etching of the dielectric surface by a doping/passivating species. The surface of the dielectric may be exposed to the blocking species a plurality of times during the process to ensure that the surface is well protected.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Intermolecular, Inc.
    Inventor: Sandip Niyogi
  • Patent number: 9029272
    Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
  • Publication number: 20150118864
    Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: ASM IP Holding B.V.
    Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
  • Patent number: 9018093
    Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 28, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Naoto Tsuji, Fumitaka Shoji
  • Patent number: 9006114
    Abstract: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: April 14, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Volker Grimm, Heike Salz, Heike Berthold
  • Patent number: 8975143
    Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Byoung W. Min
  • Patent number: 8969110
    Abstract: A method of manufacturing an organic light-emitting display apparatus includes: providing an organic light emission part on a substrate; providing a first inorganic layer including a first low temperature viscosity transition (“LVT”) inorganic material on the substrate to cover the organic light emission part; and adding fluoride into the first inorganic layer using a fluorine group material such that the first inorganic layer is converted into a second inorganic layer comprising a second low temperature viscosity transition inorganic material.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jai-Hyuk Choi
  • Patent number: 8962433
    Abstract: A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Publication number: 20150044881
    Abstract: According to the present disclosure, a film containing carbon added at a high concentration is formed with high controllability. A method of manufacturing a semiconductor device includes forming a film containing silicon, carbon and a predetermined element on a substrate by performing a cycle a predetermined number of times. The predetermined element is one of nitrogen and oxygen. The cycle includes supplying a precursor gas containing at least two silicon atoms per one molecule, carbon and a halogen element and having an Si—C bonding to the substrate, and supplying a modifying gas containing the predetermined element to the substrate.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi SHIMAMOTO, Yoshiro HIROSE, Atsushi SANO
  • Publication number: 20150035073
    Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicants: GLOBALFOUNDRIES Inc., INTERNATIONAL BUSINESS MACHINES CORPORAITON
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Wing L. Lai, Vijay Narayanan, Ravikumar Ramachandran
  • Patent number: 8946095
    Abstract: A method of forming an interlayer dielectric film above a metal gate of a metal oxide semiconductor device comprises forming a metal gate above a semiconductor substrate; and forming the interlayer dielectric film above the metal gate by reacting a silicon-containing compound as precursor and a reactant for oxidizing the silicon-containing compound. The silicon-containing compound has the formula: Six(A)y(B)z(C)m(D)n??(I) wherein x is in the range of from 1 to 9; y+z+m+n is in the range of from 4 to 20; and A, B, C, and D independently represent a functional group connecting with a silicon atom. The functional group is selected from a group consisting of alkyl, alkenyl, alkynyl, aryl, alkylaryl, alkoxyl, alkylcarbonyl, carboxyl, alkylcarbonyloxy, amide, amino, alkylcarbonylamino, —NO2, and —CN.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li Chen, Jyh-Nan Lin, Chin-Feng Sun, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 8932954
    Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
  • Publication number: 20140346648
    Abstract: A low-K nitride film and a method of making are disclosed. Embodiments include forming a nitride film on a substrate by plasma enhanced chemical vapor deposition (PECVD) and periodically fluctuating a production of radicals during the PECVD based, at least in part, on plural cycles of a radiofrequency (RF) induced plasma.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Huy CAO, Huang LIU, Vijayalakshmi SESHACHALAM
  • Patent number: 8895456
    Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Tachibana, Hiroaki Ikegawa, Yu Wamura, Muneyuki Otani, Jun Ogawa, Kosuke Takahashi
  • Patent number: 8895377
    Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8846549
    Abstract: A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm?3 and an interface trap density of up to 5E11 cm?2 eV?1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 30, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yen-Hao Shih, Hang-Ting Lue, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20140273524
    Abstract: Provided are methods for the deposition and doping of films comprising Si. Certain methods involve depositing a SiN, SiO, SiON, SiC or SiCN film and doping the Si-containing film with one or more of C, B, O, N and Ge by a plasma implantation process. Such doped Si-containing films may have improved properties such as reduced etch rate in acid-based clean solutions, reduced dielectric constant and/or improved dielectric strength.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Ning Li, Martin A. Hilkene, Matthew D. Scotney-Castle
  • Patent number: 8828887
    Abstract: In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIE Inc.
    Inventors: Kai Frohberg, Frank Feustel, Thomas Werner
  • Patent number: 8815753
    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Majid Keshavarz, David E. Lazovsky
  • Patent number: 8796146
    Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 5, 2014
    Assignee: Optomec, Inc.
    Inventors: Michael J. Renn, Bruce H. King, Jason A. Paulsen
  • Patent number: 8785334
    Abstract: A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yoshitsugu Tanaka
  • Publication number: 20140179100
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventors: Sandip Niyogi, Amol Joshi, Chi-I Lang, Salil Mujumdar
  • Patent number: 8753969
    Abstract: A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20140159211
    Abstract: A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8735305
    Abstract: In some embodiments, the present invention discloses a gate dielectric deposition process, including depositing a fluorinated hafnium oxide by an ALD process utilizing a fluorinated hafnium precursor and an oxidant. A two-step ALD deposition process can be used, including a fluorinated hafnium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide high dielectric constant, high density, large bandgap and good thermal stability. Fluorinated hafnium oxide can passivate interface states and bulk traps in the hafnium oxide, for example, by forming Si—F or Hf—F bonds, which can improve the reliability of the hafnium oxide gate dielectrics.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Jinhong Tong
  • Patent number: 8728957
    Abstract: A thin film formation method to form a silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes alternately and repeatedly performing a first gas supply process in which a silane-based gas composed of silicon and hydrogen is supplied into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object to be processed and a second gas supply process in which an impurity-containing gas is supplied into the process chamber, to form an amorphous silicon film containing an impurity. Accordingly, an amorphous silicon film containing an impurity having good filling characteristics can be formed even at a relatively low temperature.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 20, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Akinobu Kakimoto
  • Patent number: 8716155
    Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak A. Ramappa, Kyu-Ha Shim
  • Patent number: 8697584
    Abstract: By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Andy Wei, Roman Boschke
  • Patent number: 8697513
    Abstract: In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryo Tanabe
  • Patent number: 8691609
    Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 8, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Peter Smith, Jane Blake, Leon Cavanagh, Raymond Speer
  • Patent number: 8669148
    Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8669131
    Abstract: Gas sensor materials and methods are disclosed for preparing and using the same to produce gas sensor structures. Also disclosed are gas sensor structures and systems that employ these disclosed materials. A gas sense-enhancing metal such as platinum may be added to a gas sensitive metal oxide material in a manner that more highly disperses the added platinum than conventional methods so as to more effectively utilize the platinum at a lower concentration, thus achieving a more cost effective solution. An ink vehicle may also be used for deposition of a gas sensitive material (e.g. on the surface of integrated circuit) that is formulated to allow “burn-out” of ink vehicle components at relatively low temperatures as compared to conventional ink vehicles.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 11, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Peter Smith, Jane Blake, Leon Cavanagh, Raymond Speer
  • Patent number: 8657961
    Abstract: Embodiments of the invention generally provide methods for cleaning a UV processing chamber. In one embodiment, the method includes flowing an oxygen-containing gas through a plurality of passages formed in a UV transparent gas distribution showerhead and into a processing region located between the UV transparent gas distribution showerhead and a substrate support disposed within the thermal processing chamber, exposing the oxygen-containing gas to UV radiation under a pressure scheme comprising a low pressure stage and a high pressure stage to generate reactive oxygen radicals, and removing unwanted residues or deposition build-up from exposed surfaces of chamber components presented in the thermal processing chamber using the reactive oxygen radicals.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Scott A. Hendrickson, Sanjeev Baluja, Juan Carlos Rocha-Alvarez
  • Patent number: 8642426
    Abstract: It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: February 4, 2014
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8586487
    Abstract: Methods and apparatus for forming conformal silicon nitride films at low temperatures on a substrate are provided. The methods of forming a silicon nitride layer include performing a deposition cycle including flowing a processing gas mixture into a processing chamber having a substrate therein, wherein the processing gas mixture comprises precursor gas molecules having labile silicon to nitrogen, silicon to carbon, or nitrogen to carbon bonds, activating the precursor gas at a temperature between about 20° C. to about 480° C. by preferentially breaking labile bonds to provide one or more reaction sites along a precursor gas molecule, forming a precursor material layer on the substrate, wherein the activated precursor gas molecules bond with a surface on the substrate at the one or more reaction sites, and performing a plasma treatment process on the precursor material layer to form a conformal silicon nitride layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 19, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty
  • Patent number: 8569185
    Abstract: A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Hui Ouyang, Han-Pin Chung, Shiang-Bau Wang
  • Patent number: 8569186
    Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
  • Patent number: 8563443
    Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: ASM Japan K.K.
    Inventor: Atsuki Fukazawa
  • Patent number: 8563421
    Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Bon-young Koo, Ki-hyun Hwang
  • Patent number: 8546236
    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 1, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Deweerd, Mitsuhiro Horikawa, Kenichi Koyanagi, Hiroyuki Ode, Xiangxin Rui
  • Patent number: 8546274
    Abstract: A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: October 1, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joerg Hohage, Michael Finken, Ralf Richter