Introduction Simultaneous With Deposition Patents (Class 438/784)
  • Patent number: 10147600
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 4, 2018
    Assignee: ASM INTERNATIONAL N.V.
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Patent number: 10068776
    Abstract: An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal light beam. The planar surface encompasses a filled via that is in electrical and physical contact with a bond pad that is also on the planar surface.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Frank Truong, Praneeth Akkinepally, Shruti R. Jaywant, Dilan Seneviratne
  • Patent number: 9875893
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 23, 2018
    Assignee: ASM INTERNATIONAL N.V.
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Patent number: 9842871
    Abstract: Object is to prevent deterioration in pixel characteristics due to dark-time white spot defects in a pixel. Generation of these dark-time white spot defects is attributable to diffusion of electrons and Fe (iron) from the vicinity of an interface between a semiconductor substrate and an element isolation region obtained by filling a trench formed in the upper surface of the semiconductor substrate with an insulating film. A semiconductor layer is formed by forming, in the upper surface of a semiconductor substrate, a trench for filling it with an element isolation region surrounding a photodiode formation region; and carrying out plasma doping to introduce B (boron) into the side wall and bottom surface of the trench.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: December 12, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Patent number: 9746783
    Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang-Yao Lee, Jyh-Kang Ting, Tsung-Chieh Tsai, Juing-Yi Wu
  • Patent number: 9631273
    Abstract: An apparatus comprises a first gas inlet coupled between a first pipe and a reaction chamber, wherein the first pipe configured to carry process gases, a second gas inlet coupled between a second pipe and the reaction chamber, wherein the second pipe configured to carry a precursor material in a gaseous state and a heating device coupled to the second pipe and the second gas inlet, wherein the heating device keeps an ambient temperature of the second pipe and the second gas inlet above a boiling point of the precursor material.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan-Hai Wang, Ding-I Liu, Si-Wen Liao, Po-Hsiung Leu, Yong-Hung Yang
  • Patent number: 9564314
    Abstract: The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 7, 2017
    Assignee: ASM International N.V.
    Inventors: Noboru Takamure, Atsuki Fukazawa, Hideaki Fukuda, Antti Niskanen, Suvi Haukka, Ryu Nakano, Kunitoshi Namba
  • Patent number: 9165762
    Abstract: A method of forming silicon dioxide films using plasma enhanced chemical vapor deposition (PECVD) uses tetraethyl orthosilicate (TEOS), oxygen or a source of oxygen, and hydrogen as precursors. The method can be carried out at low temperatures in a range of 125 to 175° C. which is useful for manufacturing wafers with through silicon vias.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 20, 2015
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Kathrine Crook, Andrew Price, Mark Carruthers, Daniel Archard, Stephen Burgess
  • Patent number: 9165783
    Abstract: Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: October 20, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Jeremiah T. Pender, Qingjun Zhou, Dmitry Lubomirsky, Sergey G. Belostotskiy
  • Patent number: 9058982
    Abstract: An insulating film that does not contain hydrogen or free fluorine and has good film properties is provided. A silicon oxynitride film includes silicon, nitrogen, oxygen, and fluorine, wherein the elemental percentage (N+O+F)/Si of the total (N+O+F) of nitrogen (N), oxygen (O), and fluorine (F) to silicon (Si) is in a range of 1.93 to 1.48, and in the silicon oxynitride film, an elemental percentage of silicon ranges from 0.34 to 0.41, an elemental percentage of nitrogen ranges from 0.10 to 0.22, an elemental percentage of oxygen ranges from 0.14 to 0.38, and an elemental percentage of fluorine ranges from 0.17 to 0.24. The film can be formed on a substrate by inductive coupling type plasma CVD whereby a plasma is generated by inductive coupling using a silicon tetrafluoride gas, a nitrogen gas, and an oxygen gas as a material gas.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: June 16, 2015
    Assignee: NISSIN ELECTRIC CO., LTD.
    Inventors: Yasunori Ando, Eiji Takahashi, Masaki Fujiwara
  • Patent number: 9054188
    Abstract: An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Ming Chang, Wen-Huei Guo, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann, Tung Ying Lee, Cheng-Long Chen, Jui-Chien Huang
  • Patent number: 8969110
    Abstract: A method of manufacturing an organic light-emitting display apparatus includes: providing an organic light emission part on a substrate; providing a first inorganic layer including a first low temperature viscosity transition (“LVT”) inorganic material on the substrate to cover the organic light emission part; and adding fluoride into the first inorganic layer using a fluorine group material such that the first inorganic layer is converted into a second inorganic layer comprising a second low temperature viscosity transition inorganic material.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jai-Hyuk Choi
  • Patent number: 8962454
    Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: February 24, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Hiroyuki Takaba
  • Publication number: 20150044882
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 12, 2015
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Patent number: 8940648
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2), chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 27, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Publication number: 20150021693
    Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 22, 2015
    Inventors: Peter Javorka, Stefan Flachowsky
  • Patent number: 8895456
    Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Tachibana, Hiroaki Ikegawa, Yu Wamura, Muneyuki Otani, Jun Ogawa, Kosuke Takahashi
  • Patent number: 8883624
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 11, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 8822350
    Abstract: An oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element, to the substrate housed in a processing chamber and heated to a first temperature; and changing the specific element-containing layer formed on the substrate, to an oxide layer by supplying a reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure of less than atmospheric pressure and heated to a second temperature higher than the first temperature.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Yuasa, Ryuji Yamamoto
  • Patent number: 8815751
    Abstract: There is provided a method of manufacturing a semiconductor device, including: forming a film containing a specific element, nitrogen, and carbon on a substrate, by alternately performing the following steps a specific number of times: a step of supplying a source gas containing the specific element and a halogen element, to the substrate; and a step of supplying a reactive gas composed of three elements of carbon, nitrogen, and hydrogen and having more number of a carbon atom than the number of a nitrogen atom in a composition formula thereof, to the substrate.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 26, 2014
    Assignees: Hitachi Kokusai Electric Inc., L'Air Liquide-Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Yoshiro Hirose, Atsushi Sano, Kazutaka Yanagita, Katsuko Higashino
  • Patent number: 8765616
    Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8764993
    Abstract: A method of making a porous SiOC membrane is provided. The method comprises disposing a SiOC layer on a porous substrate, and etching the SiOC layer to form through pores in the SiOC layer. A porous SiOC membrane having a network of pores extending through a thickness of the membrane is provided.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: July 1, 2014
    Assignee: General Electric Company
    Inventors: Atanu Saha, Salil Mohan Joshi, An-Ping Zhang
  • Patent number: 8741772
    Abstract: A resistive memory device having an in-situ nitride initiation layer is disclosed. The nitride initiation layer is formed above the first electrode, and the metal oxide switching layer is formed above the nitride initiation layer to prevent oxidation of the first electrode. The nitride initiation layer may be a metal nitride layer that is formed by atomic layer deposition in the same chamber in which the metal oxide switching layer is formed. The nitride initiation layer and metal oxide switching layer may alternatively be formed in a chemical vapor deposition (CVD) chamber or a physical vapor deposition (PVD) chamber.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: June 3, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventor: Albert Lee
  • Patent number: 8739429
    Abstract: A system for drying a surface of a substrate is provided. The system for drying a surface of a substrate comprising: a rotary support; a first dispenser fluidly coupled to a source of liquid, the first dispenser positioned above the surface of the substrate so as to be capable of applying a film of the liquid to the surface of the substrate; a second dispenser fluidly coupled to a source of drying fluid with a supply line, the second dispenser positioned above the surface of the substrate so as to be capable of applying the drying fluid to the surface of the substrate; and a proportional valve operably coupled to the supply line between the second dispenser and the source of drying fluid, the proportional valve capable of being incrementally adjusted from a closed position to an open position.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: June 3, 2014
    Inventors: Zhi Lewis Liu, Hanjoo Lee, Ismail Kashkoush
  • Patent number: 8728956
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
  • Patent number: 8728957
    Abstract: A thin film formation method to form a silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes alternately and repeatedly performing a first gas supply process in which a silane-based gas composed of silicon and hydrogen is supplied into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object to be processed and a second gas supply process in which an impurity-containing gas is supplied into the process chamber, to form an amorphous silicon film containing an impurity. Accordingly, an amorphous silicon film containing an impurity having good filling characteristics can be formed even at a relatively low temperature.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 20, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Akinobu Kakimoto
  • Patent number: 8697578
    Abstract: A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate while supplying a film formation reactive gas from a first nozzle inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited inside the reaction chamber and the first nozzle, in a state where the reaction chamber does not accommodate the target substrate. The cleaning process includes, in order, an etching step of supplying a cleaning reactive gas for etching the by-product film into the reaction chamber, and activating the cleaning reactive gas, thereby etching the by-product film, and an exhaust step of stopping supply of the cleaning reactive gas and exhausting gas from inside the reaction chamber. The etching step is arranged to use conditions that cause the cleaning reactive gas supplied in the reaction chamber to flow into the first nozzle.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: April 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Nobutake Nodera, Jun Sato, Kazuya Yamamoto, Kazuhide Hasebe
  • Patent number: 8685815
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8657959
    Abstract: An apparatus for atomic layer deposition of a material on a moving substrate comprises a conveying arrangement for moving a substrate along a predetermined planar or curved path of travel and a coating bar having at least one precursor delivery channel. The precursor delivery channel conducts a fluid containing a material to be deposited on a substrate toward the path of travel. When in use, a substrate movable along the path of travel defines a gap between the outlet end of the precursor delivery channel and the substrate. The gap defines an impedance Zg to a flow of fluid from the precursor delivery channel. A flow restrictor is disposed within the precursor delivery channel that presents a predetermined impedance Zfc to the flow therethrough. The restrictor is sized such that the impedance Zfc is at least five (5) times, and more preferably at least fifteen (15) times, the impedance Zg. The impedance Zfc has a friction factor f.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 25, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Geoffrey Nunes, Richard Dale Kinard
  • Patent number: 8658490
    Abstract: Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: February 25, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elke Erben, Martin Trentzsch, Richard J. Carter
  • Patent number: 8637413
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: January 28, 2014
    Assignees: Sandisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Charlene Chen, Dipankar Pramanik
  • Patent number: 8617989
    Abstract: Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 ?m. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kedar Sapre, Manuel Hernandez, Lei Luo
  • Patent number: 8603900
    Abstract: Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 10, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Deepak Ramappa
  • Patent number: 8564104
    Abstract: According to an embodiment of the invention, a passivation layer structure of a semiconductor device disposed on a semiconductor substrate is provided, which includes a passivation layer structure disposed on the semiconductor substrate, wherein the passivation layer structure includes a halogen-doped aluminum oxide layer. According to an embodiment of the invention, a method for forming a passivation structure of a semiconductor device is provided.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: October 22, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Ching Sun, Tzer-Shen Lin, Sheng-Min Yu
  • Patent number: 8530361
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2)n chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8524616
    Abstract: A method is provided for reducing film surface roughness in Chemical Vapor Deposition (CVD) of dielectric films. The method may include removing dangling bonds from a film surface of a CVD dielectric film by a reactant. For reducing a surface roughness of a dielectric film, a further method may passivate a nonstoichiometric film surface of the dielectric film, or of a previous dielectric film, or of the dielectric film and of a previous dielectric film, by a reactant gas in the vapor environment. The dielectric film may include at least one out of the following group: ultraviolet light transparent Silicon Nitride (UVSIN), Silicon Rich Oxide (SRO), Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), Phosphosilicate Glass (PSG), or Silicon Oxynitride (SiON) The reactant gas may include at least one out of the following group: Ammonia (NH3), Hydrogen (H2), Nitrous Oxide (N2O), or Oxygen (O2).
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: September 3, 2013
    Assignee: Microchip Technology Incorporated
    Inventors: Lance Kim, Kwanghoon Kim
  • Publication number: 20130122722
    Abstract: A method of forming a dielectric material, comprising doping a zirconium oxide material, using a dopant precursor selected from the group consisting of Ti(NMe2)4; Ti(NMeEt)4; Ti(NEt2)4; TiCl4; tBuN?Nb(NEt2)3; tBuN?Nb(NMe2)3; t-BuN?Nb(NEtMe)3; t-AmN?Nb(NEt2)3; t-AmN?Nb(NEtMe)3; t-AmN?Nb(NMe2)3; t-AmN?Nb(OBu-t)3; Nb-13; Nb(NEt2)4; Nb(NEt2)5; Nb(N(CH3)2)5; Nb(OC2H5)5; Nb(thd)(OPr-i)4; SiH(OMe)3; SiCU; Si(NMe2)4; (Me3Si)2NH; GeRax(ORb)4.x wherein x is from 0 to 4, each Ra is independently selected from H or C1-C8 alkyl and each Rb is independently selected from C1-C8 alkyl; GeCl4; Ge(NRa2)4 wherein each Ra is independently selected from H and C1-C8 alkyl; and (Rb3Ge)2NH wherein each Rb is independently selected from C1-C8 alkyl; bis(N,N?-diisopropyl-1,3-propanediamide) titanium; and tetrakis(isopropylmethylamido) titanium; wherein Me is methyl, Et is ethyl, Pr-i is isopropyl, t-Bu is tertiary butyl, t-Am is tertiary amyl, and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate.
    Type: Application
    Filed: June 23, 2011
    Publication date: May 16, 2013
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventors: Julie Cissell, Chongying Xu, Thomas M. Cameron, William Hunks, David W. Peters
  • Patent number: 8405167
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8389421
    Abstract: When an object to be processed is transferred into a process chamber capable of keeping a vacuum and an interior of the process chamber is kept in a vacuum state, the film formation method includes performing forming a first ZrO film on the object to be processed by supplying a zirconium material and an oxidizing agent in the order listed above into the process chamber and forming a second ZrO film doped with Si on the object to be processed by supplying the zirconium material, a silicon material, and the oxidizing agent in the order listed above into the process chamber, in such a way that a number of times the forming the first ZrO film is performed and a number of times the forming the second ZrO film is performed are adjusted, respectively, to form a zirconia-based film having a predetermined film thickness while controlling a Si concentration in the film.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: March 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Katsushige Harada, Yuichiro Morozumi, Shingo Hishiya
  • Patent number: 8354341
    Abstract: A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: January 15, 2013
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Ming Zhou, Yonggen He
  • Publication number: 20130012034
    Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8309424
    Abstract: Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Alex J. Schrinsky
  • Publication number: 20120115334
    Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.
    Type: Application
    Filed: March 28, 2011
    Publication date: May 10, 2012
    Inventor: Hiroyuki Takaba
  • Publication number: 20120104566
    Abstract: According to an embodiment of the invention, a passivation layer structure of a semiconductor device for disposed on a semiconductor substrate is provided, which includes a passivation layer structure disposed on the semiconductor substrate, wherein the passivation layer structure includes a halogen-doped aluminum oxide layer. According to an embodiment of the invention, a method for forming a passivation structure of a semiconductor device is provided.
    Type: Application
    Filed: April 11, 2011
    Publication date: May 3, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Ching Sun, Tzer-Shen Lin, Sheng-Min Yu
  • Patent number: 8080483
    Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 20, 2011
    Assignee: Purdue Research Foundation
    Inventors: Hugh W. Hillhouse, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
  • Publication number: 20110300719
    Abstract: When an object to be processed is transferred into a process chamber capable of keeping a vacuum and an interior of the process chamber is kept in a vacuum state, the film formation method includes performing forming a first ZrO film on the object to be processed by supplying a zirconium material and an oxidizing agent in the order listed above into the process chamber and forming a second ZrO film doped with Si on the object to be processed by supplying the zirconium material, a silicon material, and the oxidizing agent in the order listed above into the process chamber, in such a way that a number of times the forming the first ZrO film is performed and a number of times the forming the second ZrO film is performed are adjusted, respectively, to form a zirconia-based film having a predetermined film thickness while controlling a Si concentration in the film.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 8, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Katsushige HARADA, Yuichiro MOROZUMI, Shingo HISHIYA
  • Patent number: 8043981
    Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. A two frequency plasma source is used to form a plasma in a plasma reactor. In various embodiments, different quantities of power are supplied to a power source operating at the first frequency and a power source operating at the second frequency over time.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: October 25, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Kai Ma, Yoshitaka Yokota, Christopher S. Olsen
  • Patent number: 8021991
    Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: September 20, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr
  • Patent number: 7994070
    Abstract: A method for depositing a dielectric film on a substrate includes positioning a plurality of substrates in a process chamber, heating the process chamber to a deposition temperature between 400° C. and less than 650° C., flowing a first process gas comprising water vapor into the process chamber, flowing a second process gas comprising dichlorosilane (DCS) into the process chamber, establishing a gas pressure of less than 2 Torr, and reacting the first and second process gases to thermally deposit a silicon oxide film on the plurality of substrates. One embodiment further includes flowing a third process gas comprising nitric oxide (NO) gas into the process chamber while flowing the first process gas and the second process gas; and reacting the oxide film with the third process gas to form a silicon oxynitride film on the substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 9, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Anthony Dip, Kimberly G Reid
  • Patent number: 7981791
    Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: July 19, 2011
    Assignee: ASM International N.V.
    Inventors: Suvi P. Haukka, Ivo Raaijmakers, Wei Min Li, Juhana Kostamo, Hessel Sprey, Christiaan J. Werkhoven