Introduction Simultaneous With Deposition Patents (Class 438/784)
  • Patent number: 5804259
    Abstract: A method and apparatus for forming a multilayer insulating film on a substrate involves forming a number of carbon-based layers on the substrate, each interlaid with layers of organic material, such as parylene. Preferably, the carbon-based layers are formed using a high-density plasma chemical vapor deposition system, although other CVD systems may also be used. The result is a multilayer insulating film having a low overall dielectric constant, excellent gap-fill characteristics, and desirable thermal properties.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: September 8, 1998
    Assignee: Applied Materials, Inc.
    Inventor: Stuardo Robles
  • Patent number: 5747389
    Abstract: A method for making a device and the device itself which utilizes a passivation layer displaying improved crack resistance is disclosed. This is accomplished through the incorporation of boron into a PSG passivation layer. The temperature of the passivation deposition may need to be kept to a temperature low enough so that the boron compound used for the boron source does not decompose prior to reacting with other reactants.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventor: John K. Chu
  • Patent number: 5744399
    Abstract: A process for lowering the dielectric constant of a layer on a semiconductor wafer is described. The presence of the fullerene in the composite layer changes its dielectric constant. The process forms, on the wafer, a composite layer comprising matrix-forming material and a fullerene. The fullerene may be removed from the composite layer to leave an open porous layer. Removing the fullerene may be accomplished, for example, by contacting the composite layer with a liquid which is a solvent for the fullerene but not for the insulation material or by oxidizing the fullerene. The processes and insulation layers described are particularly useful for integrated circuits.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: April 28, 1998
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch
  • Patent number: 5716890
    Abstract: The present invention provides a structure and method of manufacturing an interlevel/intermetal dielectric layer for a semiconductor device. The method begins by forming a stepped pattern 16 on a semiconductor structure 12. A barrier layer 20 composed of silicon oxide is formed on the semiconductor substrate so as to cover the surface of the stepped pattern 16. A first insulating layer 22 composed of silicon oxide is then formed over the barrier layer 20. A high P (phosphorous) content silicon glass layer 24 preferably is formed over the first insulating layer 22. The high P content silicon glass layer 24 has a phosphorous concentration in a range of about 4 and 10 weight percent. Next, in an important step, a graded P content silicon glass layer 26 is formed over the high P content silicon glass layer 24. The graded P content silicon glass layer 26 has a phosphorous concentration in a range of about 0.1 and 4 weight percent.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: February 10, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Liang-Gi Yao
  • Patent number: 5716891
    Abstract: With forming an element isolation oxide layer on p-well in a thickness of 3500 .ANG., n-type MOS transistor with a gate electrode and source and drain regions are fabricated. Thereafter, an oxide layer is deposited by an atmospheric pressure chemical vapor deposition. Subsequently, with taking TEOS as material, a TEOS-BPSG layer is deposited by way of a reduced pressure chemical vapor deposition. Then, under inert atmosphere, heat treatment is performed at a temperature higher than or equal to 700.degree. C. to remove organic component in the layer. Thereafter, reflow process is performed at a temperature of approximately 900.degree. C. under nitrogen atmosphere at normal pressure. By this, the organic component in the BPSG layer formed utilizing TEOS can be removed out of the layer to improve element isolation characteristics and reduce leak current.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: February 10, 1998
    Assignee: NEC Corporation
    Inventor: Noriyuki Kodama
  • Patent number: 5661093
    Abstract: A method and apparatus for depositing a halogen-doped oxide film having a low dielectric constant that is resistant to moisture absorption and outgassing of the halogen dopant, and that retains these qualities despite subsequent processing steps. The method begins by introducing process gases (including a halogen-containing source gas) into a processing chamber. A halogen-doped layer is then deposited. The combination of process gases is then changed and a sealing layer deposited which seals the dopant into the halogen-doped layer. The sealing layer may, for example, be a carbon-rich layer or an undoped layer. These steps are repeated until the film reaches a selected thickness.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: August 26, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Kramadhati V. Ravi, Maciek Orczyk
  • Patent number: 5629246
    Abstract: This invention is a method for forming fluorine-doped silicate glass having low concentrations of free fluorine atoms. A first embodiment of the invention provides simultaneous deposition of the fluorine-doped glass and scavenging of free fluorine atoms from the surface of the depositing material. A silicon-containing compound, an oxidizer, a fluorine containing compound and a hydrogen-containing gas are introduced into a plasma chemical vapor deposition chamber. A fluorine-doped glass layer having low concentrations of free fluorine atoms deposits. A second embodiment of the invention provides for scavenging of free fluorine atoms from an already-deposited fluorine-doped glass layer by annealing the layer in a forming gas containing hydrogen. The hydrogen gas diffuses into the deposited film and reacts with free fluorine atoms. The hydrogen fluoride so formed migrates through the matrix to the surface of the deposited film, where it is released into the ambient.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: May 13, 1997
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer