Abstract: A method for liquid phase deposition, including the steps of providing at least two raw materials from at least two supply devices of a saturation reaction system into a mixture trough and stirring until saturation occurs, filtering out unnecessary solid-state particles, and providing saturated and filtered liquid into an over-saturation reaction trough of a steady-flow over-saturation loop reaction system and stopping the saturated and filtered liquid when the over-saturation reaction trough is filled and the saturated and filtered liquid over-flows into a liquid level control trough to a pre-determined level. The method also includes the steps of providing a substrate in the over-saturation reaction trough, providing reactants from at least two supply devices into the over-saturation reaction trough, and depositing a thin film onto the substrate when the saturated liquid becomes over-saturated.

Abstract: A method for forming an ultra-thin (between about 15 to 20 Angstroms), silicon dioxide gate insulator layer, featuring a process sequence which widens the process window of the thermal oxidation procedure, and improves the quality of the ultra-thin silicon dioxide gate insulator layer, has been developed. After a series of wet clean procedures applied to a semiconductor substrate, a high temperature anneal procedure is performed in an inert ambient. The high temperature anneal removes organic, as well as inorganic material not removed during the wet clean procedures, and also removes native oxide formed during these same wet clean procedures. The removal of these materials allow the use of longer thermal oxidation times still resulting in silicon dioxide thickness equal to counterparts formed using shorter oxidation times, which were not subjected to the pre-oxidation high temperature anneal procedure.

Abstract: A method of chemical mechanical polishing a metal layer on a substrate in which the substrate is polished at a first polishing rate. Polishing is monitored with an eddy current monitoring system, and the polishing rate is reduced to a second polishing rate when the eddy current monitoring system indicates that a predetermined thickness of the metal layer remains on the substrate. Then polishing is monitored with an optical monitoring system, and polishing is halted when the optical monitoring system indicates that an underlying layer is at least partially exposed.

Abstract: The memory element of the present invention utilizes a substrate, a first conductive connection, a second conductive connection, and an ionic layer. The substrate includes a source region, a drain region, and a channel region, which is disposed between the source region and the drain region. The ionic layer includes ions and is coupled to the substrate. The first connection is coupled to the source region, and the second connection is coupled to the drain region. An electrical field is applied through said ionic layer such that the ions in the ionic layer move. When the memory element is to exhibit a logical high state, the polarity of the electrical field causes the ions to move toward the channel region. This pulls the electrons in the source and drain regions into the channel region making the channel region conductive. When the memory element is to exhibit a logical low state, the polarity of the electrical field causes the ions to move away from the channel region.

Abstract: The present invention concerns a method to produce a porous oxygen-silicon insulating layer comprising following steps: applying a silicon oxygen layer to a substrate exposing the said substrate to a HF ambient.

Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in a reactor chamber. A key feature of the invention's process is a mole ratio of gas additive to source of silicon, which is maintained in the range of about 0.3-20 depending on the compound used and the deposition process conditions. As a gas additive, one of the group including halide-containing organic compounds having the general formula CxHyRz, and chemical compounds with the double carbon-carbon bonds having the general formula CnH2n, is used.

Abstract: This invention includes: a plasma-making step of making into plasma a film-forming gas including a compound of carbon and fluorine and an etching gas which can etch a film of fluorine-added carbon; and a film-forming step of forming a film of fluorine-added carbon onto an object to be processed by means of the plasma made in the plasma-making step. For example, the film-forming gas including a compound of carbon and fluorine includes a gas of a compound having a benzene ring. For example, the etching gas which can etch a film of fluorine-added carbon is a gas including fluorine. According to the invention, a concave portion can be satisfactory filled up with the CF film.

Abstract: A compensating chemical mechanical wafer polishing apparatus and its related polishing method, which makes end point detection easy, minimizes slurry consumption, and requires less installation space and, in which a main polishing head of diameter smaller than the wafer and a compensating polishing head are used to polish the wafer, which is upwardly disposed in contact with the polishing heads. By means of the operation of the compensating polishing head to polish the wafer over the area where the main polishing head cannot effectively evenly polish, satisfactory polishing effect is achieved.

Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.

Abstract: A process for polishing a semiconductor body according to an embodiment of the present invention includes the steps of providing a semiconductor body, forming a barrier layer over a portion of the semiconductor body, and forming at least one layer including copper over a portion of the barrier layer. The process further includes the steps of polishing at least a portion of the layer including copper with a first polishing slurry composition and changing the polishing composition from the first slurry composition to a second polishing slurry composition. The process also includes the steps of polishing at least a portion of the layer including copper with the second slurry composition and polishing at least a portion of the barrier layer with the second slurry composition. Moreover, the second slurry composition includes an effective amount of a copper oxide inhibitor to substantially inhibit copper oxide formation. In an embodiment, the effective amount of the copper oxide inhibitor is between about 0.

Abstract: A semiconductor device producing method carries out an etching process during a time between a start and an end of a plasma etching, and carries out a plasma etching with respect to a specific metal as a pre-processing prior to the etching process. The etching process is selected from a group consisting of an etching process which includes no exposing of a specific metal which affects variation of an etching rate, an etching process which includes no positioning of the specific metal exposed from an etching mask, an etching process which includes exposing of the specific metal located at a surface other than an etching target surface of a semiconductor substrate, and an etching process which includes exposing the specific metal having a thickness smaller than a thickness of other etching targets regardless of an existence of the etching mask.

Abstract: A semiconductor package and a fabricating method thereof are proposed, in which a substrate is prepared for having at least one flash preventing mechanism disposed on a surface of the substrate corresponding to a position in front of an entry of an air vent in a mold. After a semiconductor chip is mounted on the substrate by a plurality of conductive elements, a molding compound having high fluidity and fine filler particles is used to encapsulate the chip and the flash preventing mechanism. As the flash preventing mechanism is disposed in a manner of reducing the entry space of the air vent, the flow of the molding compound is impeded by the flash preventing mechanism, making the molding compound rapidly absorb heat of the mold and accordingly increased in viscosity. This helps prevent flash of the molding compound from occurrence, and assure the semiconductor package in quality and profile.

Abstract: The present invention pertains to apparatus and methods for maintaining wafer back side, bevel, and front side edge exclusion during supercritical fluid processing. Apparatus of the invention include a pedestal and an exclusion ring. When the exclusion ring is engaged with the pedestal a channel is formed. A reactant-free supercritical fluid is passed through the channel and over a circumferential front edge of a wafer. The flow of reactant-free supercritical fluid protects the bevel and circumferential front edge of the wafer from exposure to reactants in a supercritical processing medium. The back side of the wafer is protected by contact with the pedestal and the flow of reactant-free supercritical fluid. Exclusion rings of the invention, when engaged with their corresponding pedestals make no or very little physical contact with the wafer front side.

Abstract: In a method of forming a metal gate of a semiconductor device, a substrate is provided, which includes a substrate body covered by a dielectric layer. A metal body having top and side surface is provided on the dielectric layer. A self-assembled monolayer is provided over the top and side surfaces of the metal body, and has an ordered region covering the top surface of the metal body and disordered regions covering the side surfaces of the metal body. The resulting structure is etched, the disordered regions of the self-assembled monolayer allowing etching of the side surfaces of the metal body while the ordered region of the self-assembled monolayer substantially blocks etching of the top surface of the metal body.

Abstract: An improved process for depositing a robust fluorosilicate glass film on a substrate in a chamber includes maintaining a total pressure in the chamber of less than about 1.7 torr, introducing vapor phase chemicals such as N2, SiF4, SiH4, and N2O into the chamber, and reacting the vapor-phase chemicals with sufficiently supplied energy to deposit a thin film layer of the fluorosilicate glass on the substrate. Advantageously, the deposited fluorosilicate glass films are chemically, mechanically, and thermally stable without additional processing. Also advantageously, the films are deposited uniformly at rates greater than about 5000 Angstroms per minute with dielectric constants of about 3.4 to about 3.9.

Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: An inductively-coupled hydrogen plasma (ICP) is used to passivate a plasma-enhanced chemical vapor deposition reactor following an in situ cleaning step. The hydrogen ICP effectively removes the fluorine and hydrogen that typically become impregnated in the walls of the reaction chamber during the in situ clean and thereby reduces the amount of “outgassing” that occurs during subsequent deposition cycles. This outgassing may cause the film of deposition material that normally forms on the walls to flake, significantly reducing the yield of usable devices. The hydrogen ICP passivation process has been found particularly effective in conjunction with the deposition of heavily-doped silicon oxide layers.

Abstract: A wafer transfer method, by which, when a wafer is loaded into a system, heat shock applied to the wafer can be relieved, the frequency of occurrence of crystal dislocation such as slip can be decreased, and productivity can be improved due to saving of energy and time required for heating and cooling of the system, and there is also provided a wafer support member used for this method. In this method, a step for transferring wafers so as to replace a wafer, which finishes its thin film growth process, with a following wafer, which is to be subjected to its thin film growth process, is carried out under the temperature being higher than the room temperature, while the wafer 1 is transferred integrally with a wafer support member 2 used for the thin film growth process.

Abstract: A method of forming an integrated circuit using a fluoro-organosilicate layer is disclosed. The fluoro-organosilicate layer is formed by applying an electric field to a gas mixture comprising a fluoro-organosilane compound and an oxidizing gas. The fluoro-organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the fluoro-organosilicate layer is used as a hardmask. In another integrated circuit fabrication process, the fluoro-organosilicate layer is incorporated into a damascene structure.

Abstract: After forming a conductive layer on the entire surface of an insulation substrate, a resin mask of poly lactic acid etc. resin which will hydrolyze in an alkali aqueous solution is integrally formed on the insulation substrate so that a part to which a conductive layer of a predetermined pattern is to be formed is exposed. Then, a conductive layer is overlaid on the part exposed from the resin mask by means of electrolytic plating using an acidic bath composition. The interface between the resin mask of poly lactic acid etc. resin and the conductive layer reproduces an accurate contour of the pattern. Thereafter, the resin mask is efficiently removed by hydrolysis using an alkali aqueous solution, and finally the conductive layer is removed by chemical etching to thereby form a conductive layer having the predetermined pattern on the surface of the insulation substrate.

Abstract: An intermediary dielectric layer is disposed between two dielectric layers thereby eliminating a flow stabilization step that may produce unwanted deposition that leads to peeling. A wafer is provided having an HDP layer. An undoped silicon glass layer is deposited on top of the HDP layer to improve adherence of a subsequently deposited PSG layer.

Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.

Abstract: A fluorine-containing organic film having a relative dielectric constant of 4 or less is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. During the deposition of the fluorine-containing organic film, a scavenger gas for scavenging fluorine constituting the fluorocarbon is mixed in the material gas. The proportion of the mixed scavenger gas in the material gas is changed to adjust the mechanical strength and relative dielectric constant of the fluorine-containing organic film.

Abstract: A method described for making a semiconductor transistor having a thin gate dielectric layer with a high k-value but without any impurities in a channel in silicon directly below the gate dielectric layer. An apparatus is used which pulses a cathode to create a plasma generating voltage potential between the cathode and an anode provided by a wall of a chamber of the apparatus. The plasma generating voltage generates an ion plasma out of a gas in the chamber. The ion plasma is maintained transient which allows for better control of its energy. A portion of a wafer stand is pulsed with a small voltage which extracts and accelerates ions out of the plasma into a silicon dioxide gate dielectric layer formed on a wafer in the chamber.

Abstract: A method of removing a photoresist layer on a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. A dry stripping process is performed to remove the photoresist layer on the semiconductor wafer. The semiconductor wafer is then placed on a rotator of a wet clean chamber and horizontally rotated. A first cleaning process is performed to remove polymers and organic components on a surface of the semiconductor wafer. Then a second cleaning process is performed as well to remove polymers and particles on the surface of the semiconductor wafer. By performing a third cleaning process, a first cleaning solution employed in the first cleaning process and a second cleaning solution employed in the second cleaning process are removed from the surface of the semiconductor wafer. Finally, the semiconductor wafer is spun dry at the end of the method.

Abstract: After forming a conductive layer on the entire surface of an insulation substrate, a resin mask of poly lactic acid etc. resin which will hydrolyze in an alkali aqueous solution is integrally formed on the insulation substrate so that a part to which a conductive layer of a predetermined pattern is to be formed is exposed. Then, a conductive layer is overlaid on the part exposed from the resin mask by means of electrolytic plating using an acidic bath composition. The interface between the resin mask of poly lactic acid etc. resin and the conductive layer reproduces an accurate contour of the pattern. Thereafter, the resin mask is efficiently removed by hydrolysis using an alkali aqueous solution, and finally the conductive layer is removed by chemical etching to thereby form a conductive layer having the predetermined pattern on the surface of the insulation substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer; decreasing the hydrophilic properties of a first portion of the dielectric layer, forming an opening through the dielectric layer, and filling the opening with metal to form a first metal feature. The hydrophilic properties of the first portion are lesser than a second portion of the dielectric layer. The hydrophilic properties of the first portion can be decreased by doping the first portion with hydrogen using ion implantation or plasma etching. An upper surface of the dielectric layer can also be roughened during the process of hydrogen doping. A semiconductor device produced by the method of manufacturing is also disclosed.

Abstract: There is provided a wafer transfer method, by which, when a wafer is loaded into a system, heat shock applied to the wafer can be relieved, the frequency of occurrence of crystal dislocation such as slip can be decreased, and productivity can be improved due to saving of energy and time required for heating and cooling of the system, and there is also provided a wafer support member used for this method. In this method, a step for transferring wafers so as to replace a wafer, which finishes its thin film growth process, with a following wafer, which is to be subjected to its thin film growth process, is carried out under the temperature being higher than the room temperature, while the wafer 1 is transferred integrally with a wafer support member 2 used for the thin film growth process.

Abstract: A layer of doped oxide glass is deposited on a semiconductor device in a chemical vapor deposition chamber by reacting gaseous sources of silicon, ozone and at least one boron or phosphorus dopant in a carrier gas, the ozone being present in a ratio of about 9-15 weight percent of the carrier gas. The deposited layer of doped oxide glass contains no greater than about 4 weight percent each of boron and phosphorus concentration and is annealed at a temperature no greater than about 700° C. for a time sufficient to soften and outgas any residual moisture in the oxide glass layer and level the upper surface to a desired degree.

Abstract: A semiconductor device formed on a substrate includes at least one metal stack formed on the substrate. A fluorosilicate glass layer is formed on the at least one metal stack, where the fluorosilicate glass layer acts as an interlayer dielectric for the semiconductor device. The fluorosilicate glass layer includes a fluorine-depleted layer at a top portion of the fluorosilicate glass layer that is further away from the substrate. The fluorine-depleted layer is formed by treating the fluorosilicate glass layer with a hydrogen plasma, such as an H2/N2 plasma. The fluorine-depleted layer lessens a likelihood of fluorine atoms in the fluorosilicate glass layer from moving into and thereby corrupting a conducting layer formed above the fluorosilicate glass layer.

Abstract: A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.

Abstract: The present invention provides an apparatus for liquid phase deposition, comprising: a saturation reaction system, including a mixture trough, at least two supply devices for raw materials, a stirrer device, a filter device, and valve control devices; a steady-flow over-saturation loop reaction system, including an over-saturation reaction trough, at least one liquid level control trough, at least two supply devices for raw materials, a stirrer device, a filter device, and valve control devices; an automatic solution concentration monitoring system, for controlling the reactant concentrations; and a waste liquid recycling system, comprising at least two storage troughs, a recycled waste liquid level sensor, a recycled waste liquid sensor, and valve control devices.

Abstract: A method for depositing a layer over a substrate includes depositing a first halogen-doped borophosphosilicate glass (BPSG) layer over said substrate at a first pressure level. A second halogen-doped BPSG layer is deposited over said first layer at a second pressure level, wherein said first pressure level is higher than said second pressure level.

Abstract: A method and apparatus for mechanically and/or chemical-mechanically planarizing microelectronic substrates. In one embodiment in accordance with the principles of the present invention, a microelectronic substrate is planarized or polished on a planarizing medium having a thin film and a plurality of micro-features on the film. The film may be an incompressible sheet or web substantially impervious to a planarizing solution, and the micro-features may be configured in a selected pattern on the film to restrain fluid flow of the planarizing solution across the surface of the film under the substrate. The micro-features, for example, may be configured in a selected pattern that has a plurality of support points and at least one cavity to entrap a substantially contiguous, uniform distribution of the solution under the substrate during planarization.

Abstract: A method of forming a silicon oxide layer of a semiconductor device comprising coating a spin-on glass (SOG) composition including perhydropolysilazane having a compound of the formula (SiH2NH2)n where n represents a positive integer on a semiconductor substrate having a surface discontinuity, to form a planar SOG layer; and forming a silicon oxide layer with a planar surface by implementing a first heat treatment to convert an SOG solution into oxide and a second heat treatment to densify thus obtained oxide. The silicon oxide layer of the present invention can bury a gap between gaps of VLSI having a high aspect ratio and gives the same characteristics as a CVD oxide layer. Further, the oxidation of silicon in the active region is restrained in the present invention to secure dimension stability. Also disclosed is a semiconductor device made by the method.

Abstract: Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer.

Abstract: A method of anastomosing two hollow bodily organs using a bioadhesive. The method involves apposing apertures in the organs to be joined and applying the bioadhesive, thereby joining the apertures in the organs and allowing movement of fluid or semi-solid material from one of the two organs to the second organ. The invention also relates to a device for anastomosing two hollow organs. The device has two inflatable balloons, one of which is placed into the lumen each of the two organs to be joined. Inflation of the balloons holds the apertures together while the bioadhesive is applied. The device allows anastomosis of blood vessels through endoscopic means.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: A method and apparatus for reducing oxide traps within a silicon oxide film by incorporating a selected level of fluorine in the silicon oxide film. The method includes the steps of distributing a fluorine source to a processing chamber at a selected rate with the rate being chosen according to the desired level of fluorine to be incorporated into the film, flowing a process gas including a silicon source, an oxygen source and the fluorine source into the processing chamber, and maintaining a deposition zone within the chamber at processing conditions suitable to deposit a silicon oxide film having the selected level of fluorine incorporated into the film over a substrate disposed in the chamber. In a preferred embodiment, the selected level of fluorine incorporated into the film is between 1×1020 atoms/cm3 and 1×1021 atoms/cm3. In another preferred embodiment the silicon oxide film is deposited as a first layer of a composite layer premetal dielectric film.

Abstract: A step mask having a plurality of test cells and a method for producing the same. Each test cell of the step mask is etched for a different amount of time and therefore has a different etch depth or height. The number of phase shifter layer etch iterations can be conducted on a column-by-column and row-by-row basis to decrease the number of etch iterations.

Abstract: A photosensitive film pattern formed through only one photolithography step and having difference in film thickness is formed utilizing difference in amount of light emitted to the photosensitive film on a film to be etched, and the film to be etched is etched two times to form plural patterns therein by utilizing the difference in film thickness of the photosensitive film pattern, thereby reducing the number of whole manufacturing process steps. In this case, at the time of etching and removing thin photosensitive film out of the photosensitive film pattern, the upper layer of thick photosensitive film out of the photosensitive film pattern has already been modified to a silica film nearly free from being affected by dry-etching, and therefore, the thick photosensitive film can maintain its planar shape nearly equal to that of the thick photosensitive film before etching the thin photosensitive film.

Abstract: Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Abstract: A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

Abstract: The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some of the evaporated aluminum oxide and silicon monoxide is deposited on a substrate to form the silicon-doped aluminum oxide on the substrate. The invention also encompasses methods of forming transistors and flash memory devices.

Abstract: A semiconductor wiring structure positioned between plurality conductors, comprisies spacers positioned on adjacent ones of the conductors and at least one wiring element positioned between the spacers.

Abstract: A film of fluorine-doped silicon glass (“FSG”) is exposed to a nitrogen-containing plasma to nitride a portion of the FSG film. In one embodiment, the FSG film is chemically-mechanically polished prior to nitriding. The nitriding process is believed to scavenge moisture and free fluorine from the FSG film. The plasma can heat the FSG film to about 400° C. for about one minute to incorporate about 0.4 atomic percent nitrogen to a depth of nearly a micron. Thus, the nitriding process can passivate the FSG film deeper than a via depth.

Abstract: The present invention provides a heat treatment apparatus capable of forming a uniform thin layer on the substrate provided with a furnace core pipe, a substrate supporting boat for supporting a lot of substrates disposed in the furnace core pipe and a process gas injector pipe having many blowing holes for spouting the process gas toward the substrate, the supporting boat having a rotation mechanism to rotate around the normal line passing through one principal face of the substrate as a rotation axis. In the apparatus, an inert gas injector pipe has the same number of inert gas or nitrogen gas blowing holes as the number of process gas blowing holes and is provided at an approximately symmetrical position relative to the center line of the rotation axis.

Abstract: A method of formation of a damascene FSG film with good adhesion to silicon nitride in an HDP-CVD system. Silane (SiH4), silicon tetrafluoride (SiF4), oxygen (O2) and argon (Ar) are used as the reactant gases. SiH4, SiF4, and O2 react to form the FSG. Ar is introduced to promote gas dissociation. All four gases are used for depositing most of the FSG film. SiH4 is not used during deposition of the interfacial part of the FSG film. The interfacial part of the FSG film refers either to the topmost portion, if silicon nitride is to be deposited on top of the FSG or the bottom portion if the FSG is to be deposited on top of silicon nitride. Using SiH4 with the SiF4 tends to mitigate the destructive effects of SiF4 throughout most of the deposition. By removing the SiH4 from the deposition of the interfacial part of the FSG film less hydrogen is incorporated into the film in the interfacial region and adhesion to overlying or underlying silicon nitride is improved.

Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.