Tertiary Silicon Containing Compound Formation (e.g., Oxynitride Formation, Etc.) Patents (Class 438/786)
  • Patent number: 10490400
    Abstract: There is provided a technique that includes forming a nitride film on a pattern including a concave portion formed in a surface of a substrate by repeating a cycle. The cycle includes non-simultaneously performing: (a) forming a first layer by supplying a precursor gas to the substrate; (b) forming an NH-terminated second layer by supplying a hydrogen nitride-based gas to the substrate to nitride the first layer; and (c) modifying a part of the NH termination to an N termination, and maintaining another part of the NH termination as it is without modifying the another part to the N termination by plasma-exciting and supplying a nitrogen gas to the substrate, wherein in (c), an N termination ratio in an upper portion of the concave portion of the pattern is made higher than an N termination ratio in a lower portion of the concave portion of the pattern.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: November 26, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Katsuyoshi Harada, Satoshi Shimamoto
  • Patent number: 10259044
    Abstract: The present disclosure provides three-dimensional (3D) printing processes, apparatuses, software, and systems for the production of at least one desired 3D object. The 3D printer system (e.g., comprising a processing chamber, build module, or an unpacking station) described herein may retain a desired (e.g., inert) atmosphere around the material bed and/or 3D object at multiple 3D printing stages. The 3D printer described herein comprises one or more build modules that may have a controller separate from the controller of the processing chamber. The 3D printer described herein comprises a platform that may be automatically constructed. The invention(s) described herein may allow the 3D printing process to occur for a long time without operator intervention and/or down time.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 16, 2019
    Assignee: VELO3D, INC.
    Inventors: Benyamin Buller, Zachary Ryan Murphree, Richard Joseph Romano, Thomas Blasius Brezoczky, Alan Rick Lappen
  • Patent number: 10141284
    Abstract: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignee: IMEC vzw
    Inventors: Soon-Wook Kim, Lan Peng, Patrick Verdonck, Robert Miller, Gerald Peter Beyer, Eric Beyne
  • Patent number: 9972598
    Abstract: Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: May 15, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Yagyu
  • Patent number: 9611544
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 4, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Mandyam Sriram
  • Patent number: 9478421
    Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 25, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher Dennis Bencher, Daniel Lee Diehl, Huixiong Dai, Yong Cao, Tingjun Xu, Weimin Zeng, Peng Xie
  • Patent number: 9425325
    Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: August 23, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
  • Patent number: 9285168
    Abstract: A substrate processing system that has a plurality of deposition chambers, and one or more robotic arms for moving a substrate between one or more of a deposition chamber, load lock holding area, and a curing and treatment module. The substrate curing and treatment module is attached to the load-lock substrate holding area, and may include: The curing chamber for curing a dielectric layer in an atmosphere comprising ozone, and a treatment chamber for treating the cured dielectric layer in an atmosphere comprising water vapor. The chambers may be vertically aligned, have one or more access doors, and may include a heating system to adjust the curing and/or heating chambers between two or more temperatures respectively.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 15, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Dmitry Lubomirsky, Jay D. Pinson, II, Kirby H. Floyd, Adib Khan, Shankar Venkataraman
  • Patent number: 9209262
    Abstract: This silicon carbide semiconductor device includes: a silicon carbide semiconductor layer; a gate insulating layer which is arranged over the silicon carbide semiconductor layer and which includes a silicon oxide film; a gate electrode which is arranged on the gate insulating layer; and a carbon transition layer which is interposed between the silicon carbide semiconductor layer and the silicon oxide film and which has a carbon atom concentration is 10% to 90% of a carbon atom concentration of the silicon carbide semiconductor layer. In a region of the carbon transition layer which is located closer to the silicon oxide film than a position where a nitrogen atom concentration becomes the highest is, a ratio of an integral of nitrogen atom concentrations to an integral of carbon atom concentrations is equal to or greater than 0.11.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 8, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Koutarou Tanaka, Masao Uchida, Masahiko Niwayama, Osamu Kusumoto
  • Patent number: 9177918
    Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Hui-Chun Yang
  • Patent number: 9171720
    Abstract: Methods of treating the surface of a metal-containing hardmask used in the manufacture of semiconductors by contacting the hardmask surface with a composition capable of adjusting the water contact angle so as to substantially match that of subsequently applied organic coatings are provided.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: October 27, 2015
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Deyan Wang, Peter Trefonas, III, Jieqian Zhang, Peng-Wei Chuang
  • Patent number: 9147685
    Abstract: A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: September 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungmun Byun, Hyongsoo Kim, Mansug Kang, Eunkee Hong
  • Patent number: 9111749
    Abstract: The negative effect of oxygen on some metal films can be reduced or prevented by contacting the films with a treatment agent comprising silane or borane. In some embodiments, one or more films in an NMOS gate stack are contacted with a treatment agent comprising silane or borane during or after deposition.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: August 18, 2015
    Assignee: ASM IP HOLDINGS B.V.
    Inventors: Eric Shero, Suvi Haukka
  • Patent number: 9111783
    Abstract: Replacement metal gates well suited for self-aligned contact formation are made by replacing the dummy gate with a recessed polysilicon layer and then effecting an aluminum-polysilicon substitution. The resulting upper polysilicon layer is easily removed from the recessed aluminum layer, which can then be protected with a protective dielectric layer for subsequent formation of a source or drain contact hole.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 18, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenzo Manabe
  • Patent number: 9082719
    Abstract: Embodiments provide a method for removing a dielectric layer from a bottom of a trench while maintaining the dielectric layer on sidewalls of the trench. The method includes etching the dielectric layer at the bottom of the trench and generating a passivation layer on the dielectric layer at an upper portion of the trench by adjusting the conditions of a plasma etch process to a first mode; and a step of etching the dielectric layer at the bottom of the trench and etching the passivation layer at the upper portion of the trench by adjusting the conditions of the plasma etch process to a second mode before the dielectric layer at the bottom of the trench is completely removed.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: July 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Lothar Brencher, Carsten Moritz
  • Patent number: 9070554
    Abstract: A method of manufacturing a semiconductor device includes supplying a precursor gas to a substrate; supplying a reaction gas to a plasma generation region; supplying high frequency power to the plasma generation region; and generating plasma of the reaction gas by adjusting a pressure of the plasma generation region to a first pressure before the reaction gas is supplied and adjusting the pressure of the plasma generation region to a second pressure lower than the first pressure while the reaction gas and the high frequency power are supplied.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: June 30, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuyuki Toyoda, Yukitomo Hirochi, Tetsuo Yamamoto, Kazuhiro Morimitsu, Tadashi Takasaki
  • Publication number: 20150140839
    Abstract: Provided is a substrate processing apparatus, which comprises a process chamber configured to process a substrate, a first plasma generation chamber in the process chamber, a first reactive gas supply unit configured to supply first reactive gas into the first plasma generation chamber, a pair of first discharge electrodes configured to generate plasma and to excite the first reactive gas, a first gas ejection port installed in a side wall of the first plasma generation chamber to eject an active species toward the substrate, a second plasma generation chamber in the process chamber, a second reactive gas supply unit configured to supply second reactive gas into the second plasma generation chamber, a pair of second discharge electrodes configured to generate plasma and to excite the second reactive gas, and a second gas ejection port installed in a side wall of the second plasma generation chamber to eject an active species.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 21, 2015
    Inventors: Tetsuo Yamamoto, Naoki Matsumoto, Koichi Honda
  • Publication number: 20150118865
    Abstract: A method for forming a silicon oxycarbonitride film includes supplying a gas containing a silicon precursor having an oxygen-containing group onto a process surface of a workpiece, supplying a gas containing a carbon precursor onto the process surface, and supplying a nitriding gas onto the process surface subjected to the supplying a gas containing a silicon precursor and the supplying a gas containing a carbon precursor. The silicon oxycarbonitride film is formed on the process surface by the supplying the gas containing the silicon precursor, the supplying gas containing the carbon precursor and the supplying a nitriding gas without performing an oxidation process.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventor: Akira SHIMIZU
  • Patent number: 9018104
    Abstract: There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: April 28, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Kenji Kanayama, Norikazu Mizuno, Yushin Takasawa, Yosuke Ota
  • Publication number: 20150111394
    Abstract: Embodiments of mechanisms for forming a film deposition tool are provided. The film deposition tool includes a plasma source and a substrate processing region connected to the plasma source. The film deposition tool also includes a pedestal for supporting a substrate in the substrate processing region, wherein the substrate is prepared to be deposited with a film. The film deposition tool further includes electrodes embedded in the pedestal and separated from each other. The film deposition tool also includes a direct current bias system having variable voltage sources. The variable voltage sources are electrically connected to the electrodes, respectively, for providing direct current voltages to the electrodes independently.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao HSU, Yu-Li CHANG, Chia-I SHEN
  • Patent number: 9006051
    Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Masayuki Kajiwara, Masataka Nakada, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 8999805
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.
    Type: Grant
    Filed: October 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8993460
    Abstract: Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing film-precursor and an organometallic ligand transfer reagent into a processing chamber, adsorbing the silicon-containing film-precursor, the organometallic ligand transfer reagent, or both onto a surface of a semiconductor substrate under conditions whereby either or both form an adsorption-limited layer, and reacting the silicon-containing film-precursor with the organometallic ligand transfer reagent, after either or both have formed the adsorption-limited layer. The reaction results in the forming of the film layer. In some embodiments, a byproduct is also formed which contains substantially all of the metal of the organometallic ligand transfer reagent, and the methods may further include removing the byproduct from the processing chamber. Also disclosed herein are semiconductor processing apparatuses for forming SiC/SiCN film layers.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Novellus Systems, Inc.
    Inventor: Adrien LaVoie
  • Publication number: 20150087139
    Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below: In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 26, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Mark Leonard O'Neill, Manchao Xiao, Xinjian Lei, Richard Ho, Haripin Chandra, Matthew R. MacDonald, Meiliang Wang
  • Patent number: 8986921
    Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Bryan G. Morris, Tuan A. Vo, Christopher J. Waskiewicz, Yunpeng Yin
  • Patent number: 8980715
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Publication number: 20150072537
    Abstract: A method of manufacturing a semiconductor device, includes: forming a thin film containing silicon, oxygen and carbon or a thin film containing silicon, oxygen, carbon and nitrogen on a substrate by performing a cycle a predetermined number of times.
    Type: Application
    Filed: March 27, 2014
    Publication date: March 12, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takaaki NODA, Satoshi SHIMAMOTO, Shingo NOHARA, Yoshiro HIROSE, Kiyohiko MAEDA
  • Publication number: 20150056540
    Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 26, 2015
    Inventor: Hideaki Fukuda
  • Patent number: 8951903
    Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dan Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
  • Patent number: 8951919
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a specific element, oxygen, carbon, and nitrogen by performing a cycle a predetermined number of times. The cycle includes supplying a specific element-containing gas, supplying a carbon-containing gas, supplying an oxidizing gas, and supplying a nitriding gas. The act of supplying the nitriding gas is performed before the act of supplying the specific element-containing gas, and the act of supplying the carbon-containing gas and the act of supplying the oxidizing gas are not performed until the act of supplying the specific element-containing gas is performed.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: February 10, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshinobu Nakamura
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Publication number: 20150021775
    Abstract: A method for manufacturing a semiconductor device for forming a metal element-containing layer on an insulating layer in which a concave portion is formed, includes: forming an oxide layer including mainly an oxide of the metal element on the insulating layer including the concave portion; and forming a silicate layer including mainly a silicate of the metal element by making the oxide layer into silicate by annealing under a reducing atmosphere.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Inventors: Kenji MATSUMOTO, Tatsufumi HAMADA, Kaoru MAEKAWA
  • Patent number: 8927442
    Abstract: A structure and method for fabricating an improved SiCOH hardmask with graded transition layers having an improved profile for forming sub-20 nm back end of the line (BEOL) metallized interconnects are provided. In one embodiment, the improved hardmask may be comprised of five layers: an oxide adhesion layer, a graded transition layer, a dielectric layer, an inverse graded transition layer, and an oxide layer. In another embodiment, the improved hardmask may be comprised of four layers; an oxide adhesion layer, a graded transition layer, a dielectric layer, and an oxide layer. In another embodiment, a method of forming an improved hardmask may comprise a continuous five step plasma enhanced chemical vapor deposition (PECVD) process utilizing a silicon precursor, a porogen, and oxygen. In yet another embodiment, a method of forming an improved hardmask may comprise a continuous four step PECVD process utilizing a silicon precursor, a porogen, and oxygen.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Yannick S. Loquet, Yann A. Mignot, Son V. Nguyen, Muthumanickam Sankarapandian, Hosadurga Shobha
  • Publication number: 20150004805
    Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Thomas R. Omstead, Cole S. Franklin
  • Publication number: 20150001681
    Abstract: A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Chen-Fa Lu, Yeur-Luen Tu, Shu-Ju Tsai, Cheng-Ta Wu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20140363985
    Abstract: Provided are a novel amino-silyl amine compound, a method for preparing the same, and a silicon-containing thin-film using the same, wherein the amino-silyl amine compound has thermal stability and high volatility and is maintained in a liquid state at room temperature and under a pressure where handling is easy to thereby form a silicon-containing thin-film having high purity and excellent physical and electrical properties by various deposition methods.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: Se Jin Jang, Sang Do Lee, Sung Gi Kim, Jong Hyun Kim, Byeong IL Yang, Jang Hyeon Seok, Sang Ick Lee, Myong Woon Kim
  • Patent number: 8906455
    Abstract: This invention discloses the method of forming silicon nitride, silicon oxynitride, silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxide and carbon-doped oxynitride films at low deposition temperatures. The silicon containing precursors used for the deposition are monochlorosilane (MCS) and monochloroalkylsilanes. The method is preferably carried out by using plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced cyclic chemical vapor deposition.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 9, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Liu Yang, Xinjian Lei, Bing Han, Manchao Xiao, Eugene Joseph Karwacki, Jr., Hansong Cheng
  • Patent number: 8901556
    Abstract: In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm2 and lower than or equal to 0.5 W/cm2 is supplied to an electrode provided in the treatment chamber.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Toshinari Sasaki, Shuhei Yokoyama, Takashi Hamochi
  • Publication number: 20140349492
    Abstract: A semiconductor device manufacturing method includes forming a thin film containing silicon, oxygen, carbon and a specified Group III or Group V element on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas containing silicon, carbon and a halogen element and having an Si—C bonding and a first catalytic gas to the substrate; supplying an oxidizing gas and a second catalytic gas to the substrate; and supplying a modifying gas containing the specified Group III or Group V element to the substrate.
    Type: Application
    Filed: March 31, 2014
    Publication date: November 27, 2014
    Applicant: C/O HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi SHIMAMOTO, Yoshiro HIROSE, Atsushi SANO, Tsukasa KAMAKURA, Takaaki NODA
  • Patent number: 8895388
    Abstract: An object is to provide a technique for manufacturing an insulating layer with favorable withstand voltage. Another object is to provide a technique for manufacturing a semiconductor device having an insulating layer with favorable withstand voltage. By subjecting a semiconductor layer or semiconductor substrate mainly containing silicon to a high density plasma treatment, an insulating layer is formed on a surface of the semiconductor layer or a top surface of the semiconductor substrate. At this time, the high density plasma treatment is performed by switching a supply gas in the middle of the treatment from a gas containing a rare gas, oxygen, and hydrogen, to a gas containing a rare gas and oxygen.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Tomokazu Yokoi
  • Patent number: 8895456
    Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Tachibana, Hiroaki Ikegawa, Yu Wamura, Muneyuki Otani, Jun Ogawa, Kosuke Takahashi
  • Patent number: 8889567
    Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Hui-Chun Yang
  • Patent number: 8871655
    Abstract: The method of forming a silicon oxycarbonitride film on a base includes stacking a silicon carbonitride film and a silicon oxynitride film on the base to form the silicon oxycarbonitride film.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Suzuki, Kentaro Kadonaga, Byoung Hoon Lee, Eun Jo Lee, Sung Duk Son, Jae Hyuk Jang, Do Hyun Park
  • Publication number: 20140315393
    Abstract: A method of manufacturing a semiconductor device includes: pre-treating a surface of a substrate by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in a process chamber under a pressure less than atmospheric pressure; and forming a film on the pre-treated substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas to the substrate in the process chamber; and supplying a reaction gas to the substrate in the process chamber.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 23, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takashi OZAKI, Hideki HORITA
  • Publication number: 20140302689
    Abstract: Methods for depositing flowable dielectric films are provided. In some embodiments, the methods involve introducing a silicon-containing precursor to a deposition chamber wherein the precursor is characterized by having a partial pressure:vapor pressure ratio between 0.01 and 1. In some embodiments, the methods involve depositing a high density plasma dielectric film on a flowable dielectric film. The high density plasma dielectric film may fill a gap on a substrate. Also provided are apparatuses for performing the methods.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 9, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
  • Publication number: 20140302688
    Abstract: Methods are described for forming a dielectric layer on a patterned substrate. The methods may include combining a silicon-and-carbon-containing precursor and a radical oxygen precursor in a plasma free substrate processing region within a chemical vapor deposition chamber. The silicon-and-carbon-containing precursor and the radical oxygen precursor react in to deposit a flowable silicon-carbon-oxygen layer on the patterned substrate. The resulting film possesses a low wet etch rate ratio relative to thermal silicon oxide and other standard dielectrics.
    Type: Application
    Filed: July 3, 2013
    Publication date: October 9, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Brian Saxton Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8846550
    Abstract: The negative effect of oxygen on some metal films can be reduced or prevented by contacting the films with a treatment agent comprising silane or borane. In some embodiments, one or more films in an NMOS gate stack are contacted with a treatment agent comprising silane or borane during or after deposition.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Eric Shero, Suvi Haukka
  • Publication number: 20140287596
    Abstract: A method of manufacturing a semiconductor device including forming a thin film containing silicon, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a precursor gas containing silicon, carbon and a halogen element and having an Si—C bonding, and a first catalytic gas to the substrate; and supplying an oxidizing gas and a second catalytic gas to the substrate.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 25, 2014
    Applicants: L'AIR LIQUIDE, SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDE, HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshiro HIROSE, Norikazu MIZUNO, Kazutaka YANAGITA, Shingo OKUBO