Tertiary Silicon Containing Compound Formation (e.g., Oxynitride Formation, Etc.) Patents (Class 438/786)
  • Publication number: 20100240225
    Abstract: Disclosed is a microwave plasma processing apparatus (100) that generates a plasma of a processing gas in a chamber (1) by microwaves radiated from microwave radiating holes (32) of a plane antenna (31) and transmitted through a microwave-transmissive plate (28), thereby to carry out plasma processing of a processing object with the plasma. The microwave-transmissive plate (28) has a microwave transmitting surface having a recessed/projected area (42) in an area corresponding to a peripheral region of the processing object, and having a flat area (43) in an area corresponding to a central region of the processing object (W).
    Type: Application
    Filed: June 10, 2008
    Publication date: September 23, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Yoshihiro Sato, Takashi Kobayashi, Toshihiko Shiozawa, Daisuke Tamura
  • Patent number: 7799669
    Abstract: A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 21, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
  • Patent number: 7799668
    Abstract: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: September 21, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Luigi Colombo, James J. Chambers
  • Publication number: 20100233886
    Abstract: Described herein are methods of forming dielectric films comprising silicon, such as, but not limited to, silicon oxide, silicon oxycarbide, silicon carbide, and combinations thereof, that exhibit at least one of the following characteristics: low wet etch resistance, a dielectric constant of 6.0 or below, and/or can withstand a high temperature rapid thermal anneal process. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 16, 2010
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Liu Yang, Manchao Xiao, Kirk Scott Cuthill, Bing Han, Mark Leonard O'Neill
  • Publication number: 20100233887
    Abstract: A production method for a semiconductor device comprising the first step of supplying a first reaction material to a substrate housed in a processing chamber to subject to a ligand substitution reaction a ligand as a reaction site existing on the surface of the substrate and the ligand of the first reaction material, the second step of removing the excessive first reaction material from the processing chamber, the third step of supplying a second reaction material to the substrate to subject a ligand substituted by the first step to a ligand substitution reaction with respect to a reaction site, the fourth step of removing the excessive second reaction material from the processing chamber, and a fifth step of supplying a third reaction material excited by plasma to the substrate to subject a ligand, not subjected to a substitution reaction with respect to a reaction site in the third step, to a ligand substitution reaction with respect to a reaction site, wherein the steps 1-5 are repeated a specified number
    Type: Application
    Filed: May 27, 2010
    Publication date: September 16, 2010
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Hironobu Miya, Kazuyuki Toyoda, Norikazu Mizuno, Taketoshi Sato, Masanori Sakai, Masayuki Asai, Kazuyuki Okuda, Hideki Horita
  • Patent number: 7790556
    Abstract: Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes, aid in reducing hydrogen content for a given deposition rate.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: September 7, 2010
    Assignee: ASM America, Inc.
    Inventors: Christophe F. Pomarede, Michael E. Givens, Eric J. Shero, Michael A. Todd
  • Patent number: 7790627
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7767590
    Abstract: A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one of the plurality of layers is a non-batch layer.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: August 3, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen Ming Chen, Lin Jun Wu
  • Publication number: 20100178758
    Abstract: The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 15, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jeng-Hwa Liao, Jung-Yu Hsieh, Ling-Wu Yang
  • Patent number: 7754622
    Abstract: Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: July 13, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe, Shigeru Nakajima, Yasushi Akasaka, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 7745349
    Abstract: A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: June 29, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong-Yel Jang
  • Patent number: 7732852
    Abstract: High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: June 8, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jiong-Ping Lu, Ming-Jang Hwang
  • Patent number: 7732324
    Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 8, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Ju-Ai Ruan, Sameer K. Ajmera, Changming Jin, Anand J. Reddy, Tae S. Kim
  • Patent number: 7718553
    Abstract: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: introducing into a reaction chamber a source gas of a silicon-containing hydrocarbon compound comprising in its molecule at least one Si—O bond and at least one bond selected from the group consisting of a Si—Si bond, Si—N bond, and Si—H bond; introducing into the reaction chamber an additive gas constituted by C, H, and optionally O; controlling a susceptor at a temperature of ?50° C. to 50° C.; forming by plasma reaction an insulation film constituted by Si, O, H, and optionally N on an irregular surface of a substrate at a deposition rate of 100 nm/min or less; and heat-treating the substrate with the insulation film, thereby increasing a density of the insulation film to more than 2.1 g/cm3 as a result of the heat treatment.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 18, 2010
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Nobuo Matsuki
  • Publication number: 20100120262
    Abstract: The present invention is a method to increase the intrinsic compressive stress in plasma enhanced chemical vapor deposition (PECVD) silicon nitride (SiN) and silicon carbonitride (SiCN) thin films, comprising depositing the film from an amino vinylsilane-based precursor. More specifically the present invention uses the amino vinylsilane-based precursor selected from the formula: [RR1N]xSiR3y(R2)z, where x+y+z=4, x=1-3, y=0-2, and z=1-3; R, R1 and R3 can be hydrogen, C1 to C10 alkane, alkene, or C4 to C12 aromatic; each R2 is a vinyl, allyl or vinyl-containing functional group.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 13, 2010
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Vasil Vorsa, Andrew David Johnson, Manchao Xiao
  • Publication number: 20100117240
    Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.
    Type: Application
    Filed: February 20, 2009
    Publication date: May 13, 2010
    Inventor: Mattia Cichocki
  • Patent number: 7709316
    Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: May 4, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Ren Wang, Ying-Wei Yen, Shu-Yen Chan, Kuo-Tai Huang
  • Patent number: 7709402
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. The HfSiON film may be formed by atomic layer deposition. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. The titanium nitride and the tantalum may be formed by atomic layer deposition.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7709403
    Abstract: A gate insulating film which is an oxide layer mainly made of SiO2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100° C. and lower than 1250° C., whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: May 4, 2010
    Assignee: Panasonic Corporation
    Inventors: Kenya Yamashita, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Masao Uchida, Ryoko Miyanaga
  • Patent number: 7704897
    Abstract: The present invention pertains to methods of depositing low stress/high index multi-layer films on a substrate using an HDP-CVD process. The multi-layer films include two lining layers and a bulk gap-fill layer and the HDP-CVD process employs a reduced substrate bias power during deposition of at least the second lining layer. Deposition of the three layers occurs at reduced deposition temperatures which further reduces the stress of the multi-layer film. The lower stress results in less defectivity which improves the films ability to maintain optical confinement of radiation.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 27, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Hemant P. Mungekar, Young S. Lee, Agnieszka Jakubowicz, Zhong Qiang Hua, Rionard Purnawan, Sanjay Kamath, Walter Zygmunt
  • Patent number: 7704894
    Abstract: This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer surface and significantly reduces the number of defects in the film, particularly for short temperature soaks.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 27, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jon Henri, Xingyuan Tang, Jason Tian, Kevin Gerber, Arul N. Dhas
  • Patent number: 7696108
    Abstract: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.
    Type: Grant
    Filed: December 9, 2007
    Date of Patent: April 13, 2010
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Chieh Wang, Jin-Tau Huang, Wei-Hui Hsu, Tse-Yao Huang
  • Patent number: 7682989
    Abstract: In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Laura M. Matz, Ting Y. Tsui, Thad E. Briggs, Robert Kraft
  • Patent number: 7678711
    Abstract: A SiO2 film is formed on a semiconductor substrate. Then, a SiN film is formed on the SiO2 film. In this event bis(tertiary butyl amino) silane and NH3 are used as a material gas, and the film forming temperature is set to 600° C. or lower.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Mitsuaki Hori, Hiroyuki Ohta, Katsuaki Ookoshi
  • Patent number: 7670963
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 2, 2010
    Assignee: Cypress Semiconductor Corportion
    Inventors: Krishnaswamy Ramkumar, Sagy Levy
  • Patent number: 7670965
    Abstract: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki
  • Patent number: 7666801
    Abstract: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include aminosilane ligands.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Timothy A. Quick
  • Patent number: 7659214
    Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a first wet process gas comprising water vapor into the process chamber, and reacting the substrate with the first wet process gas to grow an oxide film on the substrate. The method further includes flowing a second wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber, and reacting the oxide film and the substrate with the second wet process gas to grow an oxynitride film. In another embodiment, the method further comprises annealing the substrate containing the oxynitride film in an annealing gas. According to one embodiment of the method where the substrate is silicon, a silicon oxynitride film can be formed that exhibits a nitrogen peak concentration of approximately 3 atomic % or greater.
    Type: Grant
    Filed: September 30, 2007
    Date of Patent: February 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kimberly G. Reid, Anthony Dip
  • Patent number: 7659206
    Abstract: A method of treating a substrate comprises depositing silicon oxycarbide on the substrate and removing the silicon oxycarbide from the substrate. The silicon oxycarbide on the substrate is decarbonized by exposure to an energized oxygen-containing gas that heats the substrate and converts the layer of silicon oxycarbide into a layer of silicon oxide. The silicon oxide is removed by exposure to a plasma of fluorine-containing process gas. Alternatively, the remaining silicon oxide can be removed by a fluorine-containing acidic bath. In yet another version, a plasma of a fluorine-containing gas and an oxygen-containing gas is energized to remove the silicon oxycarbide from the substrate.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Krishna Vepa, Yashraj Bhatnagar, Ronald Rayandayan, Venkata Balagani
  • Patent number: 7651959
    Abstract: A method of forming a dielectric film includes: introducing a source gas essentially constituted by Si, N, H, and optionally C and having at least one bond selected from Si—N, Si—Si, and Si—H into a reaction chamber where a substrate is placed; depositing a silazane-based film essentially constituted by Si, N, H, and optionally C on the substrate by plasma reaction at ?50° C. to 50° C., wherein the film is free of exposure of a solvent constituted essentially by C, H, and optionally O; and heat-treating the silazane-based film on the substrate in a heat-treating chamber while introducing an oxygen-supplying source into the heat-treating chamber to release C from the film and increase Si—O bonds in the film.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: January 26, 2010
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Jeongseok Ha, Nobuo Matsuki
  • Patent number: 7646077
    Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 12, 2010
    Assignee: LSI Corporation
    Inventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay
  • Patent number: 7642203
    Abstract: Embodiments relate to a passivation layer for a semiconductor device that may be formed in a substrate having a plurality of semiconductor devices. The passivation layer may includes a first passivation layer, a second passivation layer, and a third passivation layer, and the passivation layer may have a laminated triple layer structure.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seung Hyun Kim
  • Patent number: 7642202
    Abstract: A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch of features such as vias in subsequent processing steps.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 5, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Ming Li, Bart Van Schravendijk, Tom Mountsier, Chiu Chi, Kevin Ilcisin, Julian Hsieh
  • Patent number: 7638442
    Abstract: A process for forming a silicon nitride layer on a gate oxide film as part of formation of a gate structure in a semiconductor device includes: forming a layer of silicon nitride on top of a gate oxide film on a semiconductor substrate by a nitridation process, heating the semiconductor substrate in an annealing chamber, exposing the semiconductor substrate to N2 in the annealing chamber, and exposing the semiconductor substrate to a mixture of N2 and N2O in the annealing chamber.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: December 29, 2009
    Assignee: ProMOS Technologies, Inc.
    Inventors: Cheng-Ta Wu, Da-Yu Chuang, Yen-Da Chen, Lihan Lin
  • Publication number: 20090305517
    Abstract: A method of manufacturing a semiconductor device has: carrying a substrate into a process chamber; depositing a thin film on the substrate by supplying inside the process chamber a first film deposition gas including at least one element among plural elements forming a thin film to be deposited and capable of accumulating a film solely and a second film deposition gas including at least another element among the plural elements and incapable of accumulating a film solely; carrying the substrate on which is deposited the thin film out from inside the process chamber; and removing a first sediment adhering to an interior of the process chamber and a second sediment adhering to an interior of the supply portion and having a chemical composition different from a chemical composition of the first sediment by supplying cleaning gases inside the process chamber and inside a supply portion that supplies the first film deposition gas while changing at least one of a supply flow rate, a concentration, and a type betwee
    Type: Application
    Filed: March 27, 2007
    Publication date: December 10, 2009
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Sadao Nakashima, Takahiro Maeda, Kiyohiko Maeda, Kenji Kameda, Yushin Takasawa
  • Patent number: 7622401
    Abstract: A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: November 24, 2009
    Assignee: Sony Corporation
    Inventor: Tomoyuki Hirano
  • Patent number: 7615500
    Abstract: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: November 10, 2009
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Kensuke Takano, Ichiro Yamamoto, Koji Watanabe
  • Publication number: 20090253272
    Abstract: A gate insulating film with less leakage current is formed, while a surface temperature of a silicon substrate is decreased. Gas containing oxygen atoms and nitrogen atoms is supplied into a processing chamber, then the gas containing the oxygen atoms and the nitrogen atoms is activated by plasma, and the silicon substrate is subjected to processing by plasma, and a silicon dioxide film containing nitrogen is formed.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 8, 2009
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Tadashi Terasaki
  • Patent number: 7585752
    Abstract: Chemical vapor deposition processes utilize chemical precursors that allow for the deposition of thin films to be conducted at or near the mass transport limited regime. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, a higher order silane is employed to deposit thin films containing silicon that are useful in the semiconductor industry in various applications such as transistor gate electrodes.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: September 8, 2009
    Assignee: ASM America, Inc.
    Inventors: Michael A. Todd, Mark Hawkins
  • Publication number: 20090215253
    Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.
    Type: Application
    Filed: August 22, 2008
    Publication date: August 27, 2009
    Inventors: Gurtej S. Sandhu, John T. Moore, Neal R. Rueger
  • Publication number: 20090215281
    Abstract: The present invention pertains to methods of depositing low stress/high index multi-layer films on a substrate using an HDP-CVD process. The multi-layer films include two lining layers and a bulk gap-fill layer and the HDP-CVD process employs a reduced substrate bias power during deposition of at least the second lining layer. Deposition of the three layers occurs at reduced deposition temperatures which further reduces the stress of the multi-layer film. The lower stress results in less defectivity which improves the films ability to maintain optical confinement of radiation.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: Applied Materials, Inc.
    Inventors: HEMANT P. MUNGEKAR, Young S. Lee, Agnieszka Jakubowicz, Zhong Qiang Hua, Rionard Purnawan, Sanjay Kamath, Walter Zygmunt
  • Patent number: 7579271
    Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: August 25, 2009
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ting Cheong Ang
  • Publication number: 20090203174
    Abstract: A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into a chamber to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface. After that, the supply of a monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the air to perform plasma treatment on a surface of the insulating film.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 13, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kenichi Okazaki, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Shunpei Yamazaki
  • Patent number: 7569495
    Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough H2 in the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the H2 in a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO2:H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by N2 annealing or Ar annealing.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: August 4, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae-Suk Lee
  • Patent number: 7569502
    Abstract: A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiOxNy gate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: August 4, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Olsen, Faran Nouri, Thai Cheng Chua
  • Patent number: 7560396
    Abstract: An electronic device material comprising at least an electronic device substrate and a silicon oxynitride film disposed on the substrate is provided. The silicon oxynitride film is characterized by containing nitrogen atoms in a large amount in the vicinity of the oxynitride film surface when the nitrogen content distribution in the thickness direction of the silicon oxynitride film is examined by SIMS (secondary ion mass spectrometry) analysis. By virtue of this constitution, an electronic device material comprising an oxynitride film having an excellent effect of preventing penetration of boron and having excellent gate leak properties can be obtained.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: July 14, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Sugawara, Shigenori Ozaki, Masaru Sasaki
  • Publication number: 20090170345
    Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
    Type: Application
    Filed: December 22, 2008
    Publication date: July 2, 2009
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naonori Akae, Yoshiro Hirose
  • Patent number: 7547952
    Abstract: The present invention generally is a method for forming a high-k dielectric layer, comprising depositing a hafnium compound by atomic layer deposition to a substrate, comprising, delivering a hafnium precursor to a surface of the substrate, reacting the hafnium precursor and forming a hafnium containing layer to the surface, delivering a nitrogen precursor to the hafnium containing layer, forming at least one hafnium nitrogen bond and depositing the hafnium compound to the surface.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 16, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Craig Metzner, Shreyas Kher, Yeong Kwan Kim, M. Noel Rocklein, Steven M. George
  • Patent number: 7534731
    Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form a processing ambient that reacts with the substrate such that an oxynitride film grows on the substrate. In yet another embodiment, the method further comprises flowing a diluting gas into the process chamber while flowing the wet process gas to control a growth rate of the oxynitride film. In another embodiment, the method further comprises annealing the substrate and the oxynitride film in an annealing gas. According to embodiments of the method where the substrate is silicon, a silicon oxynitride film forms that exhibits a nitrogen peak concentration of at least approximately 6 atomic % and an interface state density of less than approximately 1.5 ×10 12 per cc.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 19, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kimberly G. Reid, Anthony Dip
  • Patent number: RE41653
    Abstract: Disclosed herein is a method of forming a metal wiring of a semiconductor device.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: September 7, 2010
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Dong Joon Kim