Organic Reactant Patents (Class 438/789)
  • Patent number: 6734115
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: May 11, 2004
    Assignee: Applied Materials Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert P. Mandal, Shin-Puu Jeng, Kuo-Wei Liu, Yung-Cheng Lu, Michael Barnes, Ralf B. Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon
  • Patent number: 6730593
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: May 4, 2004
    Assignee: Applied Materials Inc.
    Inventors: Wai-Fan Yau, David Cheung, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Yu
  • Publication number: 20040082199
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.
    Type: Application
    Filed: August 26, 2003
    Publication date: April 29, 2004
    Applicant: Applied Materials, Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert P. Mandal, Shin-Puu Jeng, Kuo-Wei Liu, Yung-Cheng Lu, Michael Barnes, Ralf B. Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon
  • Publication number: 20040082193
    Abstract: A method of depositing a low dielectric constant film on a substrate. In one embodiment, the method includes the steps of positioning the substrate in a deposition chamber, providing a gas mixture to the deposition chamber, in which the gas mixture is comprised of one or more cyclic organosilicon compounds, one or more aliphatic compounds and one or more oxidizing gases. The method further includes reacting the gas mixture in the presence of an electric field to form the low dielectric constant film on the semiconductor substrate. The electric field is generated using a very high frequency power having a frequency in a range of about 20 MHz to about 100 MHz.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: Applied Materials, Inc
    Inventors: Juan Carlos Rocha-Alvarez, Maosheng Zhao, Ying Yu, Shankar Venkataraman, Srinivas D. Nemani, Li-Qun Xia
  • Patent number: 6727190
    Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: April 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Gurtej Sandhu, Ravi Iyer
  • Patent number: 6720276
    Abstract: Methods of forming a spin-on-glass (SOG) layer are disclosed. An SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: April 13, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-hee Cho, Chang-hyun Cho, Soo-ho Shin, Hong-sik Jeong
  • Patent number: 6716770
    Abstract: Organofluorosilicate glass films contain both organic species and inorganic fluorines, exclusive of significant amounts of fluorocarbon species. Preferred films are represented by the formula SivOwCxHyFz, where v+w+x+y+z=100%, v is from 10 to 35 atomic %, w is from 10 to 65 atomic % y is from 10 to 50 atomic %, x is from 1 to 30 atomic %, z is from 0.1 to 15 atomic %, and x/z is optionally greater than 0.25, wherein substantially none of the fluorine is bonded to the carbon. A CVD method includes: (a) providing a substrate within a vacuum chamber; (b) introducing into the vacuum chamber gaseous reagents including a fluorine-providing gas, an oxygen-providing gas and at least one precursor gas selected from an organosilane and an organosiloxane; and (c) applying energy to the gaseous reagents in the chamber to induce reaction of the gaseous reagents and to form the film on the substrate.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: April 6, 2004
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Mark Leonard O'Neill, Brian Keith Peterson, Jean Louise Vincent, Raymond Nicholas Vrtis
  • Patent number: 6713364
    Abstract: A method for fabricating an insulator on a semiconductor substrate such that the insulator has a low dielectric constant. A first interconnect and a second interconnect are configured on a semiconductor substrate. A conductive silicon is formed between the first interconnect and the second interconnect. The conductive silicon is anodically etched in a hydrofluoric-acid-containing electrolyte to convert the conductive silicon into porous silicon. The porous silicon is subsequently oxidized to form porous silicon oxide. With a dielectric constant of between 1.1 and 4, the porous silicon oxide has a lower dielectric constant than customary silicon oxide with 4.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: March 30, 2004
    Assignee: Infineon Technologies AG
    Inventor: Markus Kirchhoff
  • Patent number: 6709715
    Abstract: A method and apparatus for depositing a low dielectric constant film by plasma assisted copolymerization of p-xylylene and a comonomer having carbon-carbon double bonds at a constant RF power level from about 0W to about 100W or a pulsed RF power level from about 20W to about 160W. The copolymer film has a dielectric constant from about 2.2 to about 2.5. Preferred comonomers include tetravinyltetramethylcyclotetrasiloxane, tetraallyloxysilane, and trivinylmethylsilane. The copolymer films include at least 1% by weight of the comonomer.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: March 23, 2004
    Assignee: Applied Materials Inc.
    Inventors: Chi-I Lang, Shin-Puu Jeng, Yeming Jim Ma, Fong Chang, Peter Wai-Man Lee, David W. Cheung
  • Patent number: 6709983
    Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: March 23, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Satish Bedge
  • Publication number: 20040033702
    Abstract: A method of depositing a thin film on a substrate (2), including ablating a target (16) with a laser beam (12) to create a plume (19) of evaporants extending in a propagation direction away from the target surface (17). The laser beam is focussed a finite distance (d) before the target surface (17) and within the plume (19), thereby imparting increased energy to the evaporants within the plume (19). The target can also be rotated a hihg speed in order to impart a predetermined component of velocity to the evaporants which causes the slower moving evaporants to deflect from the propagation direction and are prevented from being deposited on the substrate. The method is useful in the formation of diamond film and has application in the fields of microchip manufacture, visual display units, solar energy conversion, optics, photonics, protective surfaces, medical uses, and cutting and drilling applications.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 19, 2004
    Inventors: Astghik Tamanyan, Grigori Tamanyan
  • Publication number: 20040022960
    Abstract: A dielectric film is prepared by a process comprising a) forming a film on a substrate by depositing a reactant gas containing a precursor of the dielectric film using plasma; b) stopping the reactant gas supply and continuing the plasma treatment to form a dielectric layer from the precursor film; and repeating the steps of a) and b) until a desired thickness of the film is obtained.
    Type: Application
    Filed: April 25, 2003
    Publication date: February 5, 2004
    Inventors: Shi-Woo Rhee, Chung Yi
  • Patent number: 6677231
    Abstract: A first dielectric layer 310 is formed on a substrate, wherein the first dielectric layer is a low-K material of an organic polymer. An adhesion promoter is then deposited on the first dielectric layer by chemical vapor deposition to form a first interlayer, wherein the first adhesion promoter is an organic material that comprises a C—H group and a siloxane (Si—O), such as methyltriacetoxysilane (MTAS). Next, an inorganic layer is formed on the first interlayer. Then the adhesion promoter mentioned previously is deposited on the inorganic layer by chemical vapor deposition to form a second interlayer. Next, a second dielectric layer is formed on the second interlayer 340, wherein the second interlayer is a low-K material of an organic polymer. Finally, a baking process is performed.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: January 13, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Chin-Hsiang Lin, Ming-Sheng Yang
  • Patent number: 6673725
    Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 6, 2004
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda
  • Patent number: 6667249
    Abstract: A method of coating a low dielectric constant material layer wherein the wafer surface is pre-wetted using a solvent to prevent or reduce coating defects is described. A semiconductor substrate is provided wherein a top surface of the semiconductor substrate may have surface defects. A solvent is coated overlying the top surface of the semiconductor substrate. A low dielectric constant material layer is coated overlying the solvent wherein the solvent covers the surface defects thereby preventing defects in the low dielectric constant material layer.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: December 23, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Hui Chen, Tien-I Bao, Yao-Yi Cheng
  • Publication number: 20030232495
    Abstract: One embodiment of the present invention is a method for fabricating a low-k dielectric film that includes steps of: (a) chemical vapor depositing a lower-k dielectric film; and (b) e-beam treating the lower-k dielectric film.
    Type: Application
    Filed: May 1, 2003
    Publication date: December 18, 2003
    Inventors: Farhad Moghadam, Jun Zhao, Timothy Weidman, Rick J. Roberts, Li-Qun Xia, Alexandros T. Demos
  • Patent number: 6660663
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10-250 W. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O, at an RF power level from about 10 to 200 W or a pulsed RF power level from about 20 to 250 W during 10-30% of the duty cycle.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: December 9, 2003
    Assignee: Applied Materials Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert R. Mandal
  • Patent number: 6660645
    Abstract: A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: December 9, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott A. Bell, Todd P. Lukanc, Christopher F. Lyons, Marina V. Plat, Ramkumar Subramanian
  • Patent number: 6656854
    Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate is provided. On the substrate, conductors spaced apart from one another are formed. Then, an insulating layer is formed on the conductors and the substrate. The insulating layer is formed by a chemical vapor deposition using tetramethylcyclotetrasiloxane as a source gas and oxygen as an adjunction gas. The chemical vapor deposition is performed while the substrate is irradiated by vacuum ultraviolet light. Finally, a part of the insulating layer is removed in a substantial uniform way to form a contact hole through the insulating film.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: December 2, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Junichi Miyano, Kiyohiko Toshikawa, Yoshikazu Motoyama
  • Patent number: 6653719
    Abstract: A siloxan polymer insulation film has a dielectric constant of 3.3 or lower and has —SiR2O— repeating structural units. The siloxan polymer has dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&bgr;CxHy (&agr;, &bgr;, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: November 25, 2003
    Assignee: ASM Japan K.K.
    Inventor: Nobuo Matsuki
  • Publication number: 20030215970
    Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Sung-Hoon Yang, Glenn A. Cerny, Kyuha Chung, Byung-Keun Hwang, Wan-Shick Hong
  • Patent number: 6649540
    Abstract: Methods for depositing a low-k dielectric film on the surfaces of semiconductors and integrated surfaces are disclosed. A substituted organosilane compound precursor is applied to the surface by chemical vapor deposition where it will react with the surface and form a film which will have a dielectric constant, K, less than 2.5.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: November 18, 2003
    Assignee: The BOC Group, Inc.
    Inventors: Qing Min Wang, Ce Ma
  • Patent number: 6645883
    Abstract: The present invention discloses a film forming method for forming an insulating film having a low dielectric constant. This method comprises the steps of adding at least one diluting gas of an inert gas and a nitrogen gas (N2) to a major deposition gas component consisting of siloxane and N2O, converting the resultant deposition gas into plasma, causing reaction in the plasma, and forming an insulating film 25,27, or 28 on a substrate targeted for film formation.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: November 11, 2003
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Youichi Yamamoto, Hiroshi Ikakura, Tomomi Suzuki, Yuichiro Kotake, Yoshimi Shioya, Kouichi Ohira, Shoji Ohgawara, Kazuo Maeda
  • Patent number: 6642157
    Abstract: There is provided the film forming method of forming the insulating film 204 containing silicon on the substrate 103 by plasmanizing the compound having the siloxane bonds and the oxidizing gas to react with each other.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: November 4, 2003
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Yuichiro Kotake, Youichi Yamamoto, Tomomi Suzuki, Hiroshi Ikakura, Shoji Ohgawara, Kouichi Ohira, Kazuo Maeda
  • Publication number: 20030203655
    Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:
    Type: Application
    Filed: March 28, 2003
    Publication date: October 30, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Gaku Sugahara, Nobuo Aoi, Koji Arai, Kazuyuki Sawada
  • Publication number: 20030203654
    Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
    Type: Application
    Filed: June 9, 2003
    Publication date: October 30, 2003
    Inventor: Ravi Iyer
  • Patent number: 6632735
    Abstract: A method of forming a carbon-doped silicon oxide layer is disclosed. The carbon-doped silicon oxide layer is formed by applying an electric field to a gas mixture comprising an organosilane compound and an oxidizing gas. The carbon-doped silicon oxide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the carbon-doped silicon oxide layer is used as an intermetal dielectric layer. In another integrated circuit fabrication process, the carbon-doped silicon oxide layer is incorporated into a damascene structure.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: October 14, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Wai-Fan Yau, Ju-Hyung Lee, Nasreen Gazala Chopra, Tzu-Fang Huang, David Cheung, Farhad Moghadam, Kuo-Wei Liu, Yung-Cheng Lu, Ralf B. Willecke, Paul Matthews, Dian Sugiarto
  • Patent number: 6632478
    Abstract: An embodiment of the present invention provides methods for forming a carbon-containing layer having a low dielectric constant and good gap-fill capabilities. A method includes depositing a carbon-containing layer on a substrate and transforming the carbon-containing layer to remove at least some of the carbon. The transforming step may include annealing the carbon-containing layer in a furnace containing a hydrogen atmosphere, for example. The carbon-containing layer may be a carbon-doped silicon oxide material, where the transforming step changes the carbon-doped silicon oxide. Additionally, the method may include subjecting the annealed layer to a hydrogen and/or low oxygen plasma treatment to further remove carbon from the layer. Additionally, a step of adding a capping layer to the annealed, plasma treated material is provided.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: October 14, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Frederic Gaillard, Li-Qun Xia, Jen Shu, Ellie Yieh, Tian-Hoe Lim
  • Patent number: 6632749
    Abstract: The method for manufacturing a silicon oxide film is characterized in that the method includes the steps of forming the silicon oxide film by a vapor deposition method or the like and of irradiating infrared light onto this silicon oxide film. Thus, according to the present invention, a silicon oxide film of relatively low quality formed at relatively low temperature can be improved to be a silicon oxide film of high quality. When the present invention is applied to a thin-film semiconductor device, a semiconductor device of high operational reliability and high performance can be manufactured.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: October 14, 2003
    Assignees: Seiko Epson Corporation, Mitsubishi Denki Kabushiki Kaisya
    Inventors: Mitsutoshi Miyasaka, Takao Sakamoto
  • Patent number: 6630413
    Abstract: Low hydrogen-content silicon nitride materials are deposited by a variety of CVD techniques, preferably thermal CVD and PECVD, using chemical precursors that contain silicon atoms, nitrogen atoms, or both. A preferred chemical precursor contains one or more N—Si bonds. Another preferred chemical precursor is a mixture of a N-containing chemical precursor with a Si-containing chemical precursor that contains less than 9.5 weight % hydrogen atoms. A preferred embodiment uses a hydrogen source to minimize the halogen content of silicon nitride materials deposited by PECVD.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: October 7, 2003
    Assignee: ASM Japan K.K.
    Inventor: Michael A. Todd
  • Patent number: 6627559
    Abstract: The present invention provides a coating film, which is not likely to cause cracks on the coated surface and is also capable of improving the resistance of the coated surface, especially oxidation resistance, corrosion resistance, and gas permeation resistance, a member provided with the coating film, and a method for producing the coating film. In the coating film of the present invention, a dense layer containing silicon dioxide as a principal component, which is obtained by heat-treating a solution containing perhydropolysilazane and polyorganosilazane, a ratio of the content of perhydropolysilazane to the total amount of polysilazane including perhydropolysilazane and polyorganosilazane being from 0.65 to 0.95, in air or air containing water vapor, was formed on the surface of a stainless steel plate.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: September 30, 2003
    Assignee: Contamination Control Services
    Inventor: Toyohiko Shindo
  • Patent number: 6627533
    Abstract: A method of manufacturing an insulating film in a semiconductor device is disclosed. The method comprises the steps of forming a SOD film on the entire structure to fill any distance between conductive layer patterns and after performing a curing process, forming a hard mask film on the SOD film, wherein the silicon oxide film is deposited by plasma deposition method using SiH4 and N2O as a reaction gas at a low-temperature and at a low-pressure and wherein in a stabilization step, the supply amount of SiH4 is greater than that of N2O and in a deposition step, the supply amount of N2O is greater than that of SiH4.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: September 30, 2003
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Sang Tae Ahn, Jung Gyu Song
  • Patent number: 6627532
    Abstract: A method for processing a substrate comprising depositing a dielectric layer comprising silicon, oxygen, and carbon on the substrate by chemical vapor deposition, wherein the dielectric layer has a carbon content of at least 1% by atomic weight and a dielectric constant of less than about 3, and depositing a silicon and carbon containing layer on the dielectric layer. The dielectric constant of a dielectric layer deposited by reaction of an organosilicon compound having three or more methyl groups is significantly reduced by further depositing an amorphous hydrogenated silicon carbide layer by reaction of an alkylsilane in a plasma of a relatively inert gas.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: September 30, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Frederic Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh, Wai-Fan Yau, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Lu
  • Patent number: 6627549
    Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: September 30, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 6624088
    Abstract: A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: September 23, 2003
    Assignee: Micron Technology, Inc.
    Inventor: John T. Moore
  • Publication number: 20030162410
    Abstract: A silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Tzu-Fang Huang, Yung-Cheng Lu, Li-Qun Xia, Ellie Yieh, Wai-Fan Yau, David W. Cheung, Ralf B. Willecke, Kuowei Liu, Ju-Hyung Lee, Farhad K. Moghadam, Yeming Jim Ma
  • Patent number: 6607790
    Abstract: The present invention relates to a plasma-enhanced chemical vapor deposition (PECVD) method of depositing a thin layer of a material, such as silicon dioxide, on the surface of a body, such as a semiconductor substrate. The method includes forming in a deposition chamber a plasma by means of two electrical power sources of different frequencies. A reaction gas is admitted into the deposition chamber and subjected to the plasma. The reaction gas is a mixture of tetraethylorthosilicate and a halogen gas, such as a gas of fluorine, chlorine or bromine. The reaction gas is reacted by the plasma to cause the material of the gas to deposit on the body which is within the chamber. This results in a deposited layer having a smoothly tapered surface even when the surface of the body possesses valleys and mesas, and thus prevents the formation of voids.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: August 19, 2003
    Assignee: Applied Materials, Inc.
    Inventor: Katsuyuki Musaka
  • Publication number: 20030143869
    Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.
    Type: Application
    Filed: January 25, 2002
    Publication date: July 31, 2003
    Inventors: Kevin J. Torek, Satish Bedge
  • Publication number: 20030143870
    Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.
    Type: Application
    Filed: May 7, 2002
    Publication date: July 31, 2003
    Inventors: Kevin J. Torek, Satish Bedge
  • Patent number: 6599847
    Abstract: A method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction, and an integrated circuit having formed therein the gap filling sandwich composite dielectric layer construction. To practice the method, there is first provided a substrate having formed thereover a patterned layer. There is then formed upon the patterned layer a first conformal dielectric layer through a first plasma enhanced chemical vapor deposition (PECVD) method employing a first radio frequency power optimized primarily to limit plasma induced damage to the substrate and the patterned layer. The first radio frequency power is also optimized secondarily to limit moisture permeation through the first conformal dielectric layer. There is then formed upon the first conformal dielectric layer a gap filling dielectric layer.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: July 29, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Syun-Ming Jang, Chen-Hua Yu
  • Patent number: 6596652
    Abstract: A method of forming a low dielectric constant film. The low dielectric constant film is formed by passing gaseous silane into a reaction chamber and performing a plasma chemical vapor deposition to form a carbon-rich layer. Micro-particles deposited on the dielectric film are purged by ammonia. By adjusting the flow rate of ammonia, and the pressure and plasma density inside the reaction chamber, several ammonium plasma conditions are produced in sequence to clear the particles on the dielectric film.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: July 22, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Ming-Sheng Yang
  • Patent number: 6596655
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10W to about 200W or a pulsed RF power level from about 20W to about 500W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: July 22, 2003
    Assignee: Applied Materials Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert P. Mandal, Shin-Puu Jeng, Kuo-Wei Liu, Yung-Cheng Lu, Michael Barnes, Ralf B. Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon
  • Patent number: 6589889
    Abstract: A process for forming a substantially planarized nanoporous dielectric silica coating on a substrate suitable for preparing a semiconductor device, and semiconductor devices produced by the methods of the invention. The process includes the steps of applying a composition that includes at least one silicon-based dielectric precursor to a substrate, and then, (a) gelling or aging the applied coating, (b) contacting the coating with a planarization object with sufficient pressure to transfer a planar impression to the coating without substantially impairing formation of desired nanometer-scale pore structure, (c) separating the planarized coating from the planarization object, (d) curing said planarized coating; wherein steps (a)-(d) are conducted in any one of the following sequences: (a), (b), (c) and (d); (a), (d), (b) and (c); (b), (a), (d) and (c); and (b), (c), (a) and (d).
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: July 8, 2003
    Assignee: AlliedSignal Inc.
    Inventors: Denis H. Endisch, James S. Drage
  • Patent number: 6589890
    Abstract: The invention is a precleaning process suitable for fabricating metal plugs in a low-&kgr;, carbon-containing dielectric. More specifically, the invention is a process for cleaning a contact area of a metal conductor on a semiconductor workpiece so as to minimize damage to a low-&kgr;, carbon-containing dielectric overlying the metal. After forming contact openings in the low-&kgr; dielectric so as to expose contact areas on the underlying metal conductor, the contact areas are cleaned by exposing the workpiece to an atmosphere formed by plasma decomposition of a mixture of hydrogen-containing and helium gases. Surprisingly, our preclean process can repair damage to the dielectric caused by preceding process steps, such as oxygen plasma ashing processes for removing photoresist.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: July 8, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Barney M. Cohen, Suraj Rengarajan, Kenny King-Tai Ngan
  • Patent number: 6583070
    Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: June 24, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ting Y. Tsui, Ercan Adem
  • Patent number: 6583069
    Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in a reactor chamber. A key feature of the invention's process is a mole ratio of gas additive to source of silicon, which is maintained in the range of about 0.3-20 depending on the compound used and the deposition process conditions. As a gas additive, one of the group including halide-containing organic compounds having the general formula CxHyRz, and chemical compounds with the double carbon-carbon bonds having the general formula CnH2n, is used.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: June 24, 2003
    Assignee: Chartered Semiconductor Manufacturing Co., Ltd.
    Inventors: Vladislav Y. Vassiliev, John Leonard Sudijono
  • Publication number: 20030113992
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.
    Type: Application
    Filed: November 21, 2002
    Publication date: June 19, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Wai-Fan Yau, David Cheung, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Yu
  • Patent number: 6579808
    Abstract: A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: June 17, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Yoon Cho, Jae Heon Kim
  • Patent number: 6576300
    Abstract: Low dielectric constant films with improved elastic modulus. The method of making such coatings involves providing a porous network coating produced from a resin containing at least 2 Si—H groups where the coating has been thermally cured and has a dielectric constant in the range of from about 1.1 to about 3.5, and plasma treating the coating to convert the coating into porous silica. Plasma treatment of the network coating yields a coating with improved modulus, but with a higher dielectric constant. The coating is plasma treated for between about 15 and 120 seconds at a temperature less than or about 350° C. The plasma treated coating can optionally be annealed. Rapid thermal processing (RTP) of the plasma treated coating reduces the dielectric constant of the coating while maintaining an improved elastic modulus as compared to the initial porous coating. The annealing temperature is preferably in excess of or about 350° C., and the annealing time is preferably at least or about 120 seconds.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: June 10, 2003
    Assignees: Dow Corning Corporation, Axcelis Technologies, Inc.
    Inventors: Ivan Louis Berry, III, Kyuha Chung, Qingyuan Han, Youfan Liu, Eric Scott Moyer, Michael John Spaulding
  • Patent number: 6576557
    Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: June 10, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Satish Bedge