Silicon Oxide Formation Patents (Class 438/787)
  • Patent number: 11638374
    Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: April 25, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
  • Patent number: 11587830
    Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 21, 2023
    Assignee: TESSERA LLC
    Inventors: Benjamin D. Briggs, Elbert Huang, Takeshi Nogami, Christopher J. Penny
  • Patent number: 11522091
    Abstract: Disclosed is a solar cell. The solar cell includes a semiconductor substrate, conductivity-type regions located in or on the semiconductor substrate, electrodes conductively connected to the conductivity-type regions, and insulating films located on at least one of opposite surfaces of the semiconductor substrate, and including a first film and a second film located on the first film, the second film has a higher carbon content than that of the first film, a refractive index of the second film is equal to or less than a refractive index of the first film, and an extinction coefficient of the second film is equal to or greater than an extinction coefficient of the first film.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 6, 2022
    Inventors: Juhong Yang, Indo Chung, Eunjoo Lee, Mihee Heo
  • Patent number: 11393673
    Abstract: A deposition method includes a first process performed by repeating causing aminosilane gas to be adsorbed on a substrate; causing a first silicon oxide film to be stacked on the substrate by supplying oxidation gas to the substrate to oxidize the aminosilane gas adsorbed on the substrate; and performing a reforming process on the first silicon oxide film by activating a first reformed gas by plasma and supplying the first reformed gas to the first silicon oxide film, and a second process, performed after the first process, by repeating causing aminosilane gas to be adsorbed on the substrate; causing a second silicon oxide film to be stacked on the substrate by supplying oxidation gas; and performing a reforming process on the second silicon oxide film by supplying a plasma-activated second reformed gas. The first reformed gas has a smaller effect of oxidizing the substrate than the second reformed gas.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 19, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Chiba, Jun Sato
  • Patent number: 11328831
    Abstract: Treating a reflective optical element (104) for the EUV wavelength range that has a reflective coating on a substrate. The reflective optical element in a holder (106) is irradiated with at least one radiation pulse of a radiation source (102) having a duration of between 1 ?s and 1 s. At least one radiation source (102) and the reflective optical element move relative to one another. Preferably, this is carried out directly after applying the reflective coating in a coating chamber (100). Reflective optical elements of this type are suitable in particular for use in EUV lithography or in EUV inspection of masks or wafers, for example.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: May 10, 2022
    Assignee: CARL ZEISS SMT GMBH
    Inventors: Christian Grasse, Martin Hermann, Stephan Six, Joern Weber, Ralf Winter, Oliver Dier, Vitaliy Shklover, Kerstin Hild, Sebastian Strobel
  • Patent number: 11088036
    Abstract: The disclosure is directed to techniques in preparing an atom probe tomography (“APT”) specimen. A structure in a semiconductor device is identified as including a test object for an APT procedure. A target region is identified in the structure where an APT specimen will be obtained. The target region is analyzed to determine whether a challenging component feature exists therein. A challenging component may include a hard-to-evaporate material, a hollow region, or a material unidentifiable with respect to the test object, or other structural features that pose a challenge to a successful APT analysis. If it is determined that a challenging component exists in the target region, the challenging component is replaced with a more suitable material before the APT specimen is prepared.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Hung, Jang Jung Lee
  • Patent number: 11077410
    Abstract: Gas injectors for providing uniform flow of fluid are provided herein. The gas injector includes a plenum body. The plenum body includes a recess, a protrusion adjacent to the recess and extending laterally away from the plenum body, and a plurality of nozzles extending laterally from an exterior surface of the plenum body. The plenum body has a plurality of holes in an exterior wall of the plenum body. Each nozzle is in fluid communication with an interior volume of the plenum body. By directing the flow of fluid, the gas injector provides for a uniform deposition.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 3, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Vishwas Kumar Pandey, Lara Hawrylchak, Eric Kihara Shono, Kartik Shah, Christopher S. Olsen, Sairaju Tallavarjula, Kailash Pradhan, Rene George, Johanes F. Swenberg, Stephen Moffatt
  • Patent number: 10930544
    Abstract: A method of manufacturing a semiconductor device, which has buried gate electrodes, includes: forming a plurality of gate trenches in a substrate having a plurality of active regions defined by a device isolation film, the plurality of gate trenches crossing the plurality of active regions and extending parallel to each other in a first horizontal direction; selectively forming a first gate insulating layer on an exposed surface of the substrate; forming a second gate insulating layer on exposed surfaces of both the first gate insulating layer and the device isolation film; and forming a plurality of gate insulating layers by partially removing the first gate insulating layer and the second gate insulating layer, and forming a plurality of buried gate electrodes.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-jae Kang, Yun-jung Kim, Se-min Yang, Ki-bum Lee
  • Patent number: 10910199
    Abstract: A method of controlling a position of an adjustable nozzle includes depositing a film on a surface of a wafer. The method includes measuring a thickness profile of the surface of the wafer. The method includes comparing the measurement of the thickness profile with a reference value using a control unit. The method includes transmitting a control signal to the adjustable nozzle to alter the position of the adjustable nozzle based on the result of the comparison. The adjustable nozzle includes a base having a hollow center portion for conducting gas, the base configured for connection to a gas source. The adjust nozzle includes a tip coupled to the base and having an opening for conducting gas from the base to the exterior of the nozzle, wherein the base is configured for pivoting about a longitudinal axis of the base in response to the control signal.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ching Wu, Wen-Long Lee, Ding-I Liu
  • Patent number: 10867788
    Abstract: The invention relates to depositing a layer on a substrate in a reactor, by: introducing a first precursor comprising a silicon halide in the reactor; introducing a second precursor in the reactor; providing an energy source to create a plasma from the second precursor so that the second precursor reacts with the first precursor until a primary layer comprising silicon and second precursor of a desired thickness is formed; stop introducing the second precursor; and, subsequently introducing the silicon halide in the reactor at a temperature causing decomposition of the silicon halide precursor to provide a substantially pure amorphous silicon layer on top of the primary layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 15, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Timothee Julien Vincent Blanquart, Suvi P. Haukka
  • Patent number: 10825718
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 3, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Patent number: 10784102
    Abstract: The invention relates to a method of providing a structure by depositing a layer on a substrate in a reactor. The method comprising: introducing a silicon halide precursor in the reactor; introducing a reactant gas comprising oxygen in the reactor; and, providing an energy source to create a plasma from the reactant gas so that the oxygen reacts with the first precursor in a layer comprising silicon dioxide.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 22, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Timothee Blanquart, David de Roest
  • Patent number: 10751765
    Abstract: The present disclosure relates to a chemical vapor deposition system for processing large area substrates. The chemical vapor deposition system includes a chemical vapor deposition chamber comprising a chamber body having a plurality of sidewalls, a lid assembly, and a bottom. A substrate support extends upward from the bottom within the chamber body. A gas distribution plate is located within the lid assembly. One or more cleaning gas injector ports coupled to corresponding one or more inlets in the plurality of sidewalls. Each of the one or more cleaning gas injector ports has a substantially oval-shaped or circular-shaped cleaning gas nozzle configured to provide reactive species from a remote plasma source to clean an underside of the gas distribution plate.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 25, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tae Kyung Won, Young Dong Lee, Chien-Teh Kao, Soo Young Choi, Sanjay D. Yadav
  • Patent number: 10697080
    Abstract: Photoactive silicon films may be formed by electrodeposition from a molten salt electrolyte. In an embodiment, SiO2 is electrochemically reduced in a molten salt bath to deposit silicon on a carbonaceous substrate.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: June 30, 2020
    Assignee: Board of Regents of the University of Texas System
    Inventors: Allen J. Bard, Huayi Yin
  • Patent number: 10676825
    Abstract: The gas jetting apparatus according to the present invention includes a gas jetting cell unit for rectifying a gas and jetting the rectified gas into the film formation apparatus. The gas jetting cell unit has a fan shape internally formed with a gap serving as a gas route. A gas in a gas dispersion supply unit enters from a wider-width side of the fan shape into the gap, and, due to the fan shape, the gas is rectified, accelerated, and output from a narrower-width side of the fan shape into the film formation apparatus.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 9, 2020
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Yoichiro Tabata, Kensuke Watanabe, Shinichi Nishimura
  • Patent number: 10654248
    Abstract: The present invention provides a conductive structure and an electronic device comprising same. The conductive structure comprises a first hafnium oxide layer, a metal layer, a second hafnium oxide layer and satisfies mathematical formula 1.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 19, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Sujin Kim, Yong Chan Kim, Ki-Hwan Kim
  • Patent number: 10410857
    Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyl halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 10, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Toshiya Suzuki, Viljami J. Pore, Shang Chen, Ryoko Yamada, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 10354923
    Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chun Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang
  • Patent number: 10340136
    Abstract: A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 2, 2019
    Assignee: Lam Research Corporation
    Inventors: Douglas Walter Agnew, Ishtak Karim
  • Patent number: 10312432
    Abstract: A method may include: providing a device stack, the device stack comprising sidewall portions and extending above a substrate base, the device stack further including a plurality of metal layers; depositing an interface layer conformally over the device stack using an atomic layer deposition process, the interface layer comprising a first insulator material; depositing an encapsulation layer on the interface layer, the encapsulation layer comprising a second insulator material; and depositing an interlevel dielectric disposed on the encapsulation layer, the interlevel dielectric comprising a third insulator material.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: June 4, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Tsung-Liang Chen, Shurong Liang, Alexander C. Kontos
  • Patent number: 10283348
    Abstract: A method and composition for depositing a silicon oxide film in an atomic layer deposition process at one or more temperatures of 650° C. or greater is provided. In one aspect, there is provided a method to deposit a silicon oxide film or material comprising the steps of: providing a substrate in a reactor; introducing into the reactor at least one halidosiloxane precursor selected from the group of compounds having formulae I and II described herein; purging the reactor with a purge gas; introducing an oxygen source into the reactor; and purging reactor with purge gas; and wherein the steps are repeated until a desired thickness of silicon oxide is deposited and the process is conducted at one or more temperatures ranging from about 650 to 1000° C.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 7, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Meiliang Wang, Xinjian Lei, Anupama Mallikarjunan, Haripin Chandra, Bing Han
  • Patent number: 10269558
    Abstract: The invention relates to a method of providing a structure by depositing a layer on a substrate in a reactor. The method comprising: introducing a silicon halide precursor in the reactor; introducing a reactant gas comprising oxygen in the reactor; and, providing an energy source to create a plasma from the reactant gas so that the oxygen reacts with the first precursor in a layer comprising silicon dioxide.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 23, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Timothee Blanquart, David de Roest
  • Patent number: 10229852
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V. V. S. Surisetty
  • Patent number: 10032626
    Abstract: A semiconductor device manufacturing method includes: vertically arranging and storing a plurality of substrates in a processing container and forming a condition where at least an upper region or a lower region relative to a substrate disposing region where the plurality of substrates are arranged is blocked off by an adaptor; and while maintaining the condition, forming films on the plurality of substrates by performing a cycle including the following steps a predetermined number of times in a non-simultaneous manner: supplying source gas to the plurality of substrates in the processing container from the side of the substrate disposing region; discharging the source gas from the interior of the processing container via exhaust piping; supplying reaction gas to the plurality of substrates in the processing container from the side of the substrate disposing region; and discharging the reaction gas from the interior of the processing container via the exhaust piping.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 24, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takaaki Noda, Shingo Nohara, Kosuke Takagi, Takeo Hanashima, Mamoru Sueyoshi, Kotaro Konno, Motoshi Sawada
  • Patent number: 9929005
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes: (a) accommodating a substrate having a plurality of carbon-containing films protruding from a surface of the substrate; (b) forming a silicon-containing film on a surface of the plurality of carbon-containing films and a surface of the substrate by supplying a silicon-containing gas to the substrate; (c) forming a silicon/oxygen-containing film by supplying a first plasma of an oxygen-containing gas to the substrate; and (d) forming a silicon oxide film by supplying a second plasma of the oxygen-containing gas to the substrate after performing (c).
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 27, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Satoshi Shimamoto, Teruo Yoshino, Tadashi Terasaki, Masanori Nakayama
  • Patent number: 9607828
    Abstract: A method of depositing a silicon-containing film using a film deposition apparatus is provided. The apparatus includes a turntable provided in a process chamber. In the method, a seed layer is formed on a surface of the substrate by supplying an aminosilane gas from the first process gas supplying unit for a predetermined period of time while rotating the turntable. A boron-containing gas is supplied from the first gas supplying unit to the surface of the substrate while rotating the turntable after finishing the step of forming the seed layer on the surface of the substrate. A silane-based gas is supplied from the second process gas supplying unit to the surface of the substrate while rotating the turntable and causing silicon atoms contained in the silane-based gas to bond with each other on the surface of the substrate by a catalytic action of the boron-containing gas.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 28, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Sato, Shigehiro Miura
  • Patent number: 9543248
    Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: January 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Junjing Bao, John Jianhong Zhu, Stanley Seungchul Song, Niladri Narayan Mojumder, Choh Fei Yeap
  • Patent number: 9412650
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
  • Patent number: 9340900
    Abstract: A method of producing an epitaxial wafer, comprising: performing epitaxial growth of silicon on a main surface of a wafer made of a silicon single crystal; performing surface flattening pretreatment of a main surface of the wafer using a treatment liquid of a predetermined composition at a temperature of 100° C. or less, thereby forming an oxide film of a predetermined thickness while removing particles adhered on the main surface of the wafer; and performing a surface polishing step where the main surface of the wafer is mirror polished.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: May 17, 2016
    Assignee: Sumco Corporation
    Inventors: Shinji Nakahara, Masato Sakai, Takayuki Dohi
  • Patent number: 9343293
    Abstract: Methods are described for forming a dielectric layer on a patterned substrate. The methods may include combining a silicon-and-carbon-containing precursor and a radical oxygen precursor in a plasma free substrate processing region within a chemical vapor deposition chamber. The silicon-and-carbon-containing precursor and the radical oxygen precursor react to deposit a flowable silicon-carbon-oxygen layer on the patterned substrate. The resulting film possesses a low wet etch rate ratio relative to thermal silicon oxide and other standard dielectrics.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 17, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Brian Saxton Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 9279184
    Abstract: A method of forming a pattern is provided. The method includes an etching step of forming a predetermined pattern in a silicon-containing film by etching the silicon-containing film deposited on a substrate through a mask by plasma generated from an etching gas containing a fluorocarbon gas, and a film deposition step of depositing a silicon oxide film or a silicon nitride film on a surface of the predetermined pattern by oxidizing or nitriding a silicon-containing layer adsorbed on the surface of the predetermined pattern by supplying a silicon compound gas, by using plasma generated from an oxidation gas or a nitriding gas.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 8, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhiro Kubota, Ryukichi Shimizu
  • Patent number: 9257274
    Abstract: Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 9, 2016
    Assignee: Lam Research Corporation
    Inventors: Hu Kang, Shankar Swaminathan, Jun Qian, Wanki Kim, Dennis Hausmann, Bart J. van Schravendijk, Adrien LaVoie
  • Patent number: 9171942
    Abstract: There is provided a method of manufacturing a semiconductor element including: forming a semiconductor film of which a principal constituent is an oxide semiconductor; forming a first insulation film on a surface of the semiconductor film; applying a heat treatment in an oxidizing atmosphere; and, forming a second insulation film on a surface of the first insulation film, wherein a thickness of the first insulation film and a temperature of the heat treatment in the third step are adjusted such that, if the thickness of the first insulation film is represented by Z (nm), the heat treatment temperature is represented by T (° C.) and a diffusion distance of oxygen into the first insulation film and the semiconductor film is represented by L (nm), the relational expression 0<Z<L=8×10?6×T3?0.0092×T2+3.6×T?468±0.1 is satisfied.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 27, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Fumihiko Mochizuki, Masahiro Takata, Masashi Ono, Atsushi Tanaka, Masayuki Suzuki
  • Patent number: 9147845
    Abstract: A single-walled carbon nanotube-based planar photodetector includes a substrate; a first electrode and a second electrode disposed on the substrate and spaced apart from each other; a plurality of single-walled carbon nanotubes, each of the plurality of single-walled carbon nanotubes contacting the first electrode and the second electrode; and an adsorbent attached to a surface of at least one of the plurality of single-walled carbon nanotubes, wherein the adsorbent is capable of doping the at least one of the plurality of single-walled carbon nanotubes by photo-excitation.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 29, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., The Board of Trustees of the Leland Stanford Junior University
    Inventors: Young-jun Park, Steve Park, Zhenan Bao
  • Patent number: 9105704
    Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 11, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik
  • Patent number: 9093560
    Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 28, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
  • Patent number: 9076646
    Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes using pulsed plasmas. While conventional PEALD processes use continuous wave plasmas during the plasma exposure/conversion operation, the embodiments herein utilize a pulsed plasma during this operation to achieve a film with high quality sidewalls. Because conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls, this increased sidewall quality in the disclosed methods corresponds to a film that is overall more uniform in quality compared to that achieved with conventional continuous wave plasma techniques.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 7, 2015
    Assignee: Lam Research Corporation
    Inventors: James S. Sims, Jon Henri, Kathryn M. Kelchner, Sathish Babu S. V. Janjam, Shane Tang
  • Patent number: 9064692
    Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: June 23, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shivani Srivastava, Kunal Shrotri, Fawad Ahmed
  • Patent number: 9040434
    Abstract: A film deposition method includes a step of condensing hydrogen peroxide on a substrate including a concave portion formed in a surface thereof by supplying a gas containing the hydrogen peroxide, and a step of supplying a silicon-containing gas reactable with the hydrogen peroxide to the substrate having the hydrogen peroxide condensed thereon.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Tokyo Electron Limited
    Inventor: Hitoshi Kato
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9029272
    Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
  • Patent number: 9023738
    Abstract: A film deposition method, in which a film of a reaction product of a first reaction gas, which tends to be adsorbed onto hydroxyl radicals, and a second reaction gas capable of reacting with the first reaction gas is formed on a substrate provided with a concave portion, includes a step of controlling an adsorption distribution of the hydroxyl radicals in a depth direction in the concave portion of the substrate; a step of supplying the first reaction gas on the substrate onto which the hydroxyl radicals are adsorbed; and a step of supplying the second reaction gas on the substrate onto which the first reaction gas is adsorbed.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: May 5, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Tatsuya Tamura, Takeshi Kumagai
  • Patent number: 9023737
    Abstract: A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and/or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and/or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and/or holes and a portion of the film deposited on top and bottom surfaces of the trenches and/or holes.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 5, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Julien Beynet, Ivo Raaijmakers, Atsuki Fukazawa
  • Patent number: 9018093
    Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 28, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Naoto Tsuji, Fumitaka Shoji
  • Patent number: 9018108
    Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Sukwon Hong, Toan Tran, Abhijit Mallick, Jingmei Liang, Nitin K. Ingle
  • Patent number: 9011601
    Abstract: A substrate processing apparatus capable of forming an oxide film on a substrate by forming a layer on the substrate by supplying a source gas into a process vessel accommodating the substrate via the first nozzle, and simultaneously supplying an oxygen-containing gas through a second nozzle and a hydrogen-containing gas through a first nozzle into the process vessel having an inside pressure thereof lower than atmospheric pressure; mixing and reacting the oxygen-containing gas with the hydrogen-containing gas in a non-plasma atmosphere within the process vessel to generate atomic oxygen; and oxidizing the layer with the atomic oxygen to change the layer into an oxide layer is disclosed.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: April 21, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
  • Patent number: 9012335
    Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 9012336
    Abstract: Disclosed are apparatus and methods for processing a substrate. The substrate having a feature with a layer thereon is exposed to an inductively coupled plasma which forms a substantially conformal layer.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Heng Pan, Matthew Scott Rogers, Johanes F. Swenberg, Christopher S. Olsen, Wei Liu, David Chu, Malcom J. Bevan
  • Patent number: 9006116
    Abstract: A silicon oxide film is formed, having a specific film thickness on a substrate by alternately repeating: forming a silicon-containing layer on the substrate by supplying a source gas containing silicon, to the substrate housed in a processing chamber and heated to a first temperature; and oxidizing and changing the silicon-containing layer formed on the substrate, to a silicon oxide layer by supplying reactive species containing oxygen to the substrate heated to the first temperature in the processing chamber under a pressure atmosphere of less than atmospheric pressure, the reactive species being generated by causing a reaction between an oxygen-containing gas and a hydrogen-containing gas in a pre-reaction chamber under a pressure atmosphere of less than atmospheric pressure and heated to a second temperature equal to the first temperature or higher than the first temperature.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: April 14, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Masato Terasaki
  • Patent number: 9006115
    Abstract: A method of forming a silicone oxide film includes: forming a silicon oxide film on a plurality of target objects by supplying a chlorine-containing silicon source into a reaction chamber accommodating the plurality of target objects; and modifying the silicon oxide film, which is formed by forming the silicon oxide film, by supplying hydrogen and oxygen or hydrogen and nitrous oxide into the reaction chamber and making an interior of the reaction chamber be under a hydrogen-oxygen atmosphere or a hydrogen-nitrous oxide atmosphere.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Tomoyuki Obu, Masaki Kurokawa