Ionized Irradiation (e.g., Corpuscular Or Plasma Treatment, Etc.) Patents (Class 438/798)
  • Patent number: 10580859
    Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Rag Do, Yeon Goog Sung
  • Patent number: 10438806
    Abstract: Techniques herein include methods for selectively modifying chemical properties of organosilicates including periodic mesoporous organosilicates (PMOs) in situ for use in fabrication of semiconductor devices. With techniques herein, such materials are manipulated in their chemical properties after deposition and can accordingly be used as sacrificial patterning films and/or as patterning enabling materials. Using selective treatments such as annealing, curing, plasma exposure, and silylation, chemical properties such as etch resistance and hydrophobicity can be changed to enable a given patterning operation. A given film can be etch resistant for one patterning operation, and then changed to be etch removable for a subsequent patterning operation.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kathleen Nafus, Serge Biesemans
  • Patent number: 10312331
    Abstract: A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 4, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Hiroshi Takishita, Takashi Yoshimura, Takahiro Tamura, Yuichi Onozawa
  • Patent number: 9613870
    Abstract: Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Aritra Dasgupta, Oleg Gluschenkov, Balaji Kannan, Unoh Kwon
  • Patent number: 9502232
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Huang Liu, Adam Selsley
  • Patent number: 9431238
    Abstract: In some embodiments, a reactive curing process may be performed by exposing a semiconductor substrate in a process chamber to an ambient containing hydrogen peroxide, with the pressure in the process chamber at about 300 Torr or less. In some embodiments, the residence time of hydrogen peroxide molecules in the process chamber is about five minutes or less. The curing process temperature may be set at about 500° C. or less. The curing process may be applied to cure flowable dielectric materials and may provide highly uniform curing results, such as across a batch of semiconductor substrates cured in a batch process chamber.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 30, 2016
    Assignee: ASM IP HOLDING B.V.
    Inventors: Bert Jongbloed, Dieter Pierreux, Cornelius A. van der Jeugd, Herbert Terhorst, Lucian Jdira, Radko G. Bankras, Theodorus G. M. Oosterlaken
  • Patent number: 9337058
    Abstract: There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 10, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shinya Iwasaki
  • Patent number: 9263708
    Abstract: A method of removing particles from a display panel is disclosed. In one aspect, the method includes charging the particles and applying an electric field to the charged particles to capture the charged particles. Organic particles and inorganic particles may be forcibly charged to capture the organic and inorganic particles using a metal bar so that the organic and inorganic particles may be substantially removed.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: February 16, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joo-Nyung Jang
  • Patent number: 9218654
    Abstract: An apparatus for recognizing an object may include a lens, a camera and a signal-processing unit. The lens may include two cross sections having different focal lengths. The camera may be configured to photograph the object having a first part through the lens. The first part may have a first shape. The signal-processing unit may be configured to recognize a height of the first part based on deviations of the first shape in an image obtained from the camera. Thus, the apparatus may only include the cylindrical lens interposed between the object and the camera except for the softwares for processing the signals. As a result, the apparatus may have a simple structure without a structure of a laser irradiation.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ueyama Shinji, Kajinami Masato, Togashi Mitsuhiro, Yukimori Yoshiaki
  • Patent number: 9202788
    Abstract: A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yasutoshi Okuno, Yi-Tang Lin
  • Patent number: 9040884
    Abstract: An apparatus for fabricating semiconductor devices includes a chamber having a bottom plane, a side wall and a lid. An irradiating unit is at an interior of the chamber. A substrate mounting unit is between the bottom plane of the chamber and the irradiating unit. The irradiating unit includes an irradiating tube and a hole penetrating the central region of the irradiating tube. The irradiating tube has a hollow disk shape, and a lower surface of the irradiating tube is opened to the substrate mounting unit.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il-Young Han, Jae-Sung Kwon, Sang-Wook Park, Won-Keun Kim
  • Publication number: 20150140798
    Abstract: A semiconductor manufacturing equipment includes a buffer chamber, a load port, a first chamber, and a second chamber respectively connected with the buffer chamber at a different side. The semiconductor manufacturing equipment also has a third chamber in the buffer chamber, the third chamber configured for cooling a wafer, and a single blade robot in the buffer chamber. Moreover, the semiconductor manufacturing equipment has a controller including a program, wherein the program elevates a wafer transfer priority for the first chamber and the second chamber higher than a wafer transfer priority for the third chamber.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: FANG-YUE HSU
  • Publication number: 20150126046
    Abstract: A processing system is disclosed, having a multiple power transmission elements with an interior cavity that may be arranged around a plasma processing chamber. Each of the power transmission elements may propagates electromagnetic energy that may be used to generate plasma within the plasma process chamber. The power transmission elements may be designed to accommodate a range of power and frequency ranges that range from 500W to 3500W and 0.9 GHz to 9 GHz. In one embodiment, the power transmission elements may include a rectangular interior cavity that enables the generation of a standing wave with two or more modes. In another embodiment, the power transmission elements may have a cylindrical interior cavity that may be placed along the plasma processing chamber or have one end of the cylinder placed against the plasma processing chamber.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 7, 2015
    Inventors: Merritt Funk, Megan Doppel, John Entralgo, Jianping Zhao, Toshihisa Nozawa
  • Patent number: 9023693
    Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Kung-Liang Lin, Chien-Chih Chen, Fu-Ching Tung, Chih-Yung Chen, Shih-Chin Lin, Kuan-Yu Lin, Chia-Hao Chang, Shieh-Sien Wu
  • Publication number: 20150118867
    Abstract: To provide a plasma processing device, a plasma processing method and a method of manufacturing electronic devices capable of performing high-speed processing as well as using the plasma stably. In an inductively-coupled plasma torch unit, a coil, a first ceramic block and a second ceramic block are arranged in parallel, and a long chamber has an annular shape. Plasma generated in the chamber is ejected from an opening in the chamber toward a substrate. The substrate is processed by moving the long chamber and the substrate mounting table relatively in a direction perpendicular to a longitudinal direction of the opening. A discharge suppression gas is introduced into a space between the inductively-coupled plasma torch unit and the substrate inside the chamber through a discharge suppression gas supply hole, thereby generating long plasma stably.
    Type: Application
    Filed: July 25, 2014
    Publication date: April 30, 2015
    Inventor: TOMOHIRO OKUMURA
  • Patent number: 9018111
    Abstract: A processing chamber including a reaction chamber having a processing area, a processing gas inlet in communication with the processing area, a first excited species generation zone in communication with the processing gas inlet and a second exited species generation zone in communication with the processing gas inlet. A method of processing a substrate including the steps of loading a substrate within a processing area, activating a first excited species generation zone to provide a first excited species precursor to the processing area during a first pulse and, activating a second excited species generation zone to provide a second excited species precursor different from the first excited species precursor to the processing area during a second pulse.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 28, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Publication number: 20150111396
    Abstract: A method for repairing and lowering the dielectric constant of low-k dielectric layers used in semiconductor fabrication is provided. In one implementation, a method of repairing a damaged low-k dielectric layer comprising exposing the porous low-k dielectric layer to a vinyl silane containing compound and optionally exposing the porous low-k dielectric layer to an ultraviolet (UV) cure process.
    Type: Application
    Filed: October 31, 2014
    Publication date: April 23, 2015
    Inventors: Kelvin CHAN, Alexandros T. DEMOS
  • Patent number: 9012336
    Abstract: Disclosed are apparatus and methods for processing a substrate. The substrate having a feature with a layer thereon is exposed to an inductively coupled plasma which forms a substantially conformal layer.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: April 21, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Heng Pan, Matthew Scott Rogers, Johanes F. Swenberg, Christopher S. Olsen, Wei Liu, David Chu, Malcom J. Bevan
  • Publication number: 20150104957
    Abstract: A method for processing a resist mask includes: (a) a step of preparing, in a processing chamber, a target object to be processed having a patterned resist mask provided thereon; and (b) a step of generating a plasma of the hydrogen-containing gas by supplying a hydrogen-containing gas and supplying a microwave into the processing chamber. The hydrogen-containing gas may be, e.g., H2 gas.
    Type: Application
    Filed: June 17, 2013
    Publication date: April 16, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Michihisa Takachi, Yusuke Shimizu, Toshihisa Ozu
  • Patent number: 9006104
    Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Vidmantas Sargunas
  • Patent number: 8999865
    Abstract: A laser annealing apparatus carries out an annealing treatment an amorphous silicon film on a TFT substrate. The apparatus includes: a mask having a plurality of apertures; a microlens substrate having a plurality of microlenses arranged on a surface thereof and configured to focus the plurality of laser beams Lb, that have passed through the respective apertures of the mask, onto the TFT substrate to apply a predetermined energy to the amorphous silicon film; a pair of guides each having a semi-cylindrical shape and disposed along both sides across the microlens substrate so that the axes of the guides are parallel to each other and that the tips of the guides protrude from the positions of tips of the microlenses toward the TFT substrate; and a film that is provided in a tensioned state between the pair of guides so as to be movable and that transmits a laser beam.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: April 7, 2015
    Assignee: V Technology Co., Ltd.
    Inventors: Michinobu Mizumura, Yuji Saito
  • Publication number: 20150087162
    Abstract: A plasma processing apparatus includes: a processing container which defines a processing space; a microwave generator; a dielectric having an opposing surface which faces the processing space; a slot plate formed with a plurality of slots; and a heating member provided within the slot plate. The slot plate is provided on a surface of the dielectric at an opposite side to the opposing surface to radiate microwaves for plasma excitation to the processing space through the dielectric based on the microwaves generated by the microwave generator.
    Type: Application
    Filed: May 17, 2013
    Publication date: March 26, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Naoki Matsumoto
  • Patent number: 8980765
    Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sunil Shanker, Tony P. Chiang
  • Publication number: 20150072538
    Abstract: Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal oxide surface on a substrate is reduced. A remote plasma apparatus can treat the metal oxide surface as well as cool, load/unload, and move the substrate within a single standalone apparatus. The remote plasma apparatus includes a processing chamber and a controller configured to provide a substrate having a metal seed layer in a processing chamber, move the substrate towards a substrate support in the processing chamber, form a remote plasma of a reducing gas species, expose a metal seed layer of the substrate to the remote plasma, and expose the substrate to a cooling gas. In some embodiments, the remote plasma apparatus is part of an electroplating apparatus.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Inventors: Tighe A. Spurlin, James E. Duncan, Stephen Lau, Marshall Stowell, Jonathan D. Reid, David Porter
  • Patent number: 8975603
    Abstract: Systems and methods for plasma doping microfeature workpieces are disclosed herein. In one embodiment, a method of implanting boron ions into a region of a workpiece includes generating a plasma in a chamber, selectively applying a pulsed electrical potential to the workpiece with a duty cycle of between approximately 20 percent and approximately 50 percent, and implanting an ion specie into the region of the workpiece.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Allen McTeer
  • Publication number: 20150064934
    Abstract: In accordance with one aspect of this invention, a multi charged particle beam writing apparatus includes an aperture member, in which a plurality of openings are formed, configured to form multi-beams by making portions of the charged particle beam pass through the plurality of openings; a plurality of blankers configured to perform blanking-deflect regarding beams corresponding to the multi-beams; a writing processing control unit configured to control writing processing with a plurality of beams having passed through different openings among the plurality of openings being irradiated on the target object at a predetermined control grid interval; and a dose controlling unit configured to variably control a dose of a beam associated with deviation according to a deviation amount when an interval between the plurality of beams irradiated is deviated from the control grid interval.
    Type: Application
    Filed: October 30, 2014
    Publication date: March 5, 2015
    Applicant: NuFlare Technology, Inc.
    Inventors: Ryoichi YOSHIKAWA, Munehiro OGASAWARA
  • Patent number: 8940642
    Abstract: Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: January 27, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Yifeng Zhou, Dmitry Lubomirsky, Ellie Yieh
  • Publication number: 20150024609
    Abstract: A processing chamber including a reaction chamber having a processing area, a processing gas inlet in communication with the processing area, a first excited species generation zone in communication with the processing gas inlet and a second exited species generation zone in communication with the processing gas inlet. A method of processing a substrate including the steps of loading a substrate within a processing area, activating a first excited species generation zone to provide a first excited species precursor to the processing area during a first pulse and, activating a second excited species generation zone to provide a second excited species precursor different from the first excited species precursor to the processing area during a second pulse.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Publication number: 20150011097
    Abstract: A plasma processing system having a plasma processing chamber configured for processing a substrate is provided. The plasma processing system includes at least an upper electrode and a lower electrode for processing the substrate. The substrate is disposed on the lower electrode during plasma processing, where the upper electrode and the substrate forms a first gap. The plasma processing system also includes an upper electrode peripheral extension (UE-PE). The UE-PE is mechanically coupled to a periphery of the upper electrode, where the UE-PE is configured to be non-coplanar with the upper electrode. The plasma processing system further includes a cover ring. The cover ring is configured to concentrically surround the lower electrode, where the UE-PE and the cover ring forms a second gap.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Inventors: Andreas Fischer, Eric Hudson
  • Publication number: 20150004807
    Abstract: A drawing apparatus for performing drawing on a substrate with a charged particle beam, includes: a controller configured to control a dose of the charge particle beam at each of a plurality of positions of the charged particle beam on the substrate based on information of displacement of each of the plurality of positions from a target position corresponding thereto and a target dose of the charged particle beam at the target position corresponding to each of the plurality of positions.
    Type: Application
    Filed: June 24, 2014
    Publication date: January 1, 2015
    Inventors: Masato Muraki, Tomoyuki Morita
  • Patent number: 8921214
    Abstract: A method for fabricating a variable resistance memory device includes forming an oxygen-deficient first metal oxide layer over a first electrode, forming an oxygen-rich second metal oxide layer over the first metal oxide layer, treating the first and second metal oxide layers with hydrogen-containing plasma, forming an oxygen-rich third metal oxide layer, and forming a second electrode over the third metal oxide layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Kee-Jeung Lee, Beom-Yong Kim, Wan-Gee Kim, Woo-Young Park
  • Patent number: 8921240
    Abstract: An ion implantation method includes generating CmHy+ ions (m is such an integer as 4?m?6, and y is such an integer as 1?y?2m+2) using an ion generating material expressed by CnHx (n is such an integer as 4?n?6, and x is such an integer as 1?x?2n+2), and implanting the ions into a wafer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: December 30, 2014
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventors: Yasunori Kawamura, Kyoko Kawakami, Yoshiki Nakashima
  • Publication number: 20140374883
    Abstract: A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.
    Type: Application
    Filed: March 4, 2014
    Publication date: December 25, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: CHOONGBIN YIM, HYEONGMUN KANG, TAESUNG PARK, EUNCHUL AHN
  • Patent number: 8912071
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140363986
    Abstract: A system is provided for thermal processing of a semiconductor substrate including a laser configured for emitting a laser beam towards the semiconductor substrate and a scanning means configured for scanning the laser beam along a first plurality of paths on the semiconductor substrate such that the paths are spaced apart from each other by predetermined distances. Further, a method for thermal processing of a semiconductor substrate is provided including scanning a laser beam along a first plurality of paths on the semiconductor substrate such that the paths are spaced apart from each other by predetermined distances.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventor: Jan Holub
  • Publication number: 20140357092
    Abstract: A semiconductor plasma processing apparatus includes a vacuum chamber in which semiconductor substrates are processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, and an RF energy source adapted to energize the process gas into the plasma state in the vacuum chamber. The apparatus can also include a chamber wall wherein the chamber wall includes a means for supplying a plasma compatible liquid to a plasma exposed surface thereof wherein the plasma compatible liquid flows over the plasma exposed surface thereby forming a flowing protective liquid layer thereon. A liquid supply delivers the plasma compatible liquid to the chamber wall.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 4, 2014
    Inventor: Harmeet Singh
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Publication number: 20140349493
    Abstract: Apparatuses and methods for processing substrates are disclosed. A processing apparatus includes a chamber for generating a plasma therein, an electrode associated with the chamber, and a signal generator coupled to the electrode. The signal generator applies a DC pulse to the electrode with sufficient amplitude and sufficient duty cycle of an on-time and an off-time to cause events within the chamber. A plasma is generated from a gas in the chamber responsive to the amplitude of the DC pulse. Energetic ions are generated by accelerating ions of the plasma toward a substrate in the chamber in response to the amplitude of the DC pulse during the on-time. Some of the energetic ions are neutralized to energetic neutrals in response to the DC pulse during the off-time. Some of the energetic neutrals impact the substrate with sufficient energy to cause a chemical reaction on the substrate.
    Type: Application
    Filed: August 13, 2014
    Publication date: November 27, 2014
    Inventor: Neal R. Rueger
  • Patent number: 8877659
    Abstract: A method for repairing and lowering the dielectric constant of low-k dielectric layers used in semiconductor fabrication is provided. In one implementation, a method of repairing a damaged low-k dielectric layer comprising exposing the porous low-k dielectric layer to a vinyl silane containing compound and optionally exposing the porous low-k dielectric layer to an ultraviolet (UV) cure process.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: November 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kelvin Chan, Alexandros T. Demos
  • Publication number: 20140322927
    Abstract: A drawing apparatus includes: plural charged particle optical systems arrayed at a pitch in a first direction, each configured to irradiate a substrate with charged particle beams; a stage configured to hold the substrate and be moved relative to the charged particle optical systems in a second direction orthogonal to the first direction; and a controller configured to determine charged particle beams for the drawing with respect to each charged particle optical system so as to satisfy a relation given by SW=Pc/?=Ps/(? where Ps is an array pitch of shot regions in the first direction, SW is a width, in the first direction, of each drawing region by each charged particle optical system, Pc be an array pitch of drawing regions in the first direction, and ? and ? are natural numbers.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 30, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tomoyuki MORITA
  • Publication number: 20140312469
    Abstract: Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Inventors: Lawrence Shah, Gyu Cheon Cho, Jingzhou Xu
  • Patent number: 8859443
    Abstract: The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 14, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Kenichi Yokouchi
  • Publication number: 20140302621
    Abstract: A semiconductor device manufacturing method is disclosed by which electron beam irradiation is accomplished at a low cost while exhibiting uniform characteristics. A wafer stack consisting of multiple stacked wafers is irradiated with an electron beam from both the front surface and reverse surface. As such, a semiconductor device manufacturing method is provided whereby the electrical characteristics are extremely uniform between wafers, and costs are reduced by reducing the number of electron beam irradiations.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 9, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasushi NIIMURA
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Publication number: 20140273537
    Abstract: A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ching LO, Po-Hsiung LEU, Tzu-Chun LIN, Ding-I LIU, Jen-Chi CHANG, Ho-Ta CHUANG
  • Publication number: 20140273538
    Abstract: This disclosure relates to a plasma processing system for controlling plasma density near the edge or perimeter of a substrate that is being processed. The plasma processing system may include a plasma chamber that can receive and process the substrate using plasma for etching the substrate, doping the substrate, or depositing a film on the substrate. This disclosure relates to a plasma processing system that may be configured to enable non-ambipolar diffusion to counter ion loss to the chamber wall. The plasma processing system may include a ring cavity coupled to the plasma processing system that is in fluid communication with plasma generated in the plasma processing system. The ring cavity may be coupled to a power source to form plasma that may diffuse ions into the plasma processing system to minimize the impact of ion loss to the chamber wall.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Lee Chen, Zhiying Chen, Jianping Zhao, Merritt Funk
  • Publication number: 20140273536
    Abstract: A charged particle beam writing apparatus according to an embodiment includes: a beam emitter configured to emit a charged particle beam; an aperture having an opening portion through which the charged particle beam emitted by the beam emitter passes; an aperture beam tube being provided on a surface of the aperture and functioning as a thermally conductive member having thermal conductivity; and a heater provided on a surface of the aperture beam tube and configured to supply heat to the aperture via the aperture beam tube.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 18, 2014
    Applicant: NuFlare Technology, Inc.
    Inventor: Tetsuro NISHIYAMA
  • Patent number: 8828744
    Abstract: A method for etching trenches in an etch layer disposed below a patterned organic mask is provided. The patterned organic mask is treated, comprising flowing a treatment gas comprising H2 and N2, forming a plasma from the treatment gas, making patterned organic mask more resistant to wiggling, and stopping the flow of the treatment gas. Trenches are etched in the etch layer through the patterned organic mask.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Joseph J. Vegh, Yungho Noh
  • Patent number: 8822264
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Publication number: 20140213071
    Abstract: A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 31, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryusuke KAWAKAMI, Kenichirou NISHIDA, Norihito KAWAGUCHI, Miyuki MASAKI, Atsushi YOSHINOUCHI