Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: Certain example embodiments of this invention relate to a photovoltaic (PV) device including an electrode such as a front electrode/contact, and a method of making the same. In certain example embodiments, the front electrode has a textured (e.g., etched) surface that faces the photovoltaic semiconductor film of the PV device. The front electrode has a transparent conductive oxide (TCO) film having first and second layers (continuous or discontinuous) of the same material (e.g., zinc oxide, zinc aluminum oxide, indium-tin-oxide, or tin oxide), where the first TCO layer is sputter-deposited using a ceramic sputtering target(s) and the second TCO layer of the same material is sputter-deposited using a metallic or substantially metallic sputtering target(s). This allows the better quality TCO of the film, deposited more slowly via the ceramic target(s), to be formed using the ceramic target and the lesser quality TCO of the film to be deposited more quickly and cost effectively via the metallic target(s).

Abstract: Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.

Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.

Abstract: A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T1 at an arbitrary rate R1 (° C./sec); holding the temperature at the temperature T1 for an arbitrary period t1 (sec); increasing the temperature from the temperature T1 to a temperature T2 at a rate R2 (° C./sec) of 1.0×107 (° C./sec) or less; and holding the temperature at the temperature T2 for a period t2 (sec) of 50 msec or less. The thermal cycle thereafter includes: decreasing the temperature from the temperature T2 to the temperature T1 at a rate R1? (° C./sec) of 1.0×107 (° C./sec) or less; holding the temperature T1 for an arbitrary period t3 (sec); and decreasing the temperature from the temperature T1 to a final temperature at an arbitrary rate R2? (° C./sec). Such a thermal cycle is successively repeated in a plurality of iterations.

Abstract: The present invention provides means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.

Abstract: A semiconductor device manufacturing method prevents the occurrence of a short-circuit between leads caused by peeling-off of residual resin formed on lead side faces or lead lower portions. A laser beam is radiated a plurality of times from a main surface side of leads and also a plurality of times from a back surface side of the leads to intra-dam resin formed in a dam portion, the dam portion being enclosed with adjacent leads, a dam bar and a sealing body, thereby removing all the intra-dam resin formed on lead side faces and lead lower portions. The laser beam radiation of the intra-dam resin may leave behind a sealing body-side resin portion and a projecting resin portion which projects outwardly from the sealing body.

Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.

Abstract: An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.

Abstract: Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.

Abstract: A method of implanting atoms and/or ions into a substrate, including: a) a first implantation of ions or atoms at a first depth in the substrate, to form a first implantation plane, b) at least one second implantation of ions or atoms at a second depth in the substrate, which is different from the first depth, to form at least one second implantation plane.

Abstract: Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous layer. A plasma can then be used to react a plurality of second molecules with the first layer of first molecules to form a first layer of a barrier layer. The barrier layers can seal the pores of the porous material, function as a diffusion barrier, be conformal, and/or have a negligible impact on the overall ILD k value of the porous material.

Abstract: A method of producing an array of electronic devices, the method including the steps of: forming one or more first conductive elements of a first electronic device on a substrate and one or more second conductive elements of a second electronic device on said substrate; and forming a layer of channel material over the substrate and the first and second conductive elements to provide a first channel for, in use, the movement of charge carriers between conductive elements of said first electronic device and a second channel for, in use, the movement of charge carriers between conductive elements of said second electronic device; wherein the method also includes the step (a) of using an irradiative technique to decrease in a single step the conductivity of one or more selected portions of the layer of channel material in one or more regions between the first and second conductive elements.

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

Abstract: Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry.

Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.

Abstract: A microwave heating system comprises a microwave applicator cavity; a microwave power supply to deliver power to the applicator cavity; a dielectric support to support a generally planar workpiece; a dielectric gas manifold to supply a controlled flow of inert gas proximate to the periphery of the workpiece to provide differential cooling to the edge relative to the center; a first temperature measuring device configured to measure the temperature near the center of the workpiece; and, a second temperature measuring device configured to measure the temperature near the edge of the workpiece. The gas flow is controlled to minimize the temperature difference from center to edge, and may be recipe driven or controlled in real time, based on the two temperature measurements. The method is particularly useful for monolithic semiconductor wafers, various semiconducting films on substrates, and dielectric films on semiconducting wafers.

Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.

Abstract: A method for ashing hardened resist from a photoresist patterned chromium alloy post etch using a plasma ashing chemistry which contains no gaseous source of hydrogen and contains a gaseous source of oxygen and a gaseous source of nitrogen with an oxygen to nitrogen atomic ratio of at least 5.

Abstract: A system for shielding personnel and/or equipment from radiation particles. In one embodiment, a first substrate is connected to a first array or perpendicularly oriented metal-like fingers, and a second, electrically conducting substrate has an array of carbon nanostructure (CNS) fingers, coated with an electro-active polymer extending toward, but spaced apart from, the first substrate fingers. An electric current and electric charge discharge and dissipation system, connected to the second substrate, receives a current and/or voltage pulse initially generated when the first substrate receives incident radiation. In another embodiment, an array of CNSs is immersed in a first layer of hydrogen-rich polymers and in a second layer of metal-like material. In another embodiment, a one- or two-dimensional assembly of fibers containing CNSs embedded in a metal-like matrix serves as a radiation-protective fabric or body covering.

Abstract: A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.

Abstract: An object is to provide a method for manufacturing an SOI substrate including a semiconductor film with high planarity and high crystallinity. After a single crystal semiconductor film is formed over an insulating film by a separation step, a natural oxide film existing on a surface of the semiconductor film is removed and the semiconductor film is irradiated with first laser light and second laser light under an inert gas atmosphere or a reduced-pressure atmosphere. The number of shots of the first laser light that is emitted to an arbitrary point in the semiconductor film is greater than or equal to 7, preferably greater than or equal to 10 and less than or equal to 100. The number of shots of the second laser light that is emitted to an arbitrary point in the semiconductor film is greater than 0 and less than or equal to 2.

Abstract: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

Abstract: A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process.

Abstract: Methods for treating a substrate in preparation for a subsequent process are presented, the method including: receiving the substrate, the substrate comprising conductive regions and dielectric regions; and applying an oxidizing agent to the substrate in a manner so that the dielectric regions are oxidized to become increasingly hydrophilic to enable access to the conductive regions in the subsequent process, wherein the dielectric region is treated to a depth in the range of approximately 1 to 5 atomic layers. In some embodiments, methods further include processing the substrate, wherein processing the conductive regions are selectively enhanced. In some embodiments, the oxidizing agent includes atmospheric pressure plasma and UV radiation.

Abstract: A system and method is described for applying a pre-gate plasma etch in a semiconductor device manufacturing process in order to increase the integrity of a subsequently grown gate oxide layer. During the manufacture of a semiconductor device a sacrificial oxide layer is grown over a silicon substrate. The pre-gate plasma etch process is applied to the sacrificial oxide layer. Then the sacrificial oxide layer is stripped away and a gate oxide layer is grown over the silicon substrate. The gate oxide layer has an increased integrity due to the application of the pre-gate plasma etch process.

Abstract: It is an object of the present invention to provide a laser irradiation technique which can keep the stability of the laser oscillator high and which can perform laser process homogeneously by avoiding the adverse effect due to the return light reflected on an irradiation when, for example, crystallizing with a lens array, and to provide a crystallization method and a method for manufacturing a semiconductor device which use the technique. In the present invention, a laser beam emitted from a laser oscillator is divided into a plurality of beams through a lens array such as a cylindrical lens array, the divided beams pass through opening portions of a slit while being focused at the opening portions and condensed beam is irradiated to an irradiation surface. Thus, the light reflected on the irradiation object can be blocked by using the slit.

Abstract: A film forming method includes the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio larger than 1 smaller than 2, the F/C ratio being defined as a ratio of a number of F atoms to a number of C atoms in a source gas molecule.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.

Abstract: A substrate processing apparatus is used for radiating UV rays onto a target film formed on a target surface of a substrate to perform a curing process of the target film. The apparatus includes a hot plate configured to heat the substrate to a predetermined temperature, a plurality of support pins disposed on the hot plate to support the substrate, and a UV radiating device configured to radiate UV rays onto the target surface of the substrate supported on the support pins. The support pins are preset to provide a predetermined thermal conductivity to conduct heat of the substrate to the hot plate. The hot plate is preset to have a predetermined thermal capacity sufficient to absorb heat conducted through the support pins.

Abstract: The main object of the present invention is to provide a method for manufacturing efficiently a pattern formed structure which has a surface having a property-varied pattern and can be used to manufacture a color filter or the like. In order to achieve the object, the present invention provides a method for manufacturing a pattern formed structure, comprising: a patterning substrate preparing process of preparing a patterning substrate having a base material and a property variable layer which is formed on the base material and has a property variable by action of a photocatalyst based on irradiation with energy; and an energy radiating process of arranging a photocatalyst containing layer side substrate having a base body and a photocatalyst containing layer comprising at least the photocatalyst, and the patterning substrate so as to keep a given interval between the photocatalyst containing layer and the property variable layer, and then radiating energy onto the resultant at an intensity of 0.

Abstract: A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: A method for manufacturing a semiconductor substrate including: epitaxially growing a silicon germanium (SiGe) film on a silicon (Si) substrate by a chemical vapor deposition method; subjecting a heat treatment to the SiGe film at a temperature of not less than 700° C. and not more than 1200° C.; implanting hydrogen ions into a surface of the SiGe film; subjecting a surface activation treatment to a main surface of at least one of the SiGe film and a support substrate; bonding main surfaces of the SiGe film and the support substrate at a temperature of not less than 100° C. and not more than 400° C.; and applying an external impact to a bonding interface between the SiGe film and the support substrate to delaminate the SiGe crystal along a hydrogen ion implanted interface of the SiGe film, thereby forming a SiGe thin film on the main surface of the support substrate.

Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.

Abstract: A coherent beam source, e.g., a laser having a cavity that is unstable in at least one direction, is used to produce a coherent beam having an initial intensity profile. The beam is passed through a relay having a Fourier plane containing a spatial filter that serves as a radiation defining mask. The filter has an aperture size and shape effective to modify the beam such that the modified beam forms an image on a substrate. The to image has an intensity profile that more closely approximates a super-Gaussian profile than the initial profile. For example, when the initial intensity profile is Gaussian, the spatial filter may allow passage of only unattenuated the central core of the beam and block completely blocks the wings of the Guassian profile. The modified beam may be more suitable for use in a scanning system used to anneal wafers or other substrates containing integrated circuits.

Abstract: A method of producing a semiconductor device, including: a first plasma processing step of processing a surface of a resin layer laid on a semiconductor element and containing silicon, with a first plasma generated from a gas containing oxygen and fluorine, thereby forming an oxide film; and an electrode pad forming step of forming an electrode pad of a metal on the oxide film.

Abstract: A plasma processing method performs a desired plasma process on substrates by using a plasma generated in a processing space. A first and a second electrode are disposed in parallel in a processing vessel that is grounded, the substrate is supported on the second electrode to face the first electrode, the processing vessel is vacuum evacuated, a desired processing gas is supplied into the processing space formed between the first electrode, the second electrode and a sidewall of the processing vessel, and a first radio frequency power is supplied to the second electrode. The first electrode is connected to the processing vessel via an insulator or a space, and is electrically coupled to a ground potential via a capacitance varying unit whose electrostatic capacitance is varied based on a process condition of the plasma process performed on the substrate.

Abstract: Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature.

Abstract: A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ?5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

Abstract: A dielectric insulating film including HfO or the like is formed by: cleaning a surface of a semiconductor substrate by exposing the substrate surface to a fluorine radical; performing hydrogen termination processing with a fluorine radical or a hydride (SiH4 or the like); sputtering Hf or the like; and then performing oxidation/nitridation. These steps are carried out without exposing the substrate to atmosphere, thereby making it possible to obtain a C-V curve with less hysteresis and realize a MOS-FET having favorable device characteristics.

Abstract: Among others, techniques are described for forming nanotubes. In one aspect, a method includes forming a base layer of a transition metal on a substrate. The method also includes heating the substrate with the base layer in a mixture of gases to grow nanotubes on the base layer.

Abstract: Provided are a method of evaluating an ion irradiation effect, a process simulator and a device simulator, which allow the influence of ion irradiation on atoms making up a substrate to be evaluated with high accuracy. The method includes irradiating a sample with a beam of ions, and evaluating influence of the ions used for the irradiation on atoms making up the sample, provided that the sample is prepared by alternately and periodically stacking a plurality of thin film layers, and of the plurality of thin film layers, the layer of at least one kind is composed of an isotope layer.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Abstract: It is presented an organic LED device 101 with, when in use, a predetermined pattern on its light emitting parts. The organic LED device 101 comprises an anode 105, a cathode 103, and an organic light emitting layer 107. The organic light emitting layer 107 is configured to emit light, wherein the organic light emitting layer 107 comprises portion with reduced light emitting properties, the portions of the organic light emitting layer 107 having been irradiated by light with a wavelength in the absorption band of the organic light emitting layer 107, the light intensity being below an ablation threshold of the cathode layer 103, the anode layer 105 and the organic light emitting layer 107 of the organic LED device 101, reducing the light emitting properties of the irradiated portions of the organic light emitting layer 107. It is also presented a method for reducing the light emitting properties of the organic LED device 101.

Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.