Ionized Irradiation (e.g., Corpuscular Or Plasma Treatment, Etc.) Patents (Class 438/798)
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Patent number: 7795154Abstract: To provide a manufacturing apparatus of a semiconductor device, which does not use a stepper in a manufacturing process in the case where mass production of semiconductor devices is carried out by using a large-sized substrate. A thin film formed over a substrate having an insulating surface is selectively irradiated with a laser beam through light control means, specifically through an electro-optical device to cause ablation; accordingly, the thin film is partially removed, thereby processing the thin film in a remaining region into a desired shape. The electro-optical device functions as a variable mask by inputting an electrical signal based on design CAD data of the semiconductor device.Type: GrantFiled: August 21, 2007Date of Patent: September 14, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Tanaka, Shunpei Yamazaki
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Publication number: 20100221905Abstract: A method of preparing a floating trap type device on a substrate is described. The method comprises forming a trap layer structure on a substrate, and modifying a composition of one or more layers in the trap layer structure by exposing the trap layer structure to a gas cluster ion beam (GCIB).Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Applicant: TEL Epion Inc.Inventors: John J. Hautala, Mitchell A. Carlson
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Patent number: 7785978Abstract: A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.Type: GrantFiled: February 4, 2009Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventor: John Smythe
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Patent number: 7781234Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.Type: GrantFiled: November 28, 2006Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Won-bae Jang, Seung-chul Kim, Chan-seung Choi, Min-suk Kim, Chee-wan Kim, Sun-yong Lee, Sang-rok Hah
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Publication number: 20100200953Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.Type: ApplicationFiled: April 23, 2010Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, Alvin W. Strong
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Publication number: 20100197147Abstract: High throughput systems and processes for recrystallizing thin film semiconductors that have been deposited at low temperatures on a substrate are provided. A thin film semiconductor workpiece is irradiated with a laser beam to melt and recrystallize target areas of the surface exposed to the laser beam. The laser beam is shaped into one or more beamlets using patterning masks. The mask patterns have suitable dimensions and orientations to pattern the laser beam radiation so that the areas targeted by the beamlets have dimensions and orientations that are conducive to semiconductor recrystallization. The workpiece is mechanically translated along linear paths relative to the laser beam to process the entire surface of the work piece at high speeds. Position sensitive triggering of a laser can be used generate laser beam pulses to melt and recrystallize semiconductor material at precise locations on the surface of the workpiece while it is translated on a motorized stage.Type: ApplicationFiled: February 18, 2010Publication date: August 5, 2010Inventor: JAMES S. IM
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Publication number: 20100190356Abstract: A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be positioned below the plasma generating unit. A reflector may be arranged below the grid system and may include parallel reflecting plates for converting the ions accelerated from the grid system into neutral beams.Type: ApplicationFiled: March 4, 2010Publication date: July 29, 2010Inventors: Sung-Wook Hwang, Chul-Ho Shin
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Patent number: 7763869Abstract: A UV light irradiating apparatus for irradiating a semiconductor substrate with UV light includes: a reactor in which a substrate-supporting table is provided; a UV light irradiation unit connected to the reactor for irradiating a semiconductor substrate placed on the substrate-supporting table with UV light through a light transmission window; and a liquid layer forming channel disposed between the light transmission window and at least one UV lamp for forming a liquid layer through which the UV light is transmitted. The liquid layer is formed by a liquid flowing through the liquid layer forming channel.Type: GrantFiled: March 23, 2007Date of Patent: July 27, 2010Assignee: ASM Japan K.K.Inventors: Kiyohiro Matsushita, Kenichi Kagami
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Publication number: 20100173476Abstract: A method for manufacturing a semiconductor device according to the invention irradiates a first pulse laser beam with an irradiation energy density of 1.0 J/cm2 or higher to blow off particles on the surface of wafer in activating an impurity layer positioned at a shallow location from the surface of wafer such as pt-type collector layer in an FS-type IGBT or in an NPT-type IGBT. By irradiating a second laser beam, region, on which particles were, is activated in the same manner as the region, on which particles are not, and pt-type collector layer is formed uniformly. The manufacturing method according to the invention facilitates preventing nonuniform laser beam irradiation from causing in laser annealing and preventing defective devices from causing.Type: ApplicationFiled: December 11, 2009Publication date: July 8, 2010Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventor: Haruo Nakazawa
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Patent number: 7745351Abstract: Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.Type: GrantFiled: October 15, 2008Date of Patent: June 29, 2010Assignee: Applied Materials, Inc.Inventors: Xiaolin Chen, Srinivas D. Nemani, DongQing Li, Jeffrey C. Munro, Marlon E. Menezes
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Publication number: 20100159618Abstract: In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described.Type: ApplicationFiled: February 16, 2010Publication date: June 24, 2010Applicant: Brookhaven Science Associates, LLCInventors: Eli Anguelova Sutter, Peter Werner Sutter
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Publication number: 20100159712Abstract: A method of modifying the heat transfer coefficient profile of an electrostatic chuck by configuring the areal density of a mesa configuration of an insulating layer of the chuck is provided. A method of modifying the capacitance profile of an electrostatic chuck by adjustment or initial fabrication of the height of a mesa configuration of an insulating layer of the chuck is further provided. The heat transfer coefficient at a given site can be measured by use of a heat flux probe, whereas the capacitance at a given site can be measured by use of a capacitance probe. The probes are placed on the insulating surface of the chuck and may include a plurality of mesas in a single measurement. A plurality of measurements made across the chuck provide a heat transfer coefficient profile or a capacitance profile, from which a target mesa areal density and a target mesa height are determined.Type: ApplicationFiled: November 30, 2005Publication date: June 24, 2010Inventor: Robert Steger
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Publication number: 20100151696Abstract: A manufacturing method for a semiconductor device, includes, forming an element region on a front surface of a semiconductor substrate, performing a first heat treatment by irradiating first irradiation light having a first irradiation energy density onto the front surface of the semiconductor substrate with a pulse width of 0.1 to 100 msec at the temperature of 1000° C. or less; and performing a second heat treatment by irradiating second irradiation light having a second irradiation energy density onto the surface of the semiconductor substrate with a pulse width of 0.1 to 100 msec at the temperature higher than the temperature in the first heat treatment.Type: ApplicationFiled: December 10, 2009Publication date: June 17, 2010Inventors: Takayuki ITO, Masato Fukumoto, Kunihiro Miyazaki
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Patent number: 7737010Abstract: A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the semiconductor substrate, implanting a dopant into the semiconductor substrate, and removing a dopant-containing layer from the photoresist layer. The dopant-containing layer includes dopant residuals and a carbon-rich crust and may be formed during implantation. The dopant-containing layer may be removed from the photoresist layer by exposing the dopant-containing layer to a water rinse, a chlorinated plasma or to a fluorinated plasma. The water rinse may include deionized water that is maintained at a temperature that ranges from approximately 25° C. to approximately 80° C. The fluorinated plasma may be formed from a gaseous precursor selected from the group consisting of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, sulfur hexafluoride, and mixtures thereof.Type: GrantFiled: April 14, 2006Date of Patent: June 15, 2010Assignee: Micron Technology, Inc.Inventors: Shu Qin, Allen McTeer, Robert J. Hanson
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Patent number: 7713757Abstract: Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the substrate and transmitting a light generated by the plasma through the substrate, wherein the light enters the topside and exits the backside of the substrate, and receiving the light by a sensor positioned below the substrate. The method further provides generating a signal proportional to the light received by the sensor, implanting the substrate with a dopant during a doping process, generating multiple light signals proportional to a decreasing amount of the light received by the sensor during the doping process, generating an end point signal proportional to the light received by the sensor once the substrate has a final dopant concentration, and ceasing the doping process.Type: GrantFiled: March 14, 2008Date of Patent: May 11, 2010Assignee: Applied Materials, Inc.Inventors: Majeed A. Foad, Shijian Li
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Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation
Publication number: 20100112825Abstract: Methods and apparatus provide for forming a semiconductor-on-insulator (SOI) structure, including subjecting a implantation surface of a donor semiconductor wafer to an ion implantation step to create a weakened slice in cross-section defining an exfoliation layer of the donor semiconductor wafer; and subjecting the donor semiconductor wafer to a spatial variation step, either before, during or after the ion implantation step, such that at least one parameter of the weakened slice varies spatially across the weakened slice in at least one of X- and Y-axial directions.Type: ApplicationFiled: October 30, 2008Publication date: May 6, 2010Inventors: Sarko Cherekdjian, Jeffrey Scott Cites, James Gregory Couillard, Richard Orr Maschmeyer, Michael John Moore, Alex Usenko -
Patent number: 7709814Abstract: Apparatuses and processes for treating dielectric materials such as low k dielectric materials, premetal dielectric materials, barrier layers, and the like, generally comprise a radiation source module, a process chamber module coupled to the radiation source module; and a loadlock chamber module in operative communication with the process chamber and a wafer handler. The atmosphere of each one of the modules can be controlled as may be desired for different types of dielectric materials. The radiation source module includes a reflector, an ultraviolet radiation source, and a plate transmissive to the wavelengths of about 150 nm to about 300 nm, to define a sealed interior region, wherein the sealed interior region is in fluid communication with a fluid source.Type: GrantFiled: June 17, 2005Date of Patent: May 4, 2010Assignee: Axcelis Technologies, Inc.Inventors: Carlo Waldfried, Christopher Garmer, Orlando Escorcia, Ivan Berry, III, Palani Sakthivel, Alan C. Janos
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Publication number: 20100055882Abstract: Methods for producing a junction termination extension surrounding the edge of a cathode or anode junction in a semiconductor substrate, where the junction termination extension has a controlled arbitrary lateral doping profile and a controlled arbitrary lateral width, are provided. A photosensitive material is illuminated through a photomask having a pattern of opaque and clear spaces therein, the photomask being separated from the photosensitive material so that the light diffuses before striking the photosensitive material. After processing, the photosensitive material so exposed produces a laterally tapered implant mask. Dopants are introduced into the semiconductor material and follow a shape of the laterally tapered implant mask to create a controlled arbitrary lateral doping profile and a controlled lateral width in the junction termination extension in the semiconductor.Type: ApplicationFiled: July 6, 2009Publication date: March 4, 2010Applicant: The Government of the United States of America, as rpresented by the Secretary of the NavyInventors: Eugene A. Imhoff, Francis J. Kub, Karl D. Hobart
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Patent number: 7667212Abstract: Certain film deposition and selective etching technology may involve scanning of a charged particle beam along with a deposition gas and etching gas, respectively. In conventional methods, unfortunately, the deposition rate or the selective ratio is oftentimes decreased depending on optical system setting, scan spacing, dwell time, loop time, substrate, etc. Accordingly, an apparatus is provided for finding an optical system setting, a dwell time, and a scan spacing. These parameters are found to realize the optimal scanning method of the charged particle beam from the loop time dependence of the deposition rate or etching rate. This deposition rate or etching rate are measurements stored in advance for a desired irradiation region where film deposition or selective etching should be performed. The apparatus displays a result of its judgment on a display device.Type: GrantFiled: October 31, 2008Date of Patent: February 23, 2010Assignee: Hitachi High-Technologies CorporationInventors: Muneyuki Fukuda, Hiroyasu Shichi
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Publication number: 20100041216Abstract: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.Type: ApplicationFiled: October 20, 2009Publication date: February 18, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Ming Lai, Jenq-Dar Tsay, Wen-Yueh Liu, Yih-Der Guo
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Patent number: 7662728Abstract: A method of forming a low-K dielectric film, comprises the steps of placing a substrate carrying thereon a low-K dielectric film on a stage, heating the low-K dielectric film on the stage, processing the low-K dielectric film by plasma of a processing gas containing a hydrogen gas, the plasma being excited while supplying the processing gas over the low-K dielectric film, wherein the plasma is excited within 90 seconds after placing the substrate upon the stage.Type: GrantFiled: May 11, 2006Date of Patent: February 16, 2010Assignee: Tokyo Electron LimitedInventors: Yusaku Kashiwagi, Yasuhiro Oshima, Yoshihisa Kagawa, Gishi Chung
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Patent number: 7655578Abstract: Under consideration here is a method for the production of periodic nanostructuring on one of the surfaces of a substrate (10), presenting a periodic network of dislocations, embedded within a crystalline area (4) located in the neighborhood of an interface (5) between the crystalline material surfaces of two components (1, 2) assembled by bonding to form the substrate (10). It comprises the following steps: formation, in the dislocations (3), of implants (6) made of a material other than that of the crystalline area (4); irradiation of the substrate (10) with electromagnetic waves (11) in order to cause absorption of electromagnetic energy localized in the implants (6), this absorption leading to the appearance of the periodic nanostructuring (12) on the surface of the substrate (10).Type: GrantFiled: July 3, 2007Date of Patent: February 2, 2010Assignees: Commissariat a l'Energie Atomique, Universite Jean Monnet, Centre National de la Recherche ScientifiqueInventors: Frank Fournel, Jérôme Meziere, Alexis Bavard, Florent Pigeon, Florence Garrelie
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Patent number: 7655579Abstract: A focus ring heat transfer method improves heat transfer of a focus ring arranged in an outer peripheral portion of a mounting surface of a mounting table adapted to mount a target substrate in a chamber. The method includes steps of: disposing a heat transfer sheet between the focus ring and the mounting table; and vacuum-evacuating the chamber prior to processing the target substrate and then restoring the pressure the inside of the chamber to an atmospheric pressure or a light vacuum pressure. Therefore, air present in a fine gap between the heat transfer sheet and the mounting surface is removed to allow the heat transfer sheet to adhere to the mounting surface.Type: GrantFiled: January 8, 2008Date of Patent: February 2, 2010Assignee: Tokyo Electron LimitedInventors: Masaaki Miyagawa, Akihiro Yoshimura
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Publication number: 20100015818Abstract: A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, the method including providing a semiconductor body having a first and a second side and a basic doping of a first conduction type. The method further includes irradiating the semiconductor body via one of the sides with protons, as a result of which protons are introduced into a first region of the semiconductor body situated at a distance from the irradiation side. The method also includes carrying out a thermal process in which the semiconductor body is heated to a predetermined temperature for a predetermined time duration, the temperature and the duration being chosen such that hydrogen-induced donors are generated both in the first region and in a second region adjacent to the first region in the direction of the irradiation side.Type: ApplicationFiled: August 31, 2009Publication date: January 21, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Reiner Barthelmess, Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze
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Publication number: 20100009550Abstract: [PROBLEMS] To provide a method and an apparatus for cutting a conductive link of a redundant circuit in a semiconductor circuit. [MEANS FOR SOLVING PROBLEMS] A method is provided for selectively cutting a plurality of conductive links embedded in a protection layer which covers at least the conductive links in a semiconductor device formed on a semiconductor substrate. A focused beam is aligned with a target link, a first pulsed laser beam having a short laser wavelength of 400 nm or shorter and a second pulsed laser beam having a wavelength longer than 400 nm are generated, the first and the second pulsed laser beams are overlapped and applied onto the conductive link from over the protection layer. Preferably, the second pulsed laser is applied after the first pulsed layer in terms of time.Type: ApplicationFiled: December 7, 2007Publication date: January 14, 2010Applicants: CYBER LASER, INC., MEERE COMPANY, INC.Inventors: Susumu Tsujikawa, Masanao Kamata, Tetsumi Sumiyoshi
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Publication number: 20100009551Abstract: A p-n junction is formed at the interface of a low-concentration n-type impurity layer and a p-type diffusion region in the vicinity of the upper major surface of an n-type semiconductor substrate of a semiconductor device. A mask composed of an absorber is placed on the upper major surface of the semiconductor device, and electron beams are radiated. Thereafter, heat treatment is conducted. As a result, the peak of the crystal lattice defect densities is present in the vicinity of the upper major surface of the n-type semiconductor substrate, and the crystal lattice defect densities are decreasingly distributed toward the lower major surface. Thereby, a semiconductor device that can minimize the variation of the breakdown voltage characteristics of the p-n junction of the diode, and can control the optimum carrier lifetime can be obtained.Type: ApplicationFiled: September 23, 2009Publication date: January 14, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Masanori INOUE
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Patent number: 7642192Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.Type: GrantFiled: April 26, 2005Date of Patent: January 5, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Kazuo Hashimi, Hidekazu Sato
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Patent number: 7635640Abstract: A crystallization method of an amorphous semiconductor layer includes providing an amorphous semiconductor layer having a first thickness, crystallizing the amorphous semiconductor layer in a first direction, partially reducing the crystallized semiconductor layer to a second thickness less than the first thickness and crystallizing the etched semiconductor layer in a second direction.Type: GrantFiled: April 19, 2006Date of Patent: December 22, 2009Assignee: LG Display Co., Ltd.Inventor: Sang Hyun Kim
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Patent number: 7629596Abstract: To provide production methods for a 3-D mold, a finely processed product, and a fine pattern molded product in which the depth and the line width can be formed with high precision, a 3-D mold, a finely processed product, a fine-pattern molded product, and an optical element formed with high precision.Type: GrantFiled: February 21, 2006Date of Patent: December 8, 2009Assignee: Tokyo University of Science Educational Foundation Administrative OrganizationInventor: Jun Taniguchi
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Patent number: 7629274Abstract: A storage node, a method of fabricating the same, a semiconductor memory device and a method of fabricating the same is provided. The method of fabricating a storage node may include forming a lower electrode, forming an irradiated data storage layer and forming an upper electrode.Type: GrantFiled: August 24, 2006Date of Patent: December 8, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyun Lee, Sang-Bong Bang
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Patent number: 7629196Abstract: A method is disclosed for manufacturing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of the integrated circuit. In one advantageous embodiment the radiation resistant material is silicon carbide. In another advantageous embodiment a passivation layer is placed between the device active area and the layer of radiation resistant material. The integrated circuit of the present invention exhibits minimal sensitivity to (1) enhanced low dose rate sensitivity (ELDRS) effects of radiation, and (2) pre-irradiation elevated temperature stress (PETS) effects of radiation.Type: GrantFiled: October 15, 2007Date of Patent: December 8, 2009Assignee: National Semiconductor CorporationInventor: Michael C. Maher
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Patent number: 7618880Abstract: A method is disclosed for forming a layer of a wide bandgap material in a non-wide bandgap material. The method comprises providing a substrate of a non-wide bandgap material and converting a layer of the non-wide bandgap material into a layer of a wide bandgap material. An improved component such as wide bandgap semiconductor device may be formed within the wide bandgap material through a further conversion process.Type: GrantFiled: February 18, 2005Date of Patent: November 17, 2009Inventor: Nathaniel R. Quick
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Patent number: 7605084Abstract: A method of filling a gap on a substrate comprises disposing the substrate, on which the gap is formed, on a susceptor in a chamber; applying a source power to the chamber to generate plasmas into the chamber; supplying a process gas into the chamber; filling a thin film into a gap by applying a first bias power to the susceptor, an amplitude of the first bias power being periodically modulated; stopping supply of the process gas and cutting off the first bias power; and extinguish the plasmas in the chamber.Type: GrantFiled: May 9, 2007Date of Patent: October 20, 2009Assignee: Jusung Engineering Co., Ltd.Inventors: Jeong-Hoon Han, Jin-Hyuk Yoo, Young-Rok Kim
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Publication number: 20090258507Abstract: In order to solve the problem of contamination caused by static electricity on the surface of a substrate after plasma treatment, the invention provides a substrate treatment device comprising a standby chamber in which is arranged a transfer device for loading a substrate out of/into a cassette rack accommodating a substrate, said substrate treatment device capable of retaining said substrate transferred by the transfer device in a boat and loading, by way of a boat elevator, the boat into/out of a treatment furnace capable of applying plasma treatment to said substrate, wherein a static eliminator for eliminating static electricity of said substrate is arranged in said standby chamber.Type: ApplicationFiled: March 2, 2007Publication date: October 15, 2009Inventors: Takeshi Itoh, Kazuyuki Toyoda, Yuji Takebayashi
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Patent number: 7588803Abstract: According to one embodiment of the invention, a method of modifying a mechanical, physical and/or electrical property of a dielectric layer comprises exposing the dielectric layer to a first dose of electron beam radiation at a first energy level; and thereafter, exposing the dielectric layer to a second dose of electron beam radiation at a second energy level that is different from the first energy level.Type: GrantFiled: February 1, 2005Date of Patent: September 15, 2009Assignee: Applied Materials, Inc.Inventors: Alexandros T. Demos, Li-Qun Xia, Tzu-Fang Huang, Wen H. Zhu
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Patent number: 7585704Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.Type: GrantFiled: April 1, 2005Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Michael P. Belyansky, Oleg Gluschenkov, Ying Li, Anupama Mallikarjunan
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Patent number: 7582492Abstract: The invention provides a method of doping impurities that includes a step of doping impurities in a solid base substance by using a plasma doping method, a step of forming a light antireflection layer that functions to reduce light reflection on the surface of the solid base substance, and a step of performing annealing by light radiation. According to the method, it is possible to reduce the reflectance of light radiated during annealing, to efficiently apply energy an impurity doped layer, to improve activation efficiency, to prevent diffusion, and to reduce sheet resistance of the impurity doped layer.Type: GrantFiled: May 19, 2005Date of Patent: September 1, 2009Assignee: Panasonic CorporationInventors: Cheng-Guo Jin, Yuichiro Sasaki, Bunji Mizuno, Katsumi Okashita, Hiroyuki Ito, Tomohiro Okumura, Satoshi Maeshima, Ichiro Nakayama
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Patent number: 7579287Abstract: A method for processing an object containing moisture is provided to efficiently remove the moisture and to prevent re-adsorption of the moisture. In particular, the method has a step of removing the moisture contained in the object in an atmosphere containing excited hydrogen, deuterium, deuterated hydrogen, or tritium.Type: GrantFiled: August 9, 2006Date of Patent: August 25, 2009Assignee: Canon Kabushiki KaishaInventors: Shigenori Ishihara, Nobuo Kawase
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Patent number: 7576341Abstract: A lithography system and method for operating the same. The lithography system may include a cathode adapted to emit an electron beam, a beam-homogenizing structure, capable of increasing at least one of the uniformity and energetic of the electron beam, and a mask adapted to accelerate the electron beam to form a pattern on a wafer.Type: GrantFiled: December 8, 2005Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Wook Kim, Sungho Jin, In Kyung Yoo
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Publication number: 20090203190Abstract: A method of forming a mask stack pattern and a method of manufacturing a flash memory device including an active area having rounded corners are provided. The method of manufacture including forming a mask stack pattern defining an active region, the mask stack pattern having a pad oxide layer formed on a semiconductor substrate, a silicon nitride layer formed on the pad oxide layer and a stack oxide layer formed on the silicon nitride layer, oxidizing a surface of the semiconductor substrate exposed by the mask stack pattern and lateral surfaces of the silicon nitride layer such that corners of the active region are rounded, etching the semiconductor substrate having an oxidized surface to form a trench in the semiconductor substrate, forming a device isolation oxide layer in the trench, removing the silicon nitride layer from the semiconductor substrate, and forming a gate electrode in a portion where the silicon nitride layer is removed.Type: ApplicationFiled: January 26, 2009Publication date: August 13, 2009Inventors: Young-jin Noh, Si-young Choi, Bon-young Koo, Ki-hyun Hwang, Chul-sung Kim, Sung-kweon Baek, Jin-hwa Heo
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Patent number: 7566482Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.Type: GrantFiled: September 30, 2003Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
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Publication number: 20090186469Abstract: There is proposed an apparatus for doping a material to be doped by generating plasma (ions) and accelerating it by a high voltage to form an ion current is proposed, which is particularly suitable for processing a substrate having a large area. The ion current is formed to have a linear sectional configuration, and doping is performed by moving a material to be doped in a direction substantially perpendicular to the longitudinal direction of a section of the ion current.Type: ApplicationFiled: April 1, 2009Publication date: July 23, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Toshiji Hamatani, Koichiro Tanaka
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Patent number: 7563718Abstract: A semiconductor substrate is loaded into a reaction chamber to form a tungsten layer. A source gas including tungsten (W) is introduced into the reaction chamber to grow a crystal nucleus of the tungsten on the semiconductor substrate. A reduction gas containing boron (B) is introduced into the reaction chamber to form a tungsten layer on the semiconductor substrate by actions of the source gas and the reduction gas. A hydrogen (H2) gas is introduced into the reaction chamber to remove the boron (B) remaining in the tungsten layer.Type: GrantFiled: December 29, 2006Date of Patent: July 21, 2009Assignee: Hynix Semiconductor Inc.Inventor: Choon Hwan Kim
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Patent number: 7560366Abstract: The present invention provides processes for producing horizontal nanowires that are separate and oriented and allow for processing directly on a substrate material. The nanowires grow horizontally by suppressing vertical growth from a nucleating particle, such as a metal film. The present invention also provides for horizontal nanowire growth from nucleating particles on the edges of nanometer-sized steps. Following processing, the nanowires can be removed from the substrate and transferred to other substrates. The present invention also provides for nanowires produced by these processes and electronic devices comprising these nanowires. The present invention also provides for nanowire growth apparatus that provide horizontal nanowires, and processes for producing nanowire devices.Type: GrantFiled: December 1, 2005Date of Patent: July 14, 2009Assignee: Nanosys, Inc.Inventors: Linda T. Romano, Shahriar Mostarshed
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Patent number: 7557050Abstract: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.Type: GrantFiled: September 23, 2005Date of Patent: July 7, 2009Assignee: Samsung Electroncis Co., Ltd.Inventors: Se-Jin Chung, Chi-Woo Kim, Ui-Jin Chung, Dong-Byum Kim
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Patent number: 7553772Abstract: Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.Type: GrantFiled: January 31, 2005Date of Patent: June 30, 2009Assignee: LSI CorporationInventors: Shiqun Gu, Wai Lo, Hong Lin
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Publication number: 20090159881Abstract: The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip 10 within a shot, which is a segmented region of the wafer, by a fixed pattern method. In addition, an information bit uniquely given to each shot within the wafer is written by a mask shift method. Further, an information bit uniquely given to each wafer is written in a wafer discrimination block of the chip 10 which is fabricated on the wafer by the mask shift method and mask combination method.Type: ApplicationFiled: August 7, 2008Publication date: June 25, 2009Inventors: Hidehiko KANDO, Isao Sakama
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Publication number: 20090156019Abstract: A substrate processing apparatus is used for radiating UV rays onto a target film formed on a target surface of a substrate to perform a curing process of the target film. The apparatus includes a hot plate configured to heat the substrate to a predetermined temperature, a plurality of support pins disposed on the hot plate to support the substrate, and a UV radiating device configured to radiate UV rays onto the target surface of the substrate supported on the support pins. The support pins are preset to provide a predetermined thermal conductivity to conduct heat of the substrate to the hot plate. The hot plate is preset to have a predetermined thermal capacity sufficient to absorb heat conducted through the support pins.Type: ApplicationFiled: June 4, 2008Publication date: June 18, 2009Inventors: Naoyuki Satoh, Takeshi Tamura, Hiroyuki Ide, Manabu Hama
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Publication number: 20090149034Abstract: In a semiconductor module, adhesion between an insulating base material and an insulator provided on the insulating base material, for example a sealing resin of the semiconductor element, is to be improved. A plurality of interconnect layers, each including an interlayer dielectric film 405 and a copper interconnect 407, is stacked and a solder resist layer 408 is formed on an uppermost layer. Elements 410a and 410b are formed on a surface of the solder resist layer 408. The elements 410a and 410b are molded in a molding resin 415. The surface of the solder resist layer 408 is modified by plasma processing under a specific condition so that minute projections are formed thereon. Such surface of the solder resist layer 408 is processed such that a value of y/x becomes not less than 0.4, where x represents a detected intensity at a binding energy of 284.5 eV and y represents a detected intensity at a binding energy of 286 eV, by an X-ray photoelectric spectroscopy spectrum.Type: ApplicationFiled: December 15, 2008Publication date: June 11, 2009Applicant: SANYO ELECTRIC CO., LTD.Inventors: Ryosuke USUI, Hideki Mizuhara, Takeshi Nakamura
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Patent number: 7524777Abstract: The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.Type: GrantFiled: December 14, 2006Date of Patent: April 28, 2009Assignee: Texas Instruments IncorporatedInventors: Puneet Kohli, Manoj Mehrotra, Jin Zhao, Sameer Ajmera