Abstract: A semiconductor mask has storage node patterns (101a, 101b, 101c, 101d) defining a first region and a second region. Serifs (10) are provided adjacent comers of the storage node patterns for reducing optical proximity effects. Diffraction bars (202) are positioned between the patterns in the first region. In alternative embodiments of the invention, a diffraction bar (702, 802) is situated adjacent patterns that are variously arranged and configured with respect to the diffraction bar.

Abstract: A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer which does not overlie the alignment mark. The removal exposes a portion of the alignment mark protection layer which does not overlie the alignment mark and the exposed portion of the alignment mark protection layer is then removed. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion thereof using an edge-bead removal tool, thereby allowing for the formation of an alignment mark protection structure without an extra masking step.

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: To compensate for process, activity and environmental variations in a semiconductor device, a back-bias potential tuning circuit is formed on a semiconductor die. The tuning circuit tunes a bias potential applied to the semiconductor die to maintain a predetermined ratio between a transistor on-current and a transistor off-current through at least one channel region. Then, a leakage current is measured for multiple transistors formed in the semiconductor die to determine a representative leakage of the semiconductor die. Tuning characteristics of the back-bias potential tuning circuit are then set to match the representative leakage of the semiconductor die.

Abstract: Semiconductor wafer alignment processes are described. In one embodiment, a first geometric shape is formed over a substrate and has a plurality of sides. A majority of the sides are formed along lines which intersect with another side's line at angles greater than 90.degree.. A second geometric shape is formed over the first geometric shape and is substantially the same as, but different in dimension from the first geometric shape. The position of the shapes is inspected relative to one another to ascertain whether the shapes are misaligned. In another embodiment, an enclosed polygon is formed over the substrate and each of the polygon's sides is joined with another of the polygon's sides to define an angle greater than 90.degree.. A shape is provided elevationally displaced from and received entirely inside the polygon when viewed from over the substrate. The relative positions of the polygon and the elevationally displaced shape are inspected for alignment.

Abstract: A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step difference in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: The present invention provides a bump bonding method that can prevent bumps from being inappropriately shaped.

Abstract: A method of manufacturing a shallow trench isolation alignment mark comprises the steps of first providing a silicon wafer whose surface has an alignment mark formed thereon. Next, a silicon nitride layer is formed over the silicon wafer, and then shallow trenches are formed. At least one of the shallow trenches is positioned at a distance of about 2000 .ANG. to 10000 .ANG. from the edge of the alignment mark. Thereafter, an oxide layer is formed over the silicon nitride layer, and then a chemical-mechanical polishing operation is conducted to remove a portion of the oxide layer and silicon nitride layer above the alignment mark. Altogether, a layer of silicon nitride having a thickness of about 600 .ANG. is removed from the top of the alignment mark. Finally, the silicon nitride layer is also removed. By forming a shallow trench at a distance of between 2000 .ANG. to 10000 .ANG.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) in a selected manner through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth and the particles for a pattern at the selected depth. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: Disclosed is a capacitive structure and method for making the capacitive structure for suppressing inductive noise produced by high performance device power supplies. The capacitive structure includes a trench having a bottom surface and respective walls that are integral with the bottom surface. The trench is defined in a semiconductor substrate and is configured to isolate at least one transistor active area from another transistor active area. The structure further includes an oxide layer that is defined along the bottom surface and the respective walls of the trench, such that a channel is defined within the trench between the oxide layer that is defined along the bottom surface and the respective walls. The structure also includes a conductive polysilicon layer that is defined within the channel and is within the trench. The conductive polysilicon layer defines a conductive electrode that is separated from the semiconductor substrate by a thickness of the oxide layer.

Abstract: A method for wet processing of a semiconductor-containing substrate that reduces contamination in the wet process by removing undesired sources of gas contamination, the method comprising: pumping a processing liquid through a degasifier, exposing the semiconductor wafer, in a vessel, to the degasified processing liquid; and optionally recirculating the processing liquid through the degasifier and back into the vessel.

Abstract: A method is disclosed for fabricating a two- or three-dimensional photonic bandgap structure (also termed a photonic crystal, photonic lattice, or photonic dielectric structure). The method uses microelectronic integrated circuit (IC) processes to fabricate the photonic bandgap structure directly upon a silicon substrate. One or more layers of arrayed elements used to form the structure are deposited and patterned, with chemical-mechanical polishing being used to planarize each layer for uniformity and a precise vertical tolerancing of the layer. The use of chemical-mechanical planarization allows the photonic bandgap structure to be formed over a large area with a layer uniformity of about two-percent. Air-gap photonic bandgap structures can also be formed by removing a spacer material separating the arrayed elements by selective etching. The method is useful for fabricating photonic bandgap structures including Fabry-Perot resonators and optical filters for use at wavelengths in the range of about 0.2-20 .

Abstract: An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Abstract: Apparatus for assembling microstructures onto a substrate through fluid transport. The apparatus includes a vessel that contains the substrate, a fluid, and microstructures. The substrate has at least one recessed region thereon. The microstructures being shaped blocks self-align into the recessed regions located on the substrate such that the microstructure becomes integral with the substrate. The apparatus also includes a pump that circulates the microstructures within the vessel at a rate where at least one of the microstructures is disposed into the recessed region.

Abstract: A process chamber for semiconductor wafers is formed of multiple compartments. A first compartment is provided for supplying an isolated environment for processing the wafers, and a second compartment is provided, in selective communication with the first compartment, to load and unload wafers from the chamber. The wafer handling equipment is located in the second compartment to isolate it from the process environment, and thus form a clean, non-contaminating, environment for the wafer handling equipment. When the chamber must be cleaned, only the first compartment must be cleaned, as no processing occurs in the second chamber. Therefore, the entire first chamber may be removed for cleaning, and replaced with a clean first compartment to decrease chamber turnaround time during chamber cleaning operations.

Abstract: A new method of changing the surface property of a nitride film from hydrophobic to hydrophillic and thereby reducing nitride residue after photolithography is described. A pad oxide layer is provided on the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. Thereafter, the surface of the nitride layer is cleaned wherein the surface is changed from hydrophobic to hydrophillic. The nitride layer is coated with a photoresist film which is developed to leave an opening where the field oxidation region is to be formed. The nitride layer and pad oxide layer are etched away where they are not covered by the photoresist film to expose a portion of the semiconductor substrate. The exposed portion of the semiconductor substrate is oxidized to form a field oxidation region in the fabrication of an integrated circuit.

Abstract: A process for manufacturing microelectronic components that can be fabricated in a facility 1 including integrated circuits on silicon wafers, flat panel displays on glass substrates or any other microelectronic components fabricated in a similar fashion, a process of constructing the facility, and the facility. The fabrication facility 1 relies on a central hub 3 from which processing areas 2 extend out radially like spokes. The processing areas 2 are arranged in a pattern so as to be served by common services which include gases, chemicals, ultra pure water, vapor exhaust, liquid waste, air conditioning, centralized vacuum, centralized clean compressed air, hot water, steam, natural gas, power including emergency, conditioned, and unconditioned power, and process cooling water.

Abstract: Disclosed is a production process and apparatus of high-purity air and various air material gases for semiconductor production factories that, together with enabling the production of high-purity air, also enables the production high-purity nitrogen simultaneous to the production of oxygen-rich air as the finished product. This is accomplished by compressing feed air to a pressure of 3 to 10 kg/cm.sup.2 G, introducing this compressed air into a catalyst tower (8) to convert the carbon monoxide, hydrocarbons and hydrogen contained in the feed air into carbon dioxide and water, and introducing the purified air into an adsorption tower (12a) or (12b) after cooling the heated air following catalytic reaction to remove carbon dioxide, water and other minute amounts of impurities by adsorption. A portion of the resulting purified air is removed as product high-purity air, while the remainder is introduced into a main heat exchanger (18) where it is cooled to substantially the liquefaction temperature.

Abstract: Capacitive coupling between neighboring conductive lines of the semiconductor device is reduced by applying an alternating magnetic field in a direction perpendicular to the plane of the conductive lines.