Abstract: A vacuum/purge operation of a loadlock chamber prevents an eddy phenomenon from occurring in the chamber and thereby prevents wafers from being polluted and damaged by particles in the chamber. A vacuum pump for providing the loadlock chamber with vacuum pressure, and a gas supply for providing the chamber with purge gas are connected to the loadlock chamber by an exhaust line and a gas supply line, respectively. At least one control valve is installed in each of the lines. At the time the state of pressure in the loadlock chamber is to be changed, the loadlock chamber is provided with both the vacuum pressure and the purge gas at rates that are inter-dependent to establish a flow of gases towards and into the exhaust line. Then, the supplying of one of the vacuum pressure and the purge gas is gradually reduced and cut off.

Abstract: The invention allows a cluster tool to change from a first recipe to a second recipe, while preserving periodicity and ensuring that there are no delays at critical points. This procedure is referred to as recipe cascading. Cascading involves emptying a first lot of wafers off a cluster tool and populating the cluster tool with another lot of wafers, serially and simultaneously. The procedure is performed with no delays incurred at critical process steps; and with no additional robots and process modules other than those called for by the recipe and throughput requirements of the entering and the exiting lots. The entering lot may also have different recipes and throughput requirements from the exiting lot. A program residing on a computer determines a schedule for the cluster tool which enables recipe cascading. The program may use a genetic algorithm to determine the schedule, or any other optimization technique.

Abstract: A system and method of for determining multiple uniformity metrics of a semiconductor wafer manufacturing process includes collecting a quantity across each one of a group of semiconductor wafers. The collected quantity data is scaled and a principal component analysis (PCA) is performed on the collected, scaled quantity data to produce a first set of metrics for the first group of semiconductor wafers. The first set of metrics including a first loads matrix and a first scores matrix.

Abstract: A semiconductor device fabricating method includes the steps of loading one or more substrates into a boat disposed in a waiting room positioned next to a reaction furnace; vacuum-evacuating the waiting room to a vacuum state at a base pressure; loading the boat into the reaction furnace at a first ambient pressure; and recovering a temperature of the reaction furnace at a second ambient pressure. The first or the second ambient pressure is greater than the vacuum state but less than the atmospheric pressure. Further, the method includes the step of increasing the temperature of the one or more substrates at a third ambient pressure, and also the third ambient pressure is greater than the base pressure but less than the atmospheric pressure.

Abstract: In a plasma deposition system for depositing a film of sputtered target material on a substrate, the output of an RF generator coupled to a coil for generating a plasma can be varied during the deposition process so that heating and sputtering of the RF coil can be more uniform by “time-averaging” RF voltage distributions along the RF coil.

Abstract: The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. The problem of interconnection congestion is overcome by routing the interconnections through the substrate. The through interconnections are made by etching vias through the substrate by RIE, oxidizing the via sidewalls, and filling the vias with polysilicon.

Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.

Abstract: A pellicle formed by bonding a pellicle membrane composed of synthesized glass on a pellicle frame by an adhesive wherein a light shielding member for shielding ultra-violet rays irradiated to the adhesive is provided at a portion where the pellicle membrane is bonded to the pellicle frame, whereby the adhesive for bonding the pellicle membrane to the pellicle frame is prevented from being deteriorated due to the irradiation of ultra-violet rays for cleaning.

Abstract: A method is provided for forming a device. The method provides a substrate, and provides a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.

Abstract: A memory structure that includes a control element electrode, a heater electrode, a memory element electrode, a chalcogenide based memory element disposed between the memory element electrode and the heater electrode, and a control element disposed between the heater electrode and the control element electrode.

Abstract: This invention relates to the field of nanotechnology. Specifically the invention describes a method for cutting a multiplicity of nano-structures to uniform dimensions of length, length and width, or area, or to a specific distribution of lengths or area using various cutting techniques.

Abstract: A substrate fabrication system is provided which includes a buffer station located inline between a front docking port and a loadlock chamber, the buffer station being operatively joined with a front handling chamber. Preferred embodiments employ a buffer station having a rack with reduced pitch, or relative spacing between shelves. Additional embodiments provide variable pitch end effectors as part of the disclosed fabrication system. Methods of fabricating wafers by quickly transferring them to purgeable buffer stations upon wafers arriving at a docking port are also provided.

Abstract: The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: Disclosed is a method of manufacturing a photomask, comprising calculating a pattern area ratio, which is a ratio of the light transmitting pattern portion or the light shielding pattern portion to an area of the photomask from the design data of a given layout pattern of the photomask, and a pattern density, which is a ratio of the light transmitting pattern portion or light shielding pattern portion within the region to the area of the region extracted from the given layout pattern, estimating from the calculated pattern area ratio and the pattern density the size of a pattern formed in the case where the pattern is formed on the photomask by using the design data of the given layout pattern, and imparting the amount of correction to the design data of the given layout pattern based on the estimated pattern size.

Abstract: The present invention provides a matrix comprising an array of nanostructures that exhibit a variation (gradient) in physical properties (such as size or pitch) in at least one direction of the plane containing said array. A method for forming an array having a gradient property is also provided. In addition, a separation method is provided comprising the steps of: providing a matrix comprising an array of nanostructures arranged so that the array has the property of a gradient; and conducting at least one biomolecule separation process to separate biomolecules in a composition containing a plurality of biomolecules using the matrix.

Abstract: A nanosyringe is constructed using micro fabrication and nano fabrication techniques on a silicon substrate. The nanosyringe includes a membrane of silicon carbide. The position and operation of individual nanosyringes, arranged in an array of nanosyringes, can be independently controlled. A nanosyringe array can inject or extract a fluid from one or more cells or other structures. Microfluidic structures coupled to the nanosyringe allow external pumping or extraction. A cell matrix or organelles of individual cells can be non-destructively sampled in real time.

Abstract: A factory interface for a multiple chamber semiconductor wafer processing cluster tool having a K-wafer load-lock (KWLL). The KWLL comprises a variable number of K+1 wafer slots assigned as inbound and outbound slots. Inbound slots are used to send up to K+1 wafers into the cluster tool and the same slots, denoted as outbound slots, are used for receiving up to K+1 wafers from the cluster tool. The K+1 slots are in the same volume that has to be pumped for wafers to enter the tool and vented for wafers that to leave the tool. These K+1 slots accommodate up to K wafers when accessed by a single blade robots from the tool or the factory interface, and up to K+1 wafers when the tool and factory interface are equipped with dual blade robots. Various KWLL loading methods can be selected to optimize the throughput of a wafer processing system using the KWLL. Such methods include wafer packing, reactive and gamma tolerant methods.

Abstract: A method for producing semiconductor or metal particles comprises the steps of: storing a semiconductor or metal melt in a crucible having a nozzle; supplying a gas comprising at least one selected from the group consisting of He, Ne, Ar, Kr and Xe into the crucible such that the pressure of the supplied gas in a space over the melt in the crucible is higher than the pressure of a gaseous phase into which the melt is dropped; dropping the melt from the nozzle into the gaseous phase by the pressure of the gas to form liquid particles; and solidifying the liquid particles in the gaseous phase to obtain semiconductor or metal particles. The crucible comprises at least one selected from the group consisting of hexagonal BN, cubic BN, Si3N4, TiB2, ZrB2, zirconia and stabilized zirconia at least near the nozzle.

Abstract: A laser system includes a laser diode with a low dimensional nanostructure, such as quantum dots or quantum wires, for emitting light over a wide range of wavelengths. An external cavity is used to generate laser light at a wavelength selected by a wavelength-selective element. The system provides a compact and efficient laser tunable over a wide range of wavelengths.

Abstract: The present invention provides electrical devices having controlled electrical properties and being formed from nanotube components, together with a method of constructing the devices. In one example, the electrical device is formed from the central nanotube of a zigzag type interconnected between two nanotubes of an armchair type. The method of forming the nanotube structure includes connecting a first end of a zig-zag type nanotube to an end of an armchair type nanotube, and connecting a second end of the zig-zag type nanotube to an end of a second armchair type nanotube.

Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.

Abstract: A silicon condenser microphone is described. The silicon condenser microphone of the present invention comprises a perforated backplate comprising a portion of a single crystal silicon substrate, a support structure formed on the single crystal silicon substrate, and a floating silicon diaphragm supported at its edge by the support structure and lying parallel to the perforated backplate and separated from the perforated backplate by an air gap.

Abstract: To provide a film substrate treatment apparatus that appropriately mounts film substrates on an electrostatic adsorption stage. In the film substrate treatment apparatus, adsorption pads are disposed on the first adsorption units that mount film substrates on an electrostatic stage, and a pressing member that presses the edge portion areas of the film substrates against the stage is provided. The film substrates can thereby be reliably attached to the stage, and the film substrates can be appropriately treated in a decompressed atmosphere.

Abstract: An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The electronic devices can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The construction of molecular electronic devices is achieved on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The molecular switchable devices in the cross-bar geometry are configurable while the conformational change is controlled by intramolecular forces that are stronger than hydrogen bonding.

Abstract: A platen for electrostatic wafer clamping apparatus comprising a platen body of dielectric material and grains of electrically conductive material diffused in the dielectric material so that the platen has a relatively large electrostatic capacitance due to the diffusion of the conductive grains with the result that the platen provides an increased clamping force regardless of humidity. In accordance with another aspect of the invention, the thickness of the platen body can be decreased by an amount sufficient to maintain a constant clamping force with reduced applied voltage, to eliminate any residual voltage on the platen and to increase the speed of wafer release. The grains of electrically conductive material are present in an amount of from about 2.5 percent to about 15.0 percent of the volume of the platen body, and the grains of electrically conductive material are selected from the group consisting of carbonated transition metals, nitrified transition metals and carbonated grains.

Abstract: A system (10) is formed to include a semiconductor device (11) that typically is formed to function as a voltage regulator. The semiconductor device (11) is formed to have a control loop that includes an amplifier (30) and a feedback transistor (19) that provide a small signal AC gain that varies inversely to a load current of an output transistor (12) in order compensate for the manner in which the output transistor (12) transconductance depends on the load current flowing through the output transistor (12).

Abstract: In a substrate processing apparatus that supports substrates W by a plurality of holding members of a rotor to process the substrates W rotated by the rotor, any one of the holding members is provided with press devices 130 to apply pressures on the peripheries of the substrates W. Each press device 130 has an abutting part 160 for contact with the periphery of the substrate W, a cylinder mechanism 161 for moving the abutting part 160 between a position in contact with the periphery of the substrate W and another position apart from the periphery of the substrate W and a deformable part 162 elastically deformed by the movement of the abutting part 160 to isolate the cylinder mechanism 161 from an atmosphere around the substrates W. Consequently, it is possible to provide the substrate processing apparatus and method that do not cause a diaphragm to be deformed excessively.

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.

Abstract: An integrated circuit and method of manufacturing therefor. In one embodiment, the integrated circuit includes a substrate with an insulator and a capacitor formed over the substrate. The integrated circuit further includes an adhesive formed over the insulator. The integrated circuit still further includes a micromagnetic device. The micromagnetic device includes a ferromagnetic core formed over the adhesive. The adhesive forms a bond between the insulator and the ferromagnetic core to secure the ferromagnetic core to the substrate. The micromagnetic device also includes at least one winding, located proximate the ferromagnetic core, to impart a desired magnetic property to the ferromagnetic core. The micromagnetic device is electrically coupled to the capacitor.

Abstract: An alignment mark shielding ring for use in a physical vapor deposition chamber and a method for using the ring to avoid arcing problems on the wafer. The alignment mark shielding ring can be constructed of a ring that has a generally L-shaped cross-section, at least one hood portion to function as the shield for the alignment mark, at least one alignment pin for engaging at least one alignment sleeve mounted in a lower chamber shield for holding the alignment mark shielding ring in place. The alignment sleeve is constructed in two halves, each having an aperture therethrough. The aperture in the top half is larger than the aperture in the bottom half such that even when the apertures are coated with a metal layer deposited in the PVD process, the alignment pin does not electrically short to the lower chamber shield and thus, any possibility of arcing is avoided.

Abstract: A semiconductor manufacturing method employing optical lithography, using a reticle for lithographic alignment. The reticle includes a first area having a desired circuit pattern, and a second area including alignment marks arranged at specific positions, each area being located in an exposure range of an optical exposure apparatus. Each of the alignment marks includes mark elements arranged to form a first geometric shape. Each of the mark elements has main sub-elements arranged in a specific direction at first pitches to form a second geometric shape, and auxiliary sub-elements located at each end of the second geometric shape. Each auxiliary sub-element is apart from one of the main sub-elements at a second pitch. Each main sub-element is optically resolvable, while each auxiliary sub-element is optically irresolvable. Each of the main and auxiliary sub-elements preferably has a linear shape.

Abstract: A method for operating a multi-station processing chamber is described. A wafer is loaded onto the first station then indexed to the second station prior to processing. The indexing causes the wafer to be well-seated on it spindle before being processed. This prevents an improperly seated wafer from being processed at the first station.

Abstract: A platen for electrostatic wafer clamping apparatus comprising a platen body of dielectric material and grains of electrically conductive material diffused in the dielectric material so that the platen has a relatively large electrostatic capacitance due to the diffusion of the conductive grains with the result that the platen provides an increased clamping force regardless of humidity. In accordance with another aspect of the invention, the thickness of the platen body can be decreased by an amount sufficient to maintain a constant clamping force with reduced applied voltage, to eliminate any residual voltage on the platen and to increase the speed of wafer release. The grains of electrically conductive material are present in an amount of from about 2.5 percent to about 15.0 percent of the volume of the platen body, and the grains of electrically conductive material are selected from the group consisting of carbonated transition metals, nitrified transition metals and carbonated grains.

Abstract: A method of standardizing a fabrication process for an integrated circuit. The fabrication process includes a preceding thermal energy sensitive process and at least one set of selectable succeeding thermal energy delivery processes. An integrated circuit structure is formed using the preceding thermal energy sensitive process. The preceding thermal energy sensitive process is characterized based at least in part upon the greatest amount of thermal energy delivered to the integrated circuit by one of the set of selectable succeeding thermal energy delivery processes. Then as subsequent processes are selected and accomplished, if they do not deliver the greatest amount of thermal energy as anticipated by the preceding thermal energy sensitive process, an additional amount of thermal energy is added, so as to preferably equal the anticipated greatest amount of thermal energy. In this manner, the characterization of the preceding thermal energy sensitive process attains its desired parameters.

Abstract: A load port includes an adapter-detecting sensor arranged at an upper portion of an opener. When the opener opens a lid of a FOUP, the adapter-detecting sensor detects whether a wafer adapter is mounted in the FOUP, and notifies a control unit of a semiconductor manufacturing apparatus of the result of the detection. The control unit determines the size of semiconductor wafers based on the result of the detection and carries out processing operation dependent on the size of the wafers in a processing chamber.

Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.

Abstract: The present invention is related to a method and apparatus for liquid treating and drying a substrate, such as a semiconductor wafer, the method comprising the step of immersing a substrate or a batch of substrates in a tank filled with a liquid, and removing the substrate(s) through an opening so that a flow of the liquid takes place through the opening during removal of the substrate. Simultaneously with the removal, a reduction of the surface tension of the liquid is caused to take place near the intersection line between the liquid and the substrate. For acquiring such a tensio-active effect, a uniform flow of a gas or vapor is used, or/and a local application of heat. The invention is equally related to an apparatus for performing the method of the invention.

Abstract: One embodiment of the invention provides a method that facilitates selectively varying how much of a layout of an integrated circuit is defined by phase shifters during an optical lithography process used in manufacturing the integrated circuit. During operation, the method receives a specification of the layout of the integrated circuit. The method then assigns features within the layout to zones associated with different phase shifting priorities. Next, the method generates a phase shifter placement by placing phase shifters comprised of phase shifting geometries onto a phase shifting mask to define the features within the layout, wherein the phase shifter placement is subject to coloring constraints. Note that in general there is no restriction on the order of zone placement. During this placement process, if coloring constraints cannot be satisfied, the method resolves conflicts and/or removes features from being phase-shifted based upon phase shifting priorities of the zones.

Abstract: A shield for protecting silicon wafers. The shield includes a plurality of single crystal shielding members having a lattice unit cell repeated substantially throughout. The unit cell has a periodic arrangement of atoms defining a set of lattice planes. The shielding members each include a pair of first interface surfaces having an orientation substantially aligned along one of the set of lattice planes. The shield also includes a plurality of single crystal structural members each having substantially the same lattice unit cell as that of the shielding members repeated substantially throughout. The structural members each include a pair of second interface surfaces having an orientation substantially aligned along the same one of the set of lattice planes. The plurality of shielding members and structural members are alternately bonded together at their respective first and second interface surfaces to define an enclosed area sized to receive the silicon wafers therein.

Abstract: In a hot plate for performing heat processing while an inert gas is supplied, a mounting table is provided with a groove and a lower end portion of a lid body can be inserted into the groove. The lid body is lowered in two steps by a lid body drive apparatus. The lid body forms a processing chamber between the lid body and the mounting table by the lowering of the first step, and the lower end portion of the lid body is inserted into the groove by the lowering of the second step, thereby reducing the processing chamber in capacity. Consequently, in a substrate processing apparatus which requires a supply of gas, it becomes possible to reduce the capacity of the processing chamber and to reduce the required amount of gas.

Abstract: There is provided a storage water of a silicon wafer wherein a liquid temperature of the storage water is 0 to 18° C. And there is provided a shower water of a silicon wafer wherein a liquid temperature of the shower water is 0 to 18° C. The wafer is stored in the storage water, and showered using the shower water. The present invention also relates to a method for storing silicon wafer wherein the silicon wafer is showered using a shower water of which liquid temperature is 0 to 18° C., and is then stored in liquid using a storage water of which liquid temperature is 0 to 18° C. Thereby, there can be provided a water for storing a silicon wafer, a method for storing it, a water for showering it and a method for showering it wherein degradation of the wafer quality can be prevented.

Abstract: A method for drying a semiconductor substrate includes the steps of clearing the substrate by supplying a liquid into a processing bath of a chamber, injecting first dry gases onto a surface of the supplied liquid, draining the liquid from the processing bath so that the substrate is slowly exposed to the surface of the liquid, and injecting a second dry gas into the chamber and forcibly exhausting gas in the chamber.

Abstract: Disclosed is a method for producing semiconductor fine particles comprising a step of preparing two or more solutions each containing at least one element selected from Group II to Group VI and feeding the solutions to an addition tank with mixing the two or more solutions fed to the addition tank by stirring to produce fine particles. In this production method, (1) flows of different rotational directions are formed by stirring the two or more solutions fed to the addition tank, and/or (2) a solvent is introduced into the addition tank beforehand, a mixing chamber having an opening is disposed below liquid surface of the solvent in the addition tank, and the two or more solutions are fed to the mixing chamber with controlling flow rates of the solutions. According to this production method, semiconductor fine particles having uniform grain sizes can be produced in a simple and convenient manner.

Abstract: A backside cannelure of an electrode to provide for detecting semiconductor wafer shift after the wafer has been positioned over the cannelure of the electrode is disclosed. The wafer has a backside and a proper position over the cannelure. The cannelure exposes the backside of the wafer to a gas piped in through one or more holes of the electrode. The cannelure has a size such that deviation of the wafer from its proper position by more than a threshold partially exposes the cannelure, such that the gas leaks from the cannelure as now partially exposed. A gas flow detector may detect the gas leaking from the cannelure, and provide corresponding detection of the wafer deviating from its proper position.

Abstract: A novel system is provided for automatically generating caution labels for moisture-sensitive semiconductor devices packed in drypack bags. The system has a scanner that scans a lot number or an ID mark representing ID information of a moisture-sensitive device sealed in a drypack bag, and a computing device with a look-up table containing moisture-sensitivity levels assigned to the moisture-sensitive devices. In response to an ID signal produced by the scanner, the computing device searches the look-up table for a moisture-sensitivity level assigned to the packed moisture-sensitive device. The determined moisture-sensitivity level is supplied by the computing device to a label-formatting device for generating a caution label indicating the moisture-sensitivity level. The label-formatting device controls a printer for printing the generated caution label.

Abstract: A heat exchange section (72) is provided in the middle of a circulation water path (58, 59) connecting between a temperature-controlled water tank (71) and a semiconductor manufacturing apparatus body (4) so as to perform a heat exchange with air of a clean room (3). The heat exchange section (72) is installed near an exit of an air circulation path (32) above a fan-filter unit (34) of the clean room as a temperature stabilized area off an atmosphere of the clean room (3). Additionally, as another method, a temperature of a chemical fluid from a chemical fluid tank (6) is controlled to be a temperature of the air in the clean room by a heat exchange section (61) provided in a location the same as above without using the temperature-controlled water so as to supply the chemical fluid to the semiconductor manufacturing apparatus body (4).

Abstract: An apparatus for removing an unwanted substance from a semiconductor wafer, according to this invention, applies a peeling tape T to a protective tape P on the surface of the semiconductor wafer W. An edge member 28 is placed in contact with the surface of the peeling tape T and run along the protective tape P. The peeling tape T is peeled as being folded back by a large angle of 90 degrees or more at the tip of edge member 28. The protective tape P is peeled and removed along with the peeling tape T from the surface of the wafer. As a result, the unwanted substance is removed with high precision without breaking the wafer W.

Abstract: A cluster tool includes a block which is formed with an inner high vacuum chamber, at least two loadlock chambers that are in fluid communication with the high vacuum chamber, and at least two slot valves for selectively isolating each loadlock chamber from the high vacuum chamber. The cluster tool also includes a high vacuum pump that is connected to the high vacuum chamber and a water pump comprising a refrigeration unit and a cryoplate. The cryoplate is cooled by the refrigeration unit and projects into the high vacuum chamber between the loadlock chambers. Selective operation of the slot valves allows a single water pump to serve a plurality of loadlock chambers. Each loadlock chamber includes a refrigerated platen that projects into the loadlock chamber, a heat lamp assembly that radiates into the loadlock chamber, and a tray for holding the wafer therein. The platen has a cooling system for selectively cooling the wafer, and selective radiation of the heat lamp assembly degasses the wafer.