Abstract: A nanowire, nanosphere, metallized nanosphere, and methods for their fabrication are outlined. The method of fabricating nanowires includes fabricating the nanowire under thermal and non-catalytic conditions. The nanowires can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the method of fabricating nanospheres includes fabricating nanospheres that are substantially monodisperse. Further, the nanospheres are fabricated under thermal and non-catalytic conditions. Like the nanowires, the nanospheres can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the nanospheres can be metallized to form metallized nanospheres that are capable as acting as a catalyst.

Abstract: A process of supplying moisture at low flow rates which permits high precision control of the flow of moisture to a semiconductor manufacturing line from an apparatus for the generation of moisture, characterized in that the flow of hydrogen to a moisture-generating reactor is controlled by means of a flow controller in such a way that an amount of hydrogen as fed is gradually increased from the start and reaches a specific set level such that when a specific time has passed, a predetermined rate of moisture begins to be produced and supplied to the semiconductor manufacturing line. The moisture is generated in the apparatus for generation of moisture in which hydrogen and oxygen are (a) fed into a reactor provided with a coat of platinum on the wall in the interior space, (b) enhanced in reactivity by the platinum catalytic action, and (c) caused to instantaneously react with each other at a temperature lower than the ignition point to produce moisture without undergoing combustion at a high temperature.

Abstract: A method for preparing a wafer having a smooth surface is disclosed. The present invention includes the step of preparing a wafer base and a first material on the wafer base. The wafer base and first material have a surface and a plurality of holes. The present invention includes the step of depositing a second material at an angle on the first material such that the second material is substantially on the surface. The present invention includes the step of exposing the first material and the second material to an oxidizing agent. The present includes the step of reacting a third material on the second surface to close the holes.

Abstract: The present invention provides a method for producing a silicon wafer characterized in that at least one surface of the wafer is subjected to a multi-step polishing process, in which a heat treatment in a mixed gas atmosphere of hydrogen and argon through use of a rapid heating/rapid cooling apparatus is substituted for a final polishing in the multi-step polishing process, and a silicon wafer produced by the method. Thereby, there can be provided a silicon wafer in high productivity wherein there is neither mechanical damages nor scratches on the surface of the wafer, surface roughness is significantly improved, and there is no slip dislocation.

Abstract: A microelectronic substrate and method for manufacture. In one embodiment, the microelectronic substrate includes a body having a first surface, a second surface facing a direction opposite from the first surface, and a plurality of voids in the body between the first and second surfaces. The voids can extend from the first surface to a separation region beneath the first surface. At least one operable microelectronic device is formed at and/or proximate to the first surface of the substrate material, and then a first stratum of the microelectronic substrate above the separation region is separated from a second stratum of the microelectronic substrate below the separation region. The first stratum of the microelectronic substrate can be further separated into discrete microelectronic dies before the first stratum is separated from the second stratum. In one aspect of this embodiment, the substrate can support a film and microelectronic devices can be formed in the film and/or in the substrate.

Abstract: A method for achieving improved piezoelectric films for use in a resonator device is disclosed. The method is based on applicant's recognition that the texture of a piezoelectric film (e.g., as used in a piezoelectric resonator) is directly affected by the surface morphology of the underlying electrode, and additionally, the surface morphology of the electrode is affected by the surface morphology of the underlying oxide layer or Bragg stack. Accordingly, the invention comprises a method of making a device having a piezoelectric film and electrode comprising controlling the deposition and surface roughness of the electrode and optionally, the Bragg stack.

Abstract: A copper layer is formed in wiring grooves formed in a semiconductor substrate and also on the semiconductor substrate. The semiconductor substrate is brought into contact with a culture solution containing bacteria whose size is larger than the width of the wiring grooves. The copper layer on the semiconductor substrate is removed by the bacteria comprising autotroph, but the copper layer in the wiring grooves is not removed because the bacteria cannot enter the wiring grooves.

Abstract: The invention encompasses methods of forming capacitors, methods of forming silicon nitride layers on silicon-comprising substrates, methods for densifying silicon nitride layers, methods for forming capacitors, and capacitors. In one aspect, the invention includes a method of densifying a silicon nitride layer comprising subjecting a silicon nitride layer to a nitrogen-comprising ambient atmosphere having at least about two atmospheres of pressure. In another aspect, the invention includes a method of forming a capacitor comprising: a) forming a first capacitor plate, the first capacitor plate comprising silicon and having a surface; b) forming a dielectric layer proximate the first capacitor plate, the dielectric layer comprising a silicon nitride layer and being formed by exposing the first capacitor plate surface to a nitrogen-comprising ambient atmosphere having at least about two atmospheres of pressure; and c) forming a second capacitor plate proximate the dielectric layer.

Abstract: A process for forming a uniform nanoporous dielectric film on a substrate. The process includes horizontally positioning a flat substrate within a cup; depositing a liquid alkoxysilane composition onto the substrate surface; covering the cup such that the substrate is enclosed therein; spinning the covered cup and spreading the alkoxysilane composition evenly on the substrate surface; exposing the alkoxysilane composition to water vapor and base vapor to thereby form a gel; and then curing the gel. The invention also provides an apparatus for spin depositing a liquid coating onto a substrate. The apparatus has a cylindrical cup with an open top section and removable cover which closes the top. A vapor injection port extends through the center of the cover. Suitable means hold a substrate centered within the cup and spin the cup.

Abstract: Composite media having simultaneous negative effective permittivity and permeability over a common band of frequencies. A composite media of the invention combines media, which are either themselves separately composite or continuous media, having a negative permittivity and a negative permeability over a common frequency band. Various forms of separate composite and continuous media may be relied upon in the invention. A preferred composite media includes a periodic array of conducting elements that can behave as an effective medium for electromagnetic scattering when the wavelength is much longer than both the element dimension and lattice spacing The composite media has an effective permittivity &egr;eff(&ohgr;) and permeability &mgr;eff(&ohgr;) which are simultaneously negative over a common set of frequencies. Either one or both of the negative permeability and negative permittivity media used in the invention may be modulable via external or internal stimulus.

Abstract: There are a device and method for protecting semiconductor material, wherein semiconductor material is processed on a surface of stabilized ice made from ultrapure water and particles of semiconductor material.

Abstract: A TMR element includes: a free layer formed on a lower gap layer; a tunnel barrier layer formed on the free layer; and a pinned layer formed on the tunnel barrier layer. In the step of forming the tunnel barrier layer on the free layer, an Al layer used for making the tunnel barrier layer is formed through sputtering, for example, on the free layer while the substrate is cooled. The Al layer is oxidized to form the tunnel barrier layer.

Abstract: Methods are disclosed for performing reticle-substrate alignments in the context of charged-particle-beam (CPB) microlithography. More specifically, the subject methods pertain to detecting an amount of relative rotation between the “transfer-receiving” (e.g., substrate) side and the “transfer-originating” (e.g., reticle) side in one operation simply by detecting marks that are disposed near an axis of the CPB-optical system. A charged particle beam is passed through an alignment mark(s) situated relative to an alignment axis of the reticle and thus indicates reticle orientation. One or more respective index marks are defined on the substrate relative to an alignment axis of the substrate, thereby indicating substrate orientation. E.g., two index marks can be provided on the substrate, one convex and the other concave, but otherwise similarly shaped. The index marks can be situated linearly aligned with each other or at an angle to each other.

Abstract: In the fabrication of capacitors, a TiO2 film is formed from a TiN film by means of heat-treatment within an atmosphere which does not contain oxygen. This serves to prevent the polysilicon which forms the bottom electrode from being oxidized during heat-treatment. Thus, once the bottom electrode has been formed on the silicon wafer, a TiN film and RuO2 film are formed, and the silicon wafer is heat-treated in an atmosphere which does not contain oxygen. In this manner, a dielectric film that is a TiO2 film and a top electrode that is a ruthenium film are obtained.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of forming a stressed region in a selected manner at a selected depth (20) underneath the surface. An energy source such as pressurized fluid is directed to a selected region of the donor substrate to initiate controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: To provide a lamp annealing apparatus, which prevents cloud of a reflector, achieves stability of temperature for heat-treatment and prevents oxidization of a front surface of a semiconductor wafer. The lamp annealing apparatus includes a lamp unit 1 for heating at an upper portion of a chamber 10 and a reflector 7a for stabilizing temperature at a lower portion of the chamber 10. Process gas is supplied to a side of a front surface 21 of a semiconductor wafer 2 located and rotated on a rotating cylinder 4 in the chamber 10, and rear face gas for preventing cloud of the reflector 7a is supplied to a side of a rear surface 22 of the semiconductor wafer 2. There are further included mass flow controllers 15a to 15d for mixing gases to obtain a desire rear face gas. The rear face gas is turned around the periphery of the reflector 7a to be exhausted.

Abstract: The present invention provides a method for producing a group III nitride compound semiconductor substrate including: (a) forming a first semiconductor film over a substrate, the first semiconductor film made of a first group III nitride compound semiconductor and provided with a step; (b) forming a second semiconductor film made of a second group III nitride compound semiconductor having a different thermal expansion coefficient from that of the first group III nitride compound semiconductor on the first semiconductor film; and (c) cooling the substrate and separating the second semiconductor film from the first semiconductor film. Thus, a large-area group III nitride compound semiconductor substrate can be produced in high yields and with high reproducibility.

Abstract: A mass flow controller controls the delivery of a precursor to a mist generator. The precursor is misted utilizing a venturi in which a combination of oxygen and nitrogen gas is charged by a corona wire and passes over a precursor-filled throat. The mist is refined using a particle inertial separator, electrically filtered so that it comprises predominantly negative ions, passes into a velocity reduction chamber, and then flows into a deposition chamber through inlet ports in an inlet plate that is both a partition between the chambers and a grounded electrode. The inlet plate is located above and substantially parallel to the plane of the substrate on which the mist is to be deposited. The substrate is positively charged to a voltage of about 5000 volts. There are 440 inlet ports per square inch in an 39 square inch inlet port area of the inlet plate directly above the substrate. The inlet port area is approximately equal to the substrate area.

Abstract: Variable reactances in an impedance-matching box for an RF coil, in a plasma deposition system for depositing a film of sputtered target material on a substrate, can be varied by rotating inductor cores during the deposition process so that the RF coil and substrate heating, and the film deposition, are more uniform due to “time-averaging” of the RF voltage distributions along the RF coil.

Abstract: Method and apparatus for suction-holding a semiconductor pellet on a positioning stage of a bonding apparatus without causing the pellet to be misaligned after positioning thereof including a suction force control device. The suction force control device comprises a suction-switching electromagnetic valve, a suction force-adjusting electromagnetic valve, a vacuum source, a compressed air source and a throttle valve so that a semiconductor pellet is held on a positioning stage by a suction force that is weak enough that a positioning claw can move the semiconductor pellet for positioning; and upon completion of the positioning, the semiconductor pellet is held to the positioning stage by a suction force that is stronger than the weak suction force used for positioning.

Abstract: A novel method and apparatus for indicating a degree of manufacture of an insert molded component useable in an end use assembly by forming a removable appendage protruding from the insert molded component, or article, manufactured to an intermediate degree, the insert molded component having a lead frame at least partially embedded in a molded housing member, and the removable appendage coupled to at least one or both of the lead frame and the molded housing member, the lead frame having at least two electrical conductors coupled separably by a tie member, the removable appendage removable upon or after electrical isolation of the electrical conductors in a subsequent processing step, whereby the presence of the removable appendage is indicative that the electrical conductors are not electrically isolated, or that the insert molded component has not been tested or inspected subsequent to electrical isolation of the electrical conductors, and whereby the removable appendage is configured to prevent use of the

Abstract: This invention discloses a method for designing and manufacturing semiconductors including the steps of: (i) producing a fab-ready design for a semiconductor device by importing into the design at least one core from a remote source, the core bearing an identification indicium, (ii) utilizing the fabready design to fabricate the semiconductor device, and (iii) reading the identification indicium from the semiconductor device to indicate incorporation of the at least one core therein.

Abstract: A cluster tool includes a block which is formed with an inner high vacuum chamber, at least two loadlock chambers that are in fluid communication with the high vacuum chamber, and at least two slot valves for selectively isolating each loadlock chamber from the high vacuum chamber. The cluster tool also includes a high vacuum pump that is connected to the high vacuum chamber and a water pump comprising a refrigeration unit and a cryoplate. The cryoplate is cooled by the refrigeration unit and projects into the high vacuum chamber between the loadlock chambers. Selective operation of the slot valves allows a single water pump to serve a plurality of loadlock chambers. Each loadlock chamber includes a refrigerated platen that projects into the loadlock chamber, a heat lamp assembly that radiates into the loadlock chamber, and a tray for holding the wafer therein. The platen has a cooling system for selectively cooling the wafer, and selective radiation of the heat lamp assembly degasses the wafer.

Abstract: A method of producing a contact structure for achieving an electrical connection with a contact target. The contact structure includes a contactor formed on a planar surface of a substrate by a microfabrication technology. In one aspect, the production method involves a plastic molding technology. In another aspect, the production method involves a photolithography technology using a gray-tone photomask. The contactor has at least a horizontal portion formed on the substrate and a contact portion formed on one end of the horizontal portion. A spring force of the horizontal portion of the contactor provides a contact force when the contactor is pressed against the contact target. In a further aspect, the contact structure includes a recess for providing a free space for the contactor when the contactor is pressed against the contact target.

Abstract: A method of forming a thin film on a plurality of wafers stored in a wafer cassette does not require cleaning the reaction chamber(s) after each thin film formation step. The reaction chamber cleaning is performed after the thin film formation process is performed consecutively at least two times.

Abstract: A plasma-enhanced chemical vapor deposition system includes a number of process gas injection tubes and at least one dedicated clean gas injection tube. A plasma is used to periodically clean the interior surfaces of the deposition chamber. The cleaning is made more rapid and effective by introducing the clean gas through the dedicated clean gas injection tube. In this manner the clean gas can be introduced at a relatively high flow rate without detracting from the cleaning of the interior surfaces of the process gas injection tubes. As a separate aspect of this invention, a high-frequency signal is applied to both terminals of the coil during the cleaning process. This produces a plasma, mainly by capacitive coupling, which has a shape and uniformity that are well-suited to cleaning the surfaces of the deposition chamber.

Abstract: In a semiconductor manufacturing apparatus, a semiconductor substrate ion-implanted with an ion species is heated and thereby raised in temperature under vacuum. At this time, a partial pressure of a gas released from the semiconductor substrate is measured by a quadrupole mass spectrometer. Further, a change in partial pressure with time is observed and compared with a pre-measured release characteristic, whereby the temperature of the semiconductor substrate is corrected.

Abstract: To avoid damage to carrier substrates in a device for mechanically aligning carrier substrates for electronic circuits, the carrier substrates having two main surfaces and a peripheral surface and being supplied to a horizontal fixture of the device, centering elements being forced to engage on the peripheral surface of the carrier substrates to align the carrier substrates in the horizontal fixture, it is proposed that at least two centering elements be mounted rotationally and displaceably in the axial direction on at least two first shafts that are oriented in parallel with one another and in parallel with the horizontal fixture. The centering elements engage on sections of the peripheral surface of the carrier substrate disposed opposite one another in a first direction, and at least two further centering elements engage with stop faces at sections of the peripheral surface of the carrier substrate disposed opposite one another in a second direction running perpendicularly to the first direction.

Abstract: An implantable medical device such as a defibrillator is described. The device includes an hermetically sealed housing containing a flat electrolytic capacitor and an energy source such as a battery. The battery is connected to the capacitor and provides charge thereto. The capacitor stores the charge at a relatively high voltage. The charge stored in the capacitor is discharged through a defibrillation lead to a site on or in the heart when fibrillation of the heart is detected by the implantable medical device. Methods of making and using the implantable medical device, the capacitor, and their various components are disclosed.

Abstract: There is disclosed a method of manufacturing a ferroelectric memory device capable of improving the problems in a conventional plugging or strapping method, which are used in connecting a ferroelectric capacitor and a transistor. The present invention forms a contact leading pad at the drain junction of the transistor in the process of forming bit lines, and then forms and connects a ferroelectric capacitor and a local interconnection line connects. In this manner, the present invention connects the ferroelectric capacitor and the transistor through an additional contact leading using a local interconnection method without directly connecting them. Thus, the method according to the present invention can reduce the cell area per unit since the capacitor can be positioned at the same position to the transistor. Also, it can improve the characteristic of a device, since it can use metals suitable for interconnection materials but not used due to low step coverage.

Abstract: A wafer carrier adapter for use with a 200 millimeter wafer carrier and a pod door opener to a front end of a semiconductor processing environment. The 200 millimeter wafer carrier has a bottom surface and is provided with a plurality of recesses extending through the bottom surface in a predetermined configuration and a front opening for accessing silicon wafers in the wafer carrier. The pod door opener has a platform with a kinematic coupling which includes a plurality of pins extending upwardly in a predetermined pattern from the platform for aligning and supporting 300 millimeter wafer carriers relative to a port in the pod door opener. The wafer carrier adapter comprises a support structure having top and bottom surfaces. The support structure is provided with a plurality of recesses extending through the bottom surface adapted to receive the plurality of pins.

Abstract: Disclosed herein is a semiconductor device and a method of fabricating the same.

Abstract: A semiconductor device is tested without destroying a substrate immediately after a formation of a metal film and before patterning the metal film.To this end, the substrate is first divided into a product region and a test pattern region. Next, an insulating film is formed on the substrate. Thereafter, openings are formed in the insulating film and on the product region and the test pattern region. Subsequently, the metal film is formed in the openings and on the insulating film. Finally, the metal film is patterned to form a wiring pattern.Under these circumstances, a forming state of the metal film in the opening on the test pattern region is actually tested. Specifically, the presence or absence of a void is checked. In accordance with this test result, a forming state of the metal film in the opening in the product region is evaluated.

Abstract: The present invention provides three embodiments to deposit layers over a substrate using ultrasound energy to vibrate the substrate during (1) PVD or CVD deposition, (2) anneal or (3) plating deposition. The first embodiment deposits a first layer over a substrate using ultrasonic energy to vibrate the substrate. The ultrasound allows the layer to deposit more conformal over opening sidewalls and decreases overhangs and voids. The second embodiment involves using ultrasonic vibrations during annealing or RTA. The ultrasound smooches out barrier/seed/conductive layers in contact holes. The third embodiment is a method of plating a metal layer such as Cu over a substrate while vibrating the substrate with ultrasonic waves. The substrate is vibrated with ultrasound waves in vertical or horizontal direction. The ultrasonic vibration allow the metal to plate in small contact holes with improved step coverage.

Abstract: A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

Abstract: A method and apparatus for bonding a chip to a substrate is described, wherein the apparatus includes a chip holder assembly comprising an outer holder having a cavity formed therein and an inner holder for holding the chip, and by releaseably securing the inner holder within the outer holder cavity and contacting the chip to the substrate the inner holder has selective angular rotation within the cavity to make parallel the chip and the substrate.

Abstract: The average density and scattered light intensity or the average density and average size of void defects contained in a surface region in a predetermined depth of a semiconductor wafer sample are measured. An ingot whose a semiconductor wafer sample satisfies D.times.Is.ltoreq.a predetermined value between the measured average density D and scattered light intensity Is or satisfies D.times.L.sup.3 .ltoreq.fixed value between the measured average density D and average size L is extracted and wafers cut from the ingot are annealed. The semiconductor wafers having few residual defects in a surface region wherein devices are to be formed can be obtained.

Abstract: A method for forming an alignment mark includes defining a circuit pattern area and an alignment mark area on a semiconductor substrate, forming a first pattern in the alignment mark area, forming a second pattern of a first material on the first pattern, forming a layer of a second material different from the first on the entire surface of the semiconductor substrate, and polishing the layer of the second material and the second layer such that the second pattern and the layer of second material are polished at different speed, until a step difference appears between the second pattern and the layer.

Abstract: A method and apparatus that uses compound processing for detecting defects in integrated circuits involves processing two portions of a semiconductor wafer differently according to a first and a second process. The first process and the second process are performed on alternating columns on the wafer. Image subtraction is used to detect differences between the layouts in adjacent columns. After differences are detected, the layout is examined to determine whether the difference represents a defect. If so, the design rules of the layout can be changed to accommodate a wider process variation.

Abstract: In order to measure a width of a wire a measuring pattern for the width of the wire is prepared. The measuring pattern includes: a first pattern with a first width; a second pattern connected to the first pattern and having a second width wider than the first width; and a third pattern connected to the second pattern and having a third width narrower than the first width. The first pattern, the second pattern and the third pattern are made of same material. The first pattern through a power source is connected to the third pattern. A first pair of probes are disposed on the first pattern and then are connected to a first voltmeter. A distance between the first pair of probes is a first distance wider than the first width. A second pair of probes are disposed on the second pattern and then are connected to a second voltmeter. A distance between the second pair of probes is a second distance wider than the first width.

Abstract: A method and apparatus for controlling the introduction of contaminates into a deposition chamber that occur naturally within the chamber components. The CVD chamber is "seasoned" with a protective layer after a dry clean operation and before a substrate is introduced into the chamber. The deposited seasoning layer has a lower diffusion rate for typical contaminants in relation to the chamber component materials and covers the chamber component, reducing the likelihood that the naturally occurring contaminants will interfere with subsequent processing steps. After deposition of the seasoning layer is complete, the chamber is used for one to n substrate deposition steps before being cleaned by another clean operation as described above and then reseasoned.

Abstract: A process is disclosed for producing non-evaporable getter materials having high porosity and improved gas sorption rates. The process includes mixing together a metallic getter element, a getter alloy and a solid organic compound, all three components being in the form of powders having specific particle sizes. The mixture is subjected to a compression of less than about 1000 kg/cm.sup.2 and is sintered at a temperature between about 900.degree. C. and about 1200.degree. C. for a period between about 5 minutes and about 60 minutes. The getter material thus obtained is used to produce getter bodies shaped as pellets, sheets or discs having better mechanical strength than similar bodies of other getter material having comparable porosity.

Abstract: Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away, making sure that the barrier metal layer is not polished away. The copper layer is laser annealed to increase the grain size, remove seams, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. The part of the barrier metal layer that is not in the trenches is removed by polishing.

Abstract: Passivation of bacterial biofilm exposed surfaces is carried out utilizing cold-plasma treatments. Exposure of a substrate with biological contamination thereon to an oxygen plasma sterilizes and cross-links the biological contamination into a form which is resistant to further adhesion of bacteria and other biomaterials while cleansing and sterilizing areas of the substrate that are not covered by the biofilm. A second step may be carried out to plasma mediate the deposit of an anti-fouling film using components that will provide macromolecular networks on the substrate with a desired structure which is resistant to bacterial adhesion.

Abstract: The present invention relates to a packaging method of thin film passive components on silicon chip, which employs ceramic or glass substrate to be mounted with the silicon chip so as to improve the mechanical strength of the components, and to a method of using thick film packaging technology to package the component. The cycle time of packaging is saved and the production cost is low.

Abstract: This invention discloses an overlay measuring mark and a method of measuring an overlay error of semiconductor used by the overlay measuring mark. This overlay measuring mark comprises a first mark formed on a first layer on a semiconductor substrate and including four bar sets, which form a first square pattern, each of said bar sets at least comprising two parallel bars relatively formed by a first slim pattern; and a second mark formed on a second layer on said first layer and including four bar formed a second square pattern, wherein said four bar relatively are formed by a second slim pattern and said second square is located in and smaller than said first square in a top view.

Abstract: A method for fabricating a monolithic micro-optical component. The construction of the micro-optical components is accomplished by using standard semiconductor fabrication techniques. The method comprises the steps of depositing an etch stop layer (44) onto a semiconductor substrate (42); depositing an optical component layer (46) onto the etch stop layer (44); coating the entire surface of the optical component layer with a photoresist material; applying a photoresist mask (50) to the photoresist material on the optical component layer (46); selectively etching away the optical component layer (46) to form at least one optical column (52); forming a pedestal (54) for each of the optical columns (52) by selectively etching away the etch stop layer (44); and finally polishing each of the optical columns (52), thereby forming monolithic optical components (56).

Abstract: A device for protecting semiconductor material includes a support and a surface made of ice formed from ultrapure water. Semiconductor material is situated on this support surface.

Abstract: A method of identifying individual semiconductor devices with a unique inscription during the manufacturing process for the semiconductor devices. Each individual semiconductor device is marked during a final lithographic stepping exposure with a direct write laser mounted either in the stepper in the lithographic system working concurrently with the stepping fields during the final metal layer lithographic stepping exposure or during a post stepping pre-development treatment. The marking on the devices includes device identification, lot number and die number.

Abstract: This invention is provided to eliminate the optical proximity effect which will occur because of different rates of dimensional change between before and after etching when a plurality of gate materials are etched in a single device. After a to-be-corrected region is extracted, an n.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the n.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be a p.sup.+ -type polysilicon gate layer, thereby correcting the size of the n.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the n.sup.+ -type polysilicon gate layer. After that, a p.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the p.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be an n.sup.+ -type polysilicon gate layer, thereby correcting the size of the p.sup.