Abstract: A shield for protecting silicon wafers. The shield includes a plurality of single crystal shielding members having a lattice unit cell repeated substantially throughout. The unit cell has a periodic arrangement of atoms defining a set of lattice planes. The shielding members each include a pair of first interface surfaces having an orientation substantially aligned along one of the set of lattice planes. The shield also includes a plurality of single crystal structural members each having substantially the same lattice unit cell as that of the shielding members repeated substantially throughout. The structural members each include a pair of second interface surfaces having an orientation substantially aligned along the same one of the set of lattice planes. The plurality of shielding members and structural members are alternately bonded together at their respective first and second interface surfaces to define an enclosed area sized to receive the silicon wafers therein.

Abstract: A method is presented for fabricating an electrically isolated MEMS device having a conductive outer MEMS element, and an inner movable MEMS element spaced apart from the conductive outer MEMS element. The inner element includes a nonconductive base having a plurality of conductive structures extending therefrom. The conductive components are formed by plating a conductive material into a pre-formed mold which defines the shape of the conductor.

Abstract: In a sensor having a membrane structure, a sensor chip (silicon substrate) is provided with a through hole that is open on both upper and lower surfaces of the silicon substrate. A sensor element having a membrane structure is formed on the upper surface of the silicon substrate to close the through hole on the upper surface. The lower surface of the silicon substrate is bonded to a stem through adhesive to define a communication passage through which an inside and an outside of the through hole communicate with each other. Accordingly, the sensor can exhibit high reliability.

Abstract: A wafer processing apparatus is provided with a wafer carrier comprising a doorplate, a pedestal including one or more legs to support the pedestal on the doorplate, and a wafer rack positionable on the pedestal. A pedestal lock is connected to the doorplate and is selectively engageable with at least one of the legs to lock the pedestal to the doorplate. A lock is further provided to selectively engage at least one of the wafer rack and the pedestal to lock the wafer rack to the pedestal. The pedestal is thereby prevented from falling off of the doorplate, and the wafer rack is prevented from falling off of the pedestal, during earthquake-induced vibrations and accelerations.

Abstract: A nondestructive read-out, nonvolatile ferroelectric field effect transistor (“FET”) memory in an integrated circuit, containing a thin film of polycrystalline crystallographically oriented ferroelectric material. Preferably, the material is polycrystalline c-axis oriented layered superlattice material. More preferably, it is c-axis oriented strontium bismuth tantalate or strontium bismuth tantalum niobate.

Abstract: The present invention relates to a micro electro mechanical system (MEMS); and, more particularly, to a micro pump used in micro fluid transportation and control and a method for fabricating the same. The micro pump according to the present invention comprises: trenches formed in a silicon substrate in order to form a pumping region including a main pumping region and an auxiliary pumping region; channels formed on both sides of the pumping region; a flow prevention region having backward-flow preventing layers to resist a fluid flow; inlet/outlet regions formed at each of the channels which are disposed on both ends of the pumping region; an outer layer covering the trenches of the silicon substrate and opening portions of the inlet/outlet regions; and a thermal conducting layer formed on the outer layer and over the main pumping region so that a pressure of the fluid in the main pumping region is increased by the thermal conducting layer.

Abstract: A method for making a semiconductor light source for illuminating a physical space has been invented. In various embodiments of the invention, a semiconductor such as and LED chip, laser chip, LED chip array, laser array, an array of chips, or a VCSEL chip is mounted on a heat sink. The heat sink may have multiple panels for mounting chips in various orientations. The chips may be mounted directly to a primary heat sink which is in turn mounted to a multi-panel secondary heat sink. A TE cooler and air circulation may be provided to enhance heat dissipation. An AC/DC converter may be included in the light source fitting.

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

Abstract: Phased array components utilizing two or more different types of semiconductor in one monolithic device are provided. High quality epitaxil layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A nanosyringe is constructed using micro fabrication and nano fabrication techniques on a silicon substrate. The nanosyringe includes a membrane of silicon carbide. The position and operation of individual nanosyringes, arranged in an array of nanosyringes, can be independently controlled. A nanosyringe array can inject or extract a fluid from one or more cells or other structures. Microfluidic structures coupled to the nanosyringe allow external pumping or extraction. A cell matrix or organelles of individual cells can be non-destructively sampled in real time.

Abstract: A pick and place apparatus comprises a bond arm adapted for rotation about an axis between a pick location and a place location. The bond arm is formed with a cavity at an end of the arm remote from the axis, within which cavity are located a plurality of damping particles for damping unwanted vibrations of the bond arm. The particles may be irregular tungsten granules with a diameter between 0.3 and 1.2 mm and a filling ratio of about 75%.

Abstract: In a method of manufacturing an aluminum solid electrolyte capacitor, mass-production of aluminum solid electrolyte capacitors with high reliability and excellent quality is made possible by adopting a sequence of steps whereby it is ensured that no stress is applied to the capacitor body (for example coiled element), and by providing means that make possible implementation of these steps. A capacitor body 1 is inserted into a case 3 having a first aperture 3A that is open at the bottom and a second constricted aperture 3B at the top, via the first aperture 3A, and sealing and fixing are performed by a sealant 5 consisting of an epoxy resin, then the capacitor body 1 is coated or impregnated by introducing 3,4-ethylenedioxy-thiophene through the second aperture 3B, then solid electrolyte constituted by poly(3,4-ethylenedioxy-thiophene) is generated by an oxidative polymerization reaction, after which the second aperture 3B is sealed.

Abstract: Methods and apparatus for efficiently compensating for pressure changes in a active vibration isolation system are disclosed. According to one aspect of the present system, system that reduces the vibrations experienced by a mass includes a chamber that supports the mass, a control device, a valve mechanism, and a bypass mechanism. The control device monitors a pressure level within the chamber. The valve mechanism includes a first flow path that is in fluid communication with the chamber. The valve mechanism also alters a capacity of the first flow path in response to a control signal generated by the controller. Finally, the bypass mechanism defines a second flow path that enables fluid to flows through the second flow path into the chamber. The second flow path is parallel to the first flow path to enable parallel fluid flow to occur.

Abstract: A method of fabricating a molecular electronic device or crossbar memory device is provided. The device comprises at least one pair of crossed wires and a molecular switch film therebetween. The method comprises: (a) forming at least one bottom electrode on a substrate by first forming a first layer on the substrate and patterning the first layer to form the bottom electrode by an imprinting technique; (b) forming the molecular switch film on top of the bottom electrode; (c) optionally forming a protective layer on top of the molecular switch film to avoid damage thereto during further processing; (d) coating a polymer layer on top of the protective layer and patterned the polymer layer by the imprinting method to form openings that expose portions of the protective layer; and (e) forming at least one top electrode on the protective layer through the openings in the polymer layer by first forming a second layer on the polymer layer and patterning the second layer.

Abstract: In the previously known methods for tuning the antenna resonant circuit, in the case of passive transponders, their range in a high-frequency carrier field is generally limited to a few cm as the supply voltage for the integrated circuit gained from the carrier field falls very quickly with increasing distance.

Abstract: A method and system for manufacturing a silicon wafer is disclosed. The ingot's crystallographic orientation is identified. Then ingot indicia is marked onto the ingot. The ingot indicia includes the manufacturer's data as well as the ingot's specific information. The indicia also identifies the crystallographic orientation of the ingot. A plurality of wafers are sliced from the ingot with a portion of the ingot indicia on each of the wafers. Wafer indicia is then marked onto a peripheral edge of the wafer. The wafer indicia includes a mark to identify the crystallographic orientation of the wafer as well as specific information about the ingot and the wafer. The wafer indicia may include dopant levels as well as resistivity and conductivity levels of the wafer.

Abstract: An exemplary method of forming a contact hole having a critical dimension which is smaller than one minimum lithographic feature can include providing a photoresist layer over a layer of material in which a contact hole is to be formed, etching the photoresist layer with an aperture having a first critical dimension, providing a bacteria film on the surface of the layer of photoresist which includes lateral side walls of the aperture, and etching a contact hole in the layer of material. The bacteria film decreases the aperture in width to a second critical dimension. The contact hole has the second critical dimension.

Abstract: A method for achieving improved piezoelectric films for use in a resonator device is disclosed. The method is based on applicant's recognition that the texture of a piezoelectric film (e.g., as used in a piezoelectric resonator) is directly affected by the surface morphology of the underlying electrode, and additionally, the surface morphology of the electrode is affected by the surface morphology of the underlying oxide layer or Bragg stack. Accordingly, the invention includes a method of making a device having a piezoelectric film and electrode including controlling the deposition and surface roughness of the electrode and optionally, the Bragg stack.

Abstract: A method is provided for pre-treating reactor parts, comprising quartz or silicon, in use in chemical vapor deposition reactors. Applying the pre-treatment prior to deposition increases the cumulative deposited film thickness that can be received by the reactor parts before contamination of wafers processed in said reactors exceeds acceptable limits. The pre-treatment comprises nitridation of the surface of the reactor part, such as by heating the reactor part to a temperature of at least 800° C. and exposing the reactor part to a nitrogen-containing gas.

Abstract: Adhesion of particles on the surface of a wafer is prevented even if particles are generated during transport, by transferring the wafers after mirror-polishing, cleaning, and drying into a container body having an opening which is closed and hermetically sealed with a cover after introduction of the wafers. The container body is disposed so that the opening is oriented in a direction other than an upward direction, and with the container body in this attitude dry air is supplied through the opening to replace the air in the container body with dry air. Then the container is oriented with the opening facing a wafer supply position and wafers are transferred into the container while the dry air is maintained in the container, after which the top cover is attached to the container body, with all of these steps being performed under highly clean air having an absolute water content of 2 ppm or less.

Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract: A memory device and related methods are described. The memory device includes a plurality of cells, each cell including a MOSFET having a source coupled to a first end of a channel, a drain coupled to a second end of the channel, a gate formed on a gate insulator and extending from the source to the drain and a plurality of conductive islands, each surrounded by an insulator, formed in the channel. The islands have a maximum dimension of three nanometers. The surrounding insulator has a thickness of between five and twenty nanometers. Each island and surrounding insulator is formed in a pore extending into the channel. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

Abstract: An improved method of fabricating nanometer-scale devices is provided, wherein the improvement comprises: (1) employing materials for a first electrode, a first insulating layer, if present, a molecular switch layer, a second insulating layer, if present, and a second electrode that permit photopatterning of the second electrode; and (2) photopatterning at least the second electrode without adversely affecting the molecular switch layer. The improved method incorporates known techniques on a smaller scale than previously done to provide a means to move away from shadow mask electrodes (many micrometers wide), presently used in nanometer-scale devices, and move to nanometer dimensions. The improved method further facilitates integration of nanometer-scale devices to larger silicon-based technology.

Abstract: In a patterning process of a semiconductor device having inverted stagger type TFTs, a normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist is applied, and a problem of the area dependency of the photo resist pattern side wall taper angle may occur. The problem is critical for the reason of influence on variation of an etching shape in a dry-etching step. The present invention has an object to solve the above problem. In a photolithography step, which is patterning step of a semiconductor device having inverted stagger type TFTs, by adjusting a pre-bake temperature or a PEB (post-exposure-bake) temperature, and positively performing evacuation of solvent in a state of a photo resist film, the volume contraction by evacuation of solvent at the post-bake is reduced, and the problem of the area dependency of the photo resist pattern side wall taper angle is solved, which is deformation due to the volume contraction.

Abstract: An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in said opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming the recessed chalcogenide-metal ion material comprises forming a metal material being recessed approximately 10-90%, in the opening in the dielectric material, forming a glass material on the metal material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

Abstract: Methods are disclosed for dividing a pattern in a segmented reticle such as used in charged-particle-beam microlithography. In the methods, the reticle pattern is divided among multiple subfields delineated by respective initial subfield-boundary lines. In an exemplary embodiment, initial subfield-boundary lines are determined by determining respective extensions of pattern elements in each of the X and Y directions. For example, if the extension in the Y direction is longer than in the X direction, then an initial pattern division (including into complementary subfields as required) is made using the initial subfield-boundary extending in the X direction. If the pattern exhibits a period repeat in the Y direction, then the initial subfield-boundary lines are established at an integer multiple of half the period repeat.

Abstract: A method for making a microstructure assembly, the method including the steps of providing a first substrate and a second substrate; depositing an electrically conductive material on the second substrate; contacting the second substrate carrying the electrically conductive material with the first substrate; and then supplying current to the electrically conductive material to locally elevate the temperature of said electrically conductive material and cause formation of a bond between the first substrate and the second substrate.

Abstract: A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. A first general feature of the process is to define suspended structures with a DRIE process, such that the dimensions desired for the suspended structures are obtained. A second general feature is the proper location of specialized features, such as stiction bumps, vulnerable to erosion caused by the DRIE process. Yet another general feature is to control the environment surrounding suspended structures delineated by DRIE in order to obtain their desired dimensions. A significant problem identified and solved by the invention is the propensity for the DRIE process to etch certain suspended features at different rates.

Abstract: A substrate storage cassette positioning device and method for positioning a substrate storage cassette in a predetermined location on an installation platform, comprising a guide section for guiding the substrate storage cassette into a predetermined location during the positioning of the substrate storage cassette.

Abstract: In precision equipment such as a semiconductor exposure apparatus, an inertial load is driven by using an actuator, and an actuator fixed to a structure such as a vibration isolation base, an apparatus mounted on the base, and a control force is applied to the structure by using a drive reaction force generated upon driving of the inertial load, thereby stably and quickly suppressing produced vibrations.

Abstract: A plant for producing semiconductor products is described and has a plurality of production and measuring units in at least one clean room. Provided there is a configuration of processing stations, which has at least one production unit or measuring unit, a production buffer disposed at the latter for the deposition of semiconductor products and a handling device for the automatic delivery and outward transport of the semiconductor products. The processing stations are interconnected via a conveyor system.

Abstract: A method for conditioning the inside walls of a process chamber is described incorporating a selected process gas such as Br, Br2, HBr, Cl2, HCl, F2, SiFx, and NF3, a pressure controller, and a timer for soaking the chamber. The invention overcomes the problem of running dummy product wafers to condition the chamber.

Abstract: Damaged low-density silicon oxide-based films having an Si—O backbone are repaired using a method for driving a self-limiting healing process. According to an example embodiment of the present invention, a deposition precursor and an oxidizer are introduced to a damaged side wall region of a low-density silicon oxide-based film. The unstable damaged portion of the film reacts with the deposition precursor and a thin repair film is grown within the interfacial layer of the damaged film. The repair film provides a strengthened interface, protects the underlying sensitive material from further chemical damage, and can improve the ability to integrate the film.

Abstract: The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first metal on the substrate; depositing a second metal on the initial nanowires of the first metal to form thickened nanowires that are more resistant to etching than the initial nanowires; and etching the substrate to form atomic ridges separated by grooves having a pitch of 0.94 to 5.35 nm. The present invention also provides a method for forming Au and other metal nanowires that may be used for electrical conductors and both positive and negative etch masks to form a plurality of ridges at a pitch of 0.94 to 5.35 nm containing at least two adjacent grooves with widths of 0.63 to 5.04 nm.

Abstract: Within a method for forming a metal-silicon layer there is first provided a reactor chamber. There is then positioned within the reactor chamber a substrate spaced from a metal source target. There is also provided within the reactor chamber a minimum of a sputter material and a reactive silicon material. There is then sputtered the metal source target positioned within the reactor chamber with the sputter material provided within the reactor chamber in the presence of the reactive silicon material provided within the reactor chamber to form a metal-silicon layer over the substrate. The method is particularly useful for forming metal silicate layers, metal silicon nitride layers and metal silicon oxynitride layers within microelectronic fabrications. An alternative method employs: (1) a silicon source target rather than a metal source target; and (2) a reactive metal material rather than a reactive silicon material.

Abstract: The present invention relates to a micro electro mechanical system (MEMS); and, more particularly, to a micro pump used in micro fluid transportation and control and a method for fabricating the same. The micro pump according to the present invention comprises: trenches formed in a silicon substrate in order to form a pumping region including a main pumping region and an auxiliary pumping region; channels formed on both sides of the pumping region; a flow prevention region having backward-flow preventing layers to resist a fluid flow; inlet/outlet regions formed at each of the channels which are disposed on both ends of the pumping region; an outer layer covering the trenches of the silicon substrate and opening portions of the inlet/outlet regions; and a thermal conducting layer formed on the outer layer and over the main pumping region so that a pressure of the fluid in the main pumping region is increased by the thermal conducting layer.

Abstract: A method of manufacturing a fabric article to include electronic circuitry in which a flex circuit is assembled to include conductive traces and pads on a flexible substrate, a fabric article is placed on a rigid surface, and the substrate of the flex circuit is secured to the fabric article. Also disclosed is a fabric article which includes electronic circuitry and an electrically active textile article.

Abstract: A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.

Abstract: The method addresses and interrogates addressable cells having at least one element including a polysilicon resistor functioning as a heating element and blocking diode preventing sneak current to un addressed elements, for selectively addressing one of the cells using row and column address line in a thin film structure having a minimum number of address lines and a minimum number of layers. The resistor heating element can be used for igniting a respective fuel cell in an array of fuel cells disposed in a thin film microthruster. After ignition, the address lines are used to interrogate the cell location for verification of fuel cell ignition well suited for monitoring fuel burns and usage of the microthruster.

Abstract: A wafer processing system which requires no isolation between the operational areas within the processing system. The system of the present invention includes operational areas, such as a loading area, a transport area, and a reactor or thermal processing area. Advantageously, since there are no isolation devices or gate valves separating the areas, the processing system effectively has each operational area combined into a “single” chamber. Preferably, the single chamber has a single slit valve, hinge door, or other vacuum sealable door disposed proximate to the loading area to allow for the removal/insertion of the wafers into the loading area. Once the door to the loading area has been closed the internal pressure within the chamber can be kept uniform throughout each operational area.

Abstract: The present invention relates to fabrication and application of nano-manipulators with induced growth using a focused particle beam. Induced growth may be used to fabricate nano-manipulators, such as a nano-tweezers or grippers, which allows for a very precise and flexible design. Also, applying the growth techniques together with nano-manipulators provides a strong tool for performing complex operations performing pick & place operations with nanoscale structures and fabrication of other nano-manipulators.

Abstract: A semiconductor fabricating device and method that minimize the influence of a process deteriorating material that is generated during first processes on second processes, when the plurality of processes are continually performed step by step. Operational failures are prevented during the course of the semiconductor fabricating processes, by directing air flow from a location where the second processes are carried out to a location where the first processes are carried out, to carry the process deteriorating gas away from the second processes. This reduces the frequency of failures during processing.

Abstract: A paste applicator and paste application method for die bonding apply paste to adhere a semiconductor chip on a substrate. Data on paste application volume and application pattern which can be identified from paste thickness and chip size are stored. A dispensing flow rate calculator calculates dispensing flow rate of a dispenser based on the paste application volume data and application pattern data when the paste is dispensed from the dispenser and pressure fed to an application nozzle for applying paste. Based on this calculated dispensing flow rate and application pattern data, a dispenser controller controls the dispenser and a transfer table controller controls the transfer table for moving the application nozzle.

Abstract: Method and system for real-time in-situ interactive supervision of a step performed in a tool during semiconductor wafer fabrication process. The system includes a tool and the computer attached thereto, an end point detection controller, a database and a supervisor to supervise the whole wafer processing for that step. The controller is used to monitor a key process parameter of the step and is adapted to perform in-situ measurements. The database contains the evolution of said process parameter in normal operating conditions and in all the identified deviations. It further contains the history of the wafer until this step and a reference to the batch and process names for this step and the wafer identification number. At the end of the step, the important process parameters and any alert code are stored in the database to up-date the wafer history. This technique allows a total clusterized wafer fabrication process and prevents wafer rejection.

Abstract: Provided herein is a substrate processing system, which comprises a cassette load station; a load lock chamber; a centrally located transfer chamber; and one or more process chambers located about the periphery of the transfer chamber. The load lock chamber comprises double dual slot load locks constructed at same location. Such system may be used for processing substrates for semiconductor manufacturing.

Abstract: The physical movement of reticles and solder bump masks within a wafer processing plant are continually tracked and documented in a historical database for the useful life of the reticles or masks. In an example embodiment of the mask tracking method, the method includes moving the masks from one location to another in mask pods. In addition, a mask data set is generated for each mask composed of a mask identification code cross-referenced to a pod identification code and the mask data sets are then stored in a computer arrangement. The mask data sets are then updated in the computer arrangement to include a facility location identification code as each mask moves to a subsequent location during wafer processing. An important advantage is that wafer lots and reticles can now be matched to an event on the processing line and stored as data for later review and analysis.

Abstract: A method of measuring at least one parameter associated with a portion of a sample having formed thereon one or more structures with at least two zones each having an associated zone reflectance property. The method includes the steps of illuminating the zones with broadband light, and measuring at least one reflectance property of light reflected from the at least two zones. The measurement includes a substantial portion of non-specularly scattered light, thereby increasing the quality of the measurement. The method further includes the step of fitting a parameterized model to the measured reflectance property. The parameterized model mixes the zone reflectance properties of the zones to account for partially coherent light interactions between the two zones.

Abstract: A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions.

Abstract: The present method of forming a silicon oxide layer comprises providing two frequency excitation plasma CVD device which comprises a high frequency electrode, a susceptor electrode, and two matching box for impedance matching between the electrodes and a power supply, wherein one side electrode constituting a tuning condenser of a matching box toward the high frequency electrode is the high frequency electrode; placing a substrate on the susceptor electrode; applying high frequency electric power on the high frequency electrode and the susceptor electrode respectively; and forming a silicon oxide layer on the substrate by generating plasma with using a reaction gas of which main reaction gas is a mixing gas of monosilane and nitrous oxide.

Abstract: A method for developing a pattern, on a photosensitive material of negative type, including the steps of depositing the photosensitive material on a surface of a semiconductor substrate; drying the material to obtain the adherence of the material while maintaining some flexibility to it; exposing, according to a desired pattern, regions of the photosensitive material; and annealing to solidify the photosensitive material.