Having Selenium Or Tellurium Elemental Semiconductor Component Patents (Class 438/84)
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Publication number: 20090250692Abstract: A room temperature radiation detector is made from a semi-insulating Cd1-xZnxTe crystal, where 0?x?1, having a first electrode made of Pt or Au on one surface of the crystal and a second electrode of Al, Ti or In on another surface of the crystal. In use of the crystal to detect radiation events, an electrical bias is applied between the first and second electrodes.Type: ApplicationFiled: April 7, 2009Publication date: October 8, 2009Applicant: EV PRODUCTS, INC.Inventors: Csaba Szeles, Utpal K. Chakrabarti
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Publication number: 20090246906Abstract: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be microflakes that have a high aspect ratio. The resulting dense film formed from microflakes are particularly useful in forming photovoltaic devices.Type: ApplicationFiled: January 30, 2009Publication date: October 1, 2009Inventors: Matthew R. Robinson, Jeroen K.J. Van Duren, Craig Leidholm
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Publication number: 20090217967Abstract: Embodiments of the present invention provide a solar energy converter, which includes a silicon layer having at least two regions of a first and a second conductivity type that form a P-N junction, at least a portion of the silicon layer being porous, and pores in the portion of porous silicon containing a semiconductor material, the semiconductor material being different from silicon; and a first and a second electrode being placed at a bottom and a top surface of the silicon layer respectively. Methods of manufacturing the same are also provided.Type: ApplicationFiled: February 29, 2008Publication date: September 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold J. Hovel, Joel P. de Souza, Devendra K. Sadana
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Patent number: 7582506Abstract: The present invention relates to systems and methods for preparing metallic precursor thin films for the growth of semiconductor compounds to be used for radiation detector and solar cell fabrication. In one aspect, there is provided a method of efficiently using expensive materials necessary for the making of solar cells.Type: GrantFiled: January 8, 2007Date of Patent: September 1, 2009Assignee: Solopower, Inc.Inventor: Bulent M. Basol
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Patent number: 7550313Abstract: A method for forming a Phase Change Material (PCM) cell structure comprises forming both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of both the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition thereof, thereby forming high electrical resistance regions between the cells.Type: GrantFiled: July 21, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: John Christopher Arnold, Tricia Breen Carmichael
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Patent number: 7547569Abstract: A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe2 with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe2 etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.Type: GrantFiled: November 22, 2006Date of Patent: June 16, 2009Assignee: Applied Materials, Inc.Inventors: Timothy Weidman, Li Xu, Peter G. Borden
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Publication number: 20090133745Abstract: The invention relates to a photovoltaic cell comprising a photovoltaically active semiconductor material, wherein the photovoltaically active semiconductor material is a p- or n-doped semiconductor material comprising a binary compound of the formula (I) or a ternary compound of the formula (II): ZnTe??(I) Zn1-xMnxTe??(II) where x is from 0.01 to 0.99, and a particular proportion of tellurium ions in the photovoltaically active semiconductor material has been replaced by halogen ions and nitrogen ions and the halogen ions are selected from the group consisting of fluoride, chloride and bromide and mixtures thereof.Type: ApplicationFiled: October 26, 2005Publication date: May 28, 2009Applicant: BASF AktiengesellschaftInventor: Hans-Josef Sterzel
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Publication number: 20090130796Abstract: The invention relates to a method for production of thin layers of semiconductor alloys of the I-III-VI2 type, including sulphur, for photovoltaic applications, whereby a heterostructure is firstly deposited on a substrate comprising a thin layer of precursor I-III-VI2 which is essentially amorphous and a thin layer, including at least some sulphur, the heterostructure is then annealed to promote the diffusion of the sulphur into the precursor layer and the at least partial crystallization of the I-III-VI2 alloy of the precursor layer with a stoichiometry which hence includes sulphur. A layer of selenium may also be deposited to assist the recrystallization processes or annealing.Type: ApplicationFiled: May 19, 2006Publication date: May 21, 2009Applicants: ELECTRICITE DE FRANCE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE-CNRSInventors: Stephane Taunier, Daniel Lincot, Jean-Francois Guillemoles, Negar Naghavi, Denis Guimard
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Publication number: 20090130794Abstract: Thermal evaporation apparatus for depositing of a material on a substrate, comprising material storage means; heating means to generate a vapour of the material in the material storage means; vapour outlet means comprising a vapour receiving pipe having vapour outlet passages, and emission reducing means arranged such that an external surface of the vapour outlet means directed to said substrate exhibits low emission, and wherein the apparatus further comprises pipe heating means in the interior of said vapour outlet means, wherein at least the surfaces of the material storage means, heating means, and emission reducing means and pipe heating means arranged to come into contact with the material vapour are of a corrosion-resistant material.Type: ApplicationFiled: April 20, 2007Publication date: May 21, 2009Inventors: Volker Probst, Walter Stetter
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Publication number: 20090111209Abstract: A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe2 with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe2 etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.Type: ApplicationFiled: December 30, 2008Publication date: April 30, 2009Inventors: Timothy WEIDMAN, Li Xu, Peter G. Borden
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Patent number: 7514367Abstract: A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.Type: GrantFiled: May 11, 2006Date of Patent: April 7, 2009Assignee: Macronix International Co., Ltd.Inventors: Hsiang Lan Lung, Chiahua Ho, Shih Hung Chen, Chieh Fang Chen
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Patent number: 7511297Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.Type: GrantFiled: September 14, 2007Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jang, Ki-Nam Kim, Soon-Moon Jung
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Patent number: 7510929Abstract: A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.Type: GrantFiled: October 18, 2006Date of Patent: March 31, 2009Assignee: Macronix International Co., Ltd.Inventor: Chieh Fang Chen
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Publication number: 20090032108Abstract: An absorber layer of a photovoltaic device may be formed on an aluminum or metallized polymer foil substrate. A nascent absorber layer containing one or more elements of group IB and one or more elements of group IIIA is formed on the substrate. The nascent absorber layer and/or substrate is then rapidly heated from an ambient temperature to an average plateau temperature range of between about 200° C. and about 600° C. and maintained in the average plateau temperature range 1 to 30 minutes after which the temperature is reduced.Type: ApplicationFiled: March 31, 2008Publication date: February 5, 2009Inventors: Craig Leidholm, Brent Bollman, Yann Roussillon
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Publication number: 20080305573Abstract: The invention relates to a photovoltaically active semiconductor material and a photovoltaic cell comprising a photovoltaically active semiconductor material, wherein the photovoltaically active semiconductor material contains a crystal lattice composed of zinc telluride and, in the zinc telluride crystal lattice, ZnTe is substituted by—0.01 to 10 mol % CoTe, —0 to 10 mol % Cu2Te, Cu3Te or CuTe and —0 to 30 mol % of at least one compound selected from the group MgTe and MnTe, and wherein, in the zinc telluride crystal lattice Te is substituted by—0.1 to 30 mol % oxygen. The photovoltaic cell furthermore has a rear contact composed of a rear contact material that forms a metal telluride with tellurium.Type: ApplicationFiled: December 18, 2006Publication date: December 11, 2008Applicant: BASF SEInventor: Hans-Josef Sterzel
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Publication number: 20080169025Abstract: A method of forming a doped Group IBIIIAVIA absorber layer for solar cells by reacting a a metallic precursor layer with a dopant structure. The metallic precursor layer including Group IB and Group IIIA materials such as Cu, Ga and In are deposited on a base. The dopant structure is formed on the metallic precursor layer, wherein the dopant structure includes a stack of one or more Group VIA material layers such as Se layers and one or more a dopant material layers such as Na.Type: ApplicationFiled: September 10, 2007Publication date: July 17, 2008Inventors: Bulent M. Basol, Serdar Aksu, Yuriy Matus
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Publication number: 20080124831Abstract: Methods and devices are provided for high-throughput printing of semiconductor precursor layer from microflake particles. In one embodiment, the method comprises of transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be microflakes that have a high aspect ratio. The resulting dense film formed from microflakes are particularly useful in forming photovoltaic devices.Type: ApplicationFiled: June 19, 2007Publication date: May 29, 2008Inventors: Matthew R. Robinson, Jeroen K. J. Van Duren, Craig Leidholm, Brian M. Sager
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Patent number: 7323356Abstract: Disclosed is a method of producing an LnCuOX single-crystal thin film (wherein Ln is at least one selected from the group consisting of lanthanide elements and yttrium, and X is at least one selected from the group consisting of S, Se and Te), which comprises the steps of growing a base thin film on a single-crystal substrate, depositing an amorphous or polycrystalline LnCuOX thin film on the base thin film to form a laminated film, and then annealing the laminated film at a high temperature of 500° C. or more.Type: GrantFiled: February 19, 2003Date of Patent: January 29, 2008Assignee: Japan Science and Technology AgencyInventors: Hideo Hosono, Masahiro Hirano, Hiromichi Ota, Masahiro Orita, Hidenori Hiramatsu, Kazushige Ueda
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Patent number: 7294527Abstract: The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a metal-rich metal chalcogenide, such as, for example, silver-rich silver selenide. Advantageously, the processes can form the metal-rich metal chalcogenide without the use of photodoping techniques and without direct deposition of the metal. For example, the process can remove selenium from silver selenide.Type: GrantFiled: October 27, 2005Date of Patent: November 13, 2007Assignee: Micron Technology Inc.Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore
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Publication number: 20070257255Abstract: A method of forming a CIGSS absorber layer includes the steps of providing a metal precursor, and selenizing the metal precursor using diethyl selenium to form a selenized metal precursor layer (CIGSS absorber layer). A high efficiency solar cell includes a CIGSS absorber layer formed by a process including selenizing a metal precursor using diethyl selenium to form the CIGSS absorber layer.Type: ApplicationFiled: May 8, 2007Publication date: November 8, 2007Inventors: Neelkanth G. Dhere, Ankur A. Kadam
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Patent number: 7161225Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.Type: GrantFiled: January 19, 2005Date of Patent: January 9, 2007Assignee: Intel CorporationInventors: Daniel Xu, Chien Chiang
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Patent number: 7087454Abstract: A resistance variable memory element with improved data retention and switching characteristics switched between resistance memory states upon the application of write pulses having the same polarity. The resistance variable memory element can be provided having at least one silver-selenide layer in between glass layers, the glass layers are a chalcogenide glass having a GexSe100?x composition.Type: GrantFiled: March 16, 2004Date of Patent: August 8, 2006Assignee: Micron Technology, Inc.Inventors: Kristy A. Campbell, John T. Moore, Terry L. Gilton
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Patent number: 6913943Abstract: This invention is a layered thin film semiconductor device comprising a first transparent layer; a thin, second transparent layer having a conductivity less than the first transparent layer; an n-type layer; and a p-type layer comprising one or more IIB and VIA elements. This invention is also a method for making such semiconductor device. The thin film semiconductor devices of this invention are useful for making photovoltaic devices.Type: GrantFiled: May 7, 2002Date of Patent: July 5, 2005Assignee: BP Corporation North America Inc.Inventors: Daniel W. Cunningham, Marc P. Rubcich
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Patent number: 6861267Abstract: A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.Type: GrantFiled: September 17, 2001Date of Patent: March 1, 2005Assignee: Intel CorporationInventors: Daniel Xu, Chien Chiang
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Publication number: 20040253761Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.Type: ApplicationFiled: August 27, 2003Publication date: December 16, 2004Inventors: Howard E. Rhodes, Inna Patrick, Richard A. Mauritzson
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Patent number: 6825409Abstract: A thin-film solar cell and a method of producing a thin-film solar cell. The thin-film solar cell includes an absorber layer and at least one transparent window electrode. The window electrode is produced with a first metal-based thin-film, which receives an anti-reflection treatment, at least on the side of which the light is incident. Further, at least one first highly light-refracting oxide or nitride layer is provided between the absorbent layer and the first metallic layer. As a result, conductivity of the electrode window is improved and, at the same time, a thickness compared to conductivity of the window electrode is reduced.Type: GrantFiled: December 21, 2001Date of Patent: November 30, 2004Assignee: Saint-Gobain Glass FranceInventors: Wulf Haussler, Nikolas Janke, Jurgen Schutt
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Patent number: 6815250Abstract: A method for manufacturing an infrared detector forms a p-n junction by forming a low concentration p type HgCdTe layer, forming a diffusion preventing layer for exposing some upper part of the low concentration p type HgCdTe layer, and by forming a low concentration n type HgCdTe layer by diffusing hydrogen ions and atoms to the low concentration p type HgCdTe layer using hydrogen plasma. The hydrogen ions or atoms are diffused on some of the low concentration p type HgCdTe layer to be a predetermined depth using the hydrogen plasma to form the low concentration n type HgCdTe layer in order to prevent an interface of the p-n junction from damaging, and thereby leakage current can be prevented, fabrication cost is not increased and yield is increased due to simple processes.Type: GrantFiled: January 15, 2003Date of Patent: November 9, 2004Assignee: Agency for Defense DevelopmentInventors: Hee Chul Lee, Ki Dong Yang
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Patent number: 6800504Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.Type: GrantFiled: November 1, 2002Date of Patent: October 5, 2004Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Allen McTeer
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Patent number: 6784018Abstract: A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.Type: GrantFiled: August 29, 2001Date of Patent: August 31, 2004Assignee: Micron Technology, Inc.Inventors: Kristy A. Campbell, John T. Moore
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Patent number: 6709958Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.Type: GrantFiled: August 30, 2001Date of Patent: March 23, 2004Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Allen McTeer
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Publication number: 20030154909Abstract: The invention pertains to the methods of obtaining anisotropic crystalline films and to devices for carrying out the methods. A colloidal system with anisometric particles is applied as a film onto the surface of a substrate while the viscosity of the colloidal system is lowered. The particles of the colloidal system with lowered viscosity are oriented and the original viscosity of the colloidal system is restored. The film is then dried. The drying is carried out under controlled conditions. Zones of the dried film may be progressively heated to improve the film characteristics.Type: ApplicationFiled: April 14, 2003Publication date: August 21, 2003Inventors: Pavel I. Lazarev, Victor V Nazarov, Natalya A Ovchinnikova
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Patent number: 6548751Abstract: A thin-film flexible solar cell built on a plastic substrate comprises a cadmium telluride p-type layer and a cadmium sulfide n-type layer sputter deposited onto a plastic substrate at a temperature sufficiently low to avoid damaging or melting the plastic and to minimize crystallization of the cadmium telluride. A transparent conductive oxide layer overlaid by a bus bar network is deposited over the n-type layer. A back contact layer of conductive metal is deposited underneath the p-type layer and completes the current collection circuit. The semiconductor layers may be amorphous or polycrystalline in structure.Type: GrantFiled: June 25, 2001Date of Patent: April 15, 2003Assignee: SolarFlex Technologies, Inc.Inventors: Lawrence H. Sverdrup, Jr., Norman F. Dessel, Adrian Pelkus
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Patent number: 6465273Abstract: A light emitting device includes an LED chip fixed to an electrode body via a conductive layer of In or an In alloy. The conductive layer is in ohmic-contact with an n-type ZnSe crystal substrate of the LED chip. To make the device, In or an In alloy is melted on the electrode body, the ZnSe substrate is placed directly on the melted In or In alloy and then subjected to at least one of vibration and pressure to achieve a good bond and ohmic contact between the In or In alloy and the ZnSe substrate.Type: GrantFiled: May 4, 2000Date of Patent: October 15, 2002Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideki Matsubara, Koji Katayama, Akihiko Saegusa
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Patent number: 6362483Abstract: Visible-blind UV detectors are disclosed comprising an active layer of ZnSTe alloy. The Te composition can be varied to provide good lattice matching depending on the nature of the substrate (eg Si, GaP or GaAs) and a novel structure is provided to give high quantum efficiency. The invention also discloses UV detectors with an active layer of pure ZnS and with an active layer of ZnSSe.Type: GrantFiled: December 29, 1998Date of Patent: March 26, 2002Assignee: The Hong Kong University of Science & TechnologyInventors: Iam Keong Sou, Zhaohui Ma, Choi Lai Man, Zhi Yu Yang, Kam Sang Wong, George Ke-Lun Wong
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Patent number: 6281035Abstract: A method of making a low-resistance electrical contact between a p-CdTe layer and outer contact layers by ion beam processing comprising: a) placing a CdS/CdTe device into a chamber and evacuating the chamber; b) orienting the p-CdTe side of the CdS/CdTe layer so that it faces apparatus capable of generating Ar atoms and ions of preferred energy and directionality; c) introducing Ar and igniting the area of apparatus capable of generating Ar atoms and ions of preferred energy and directionality in a manner so that during ion exposure, the source-to-substrate distance is maintained such that it is less than the mean-free path or diffusion length of the Ar atoms and ions at the vacuum pressure; d) allowing exposure of the p-CdTe side of the device to said ion beam for a period less than about 5 minutes; and e) imparting movement to the substrate to control the real uniformity of the ion-beam exposure on the p-CdTe side of the device.Type: GrantFiled: September 25, 1997Date of Patent: August 28, 2001Assignee: Midwest Research InstituteInventor: Timothy A. Gessert
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Patent number: 6046068Abstract: A method, suitable for forming metal contacts on a semiconductor substrate at positions for defining radiation detector cells, includes the steps of forming one or more layers of material on a surface of the substrate with openings to the substrate surface at the contact positions; forming a layer of metal over the layer(s) of material and the openings; and removing metal overlying the layer(s) of material to separate individual contacts. Optionally, a passivation layer to be left between individual contacts on the substrate surface may be applied. Etchants used for removing unwanted gold (or other contact matter) are preferably prevented from coming into contact with the surface of the substrate, thereby avoiding degradation of the resistive properties of the substrate.Type: GrantFiled: November 26, 1996Date of Patent: April 4, 2000Assignee: Simage OyInventors: Risto O. Orava, Jouni I. Pyyhtia, Tom G. Schulman, Miltiadis E. Sarakinos, Konstantinos E. Spartiotis, Panu Y. Jalas
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Patent number: 6036771Abstract: In a method of manufacturing an optical semiconductor device having a semiconductor substrate, an optical waveguide formed by a semiconductor layer is formed on the semiconductor substrate by the use of the selective metal-organic vapor phase epitaxy including source materials. The source materials are intermittently supplied in the selective metal-organic vapor phase epitaxy.Type: GrantFiled: September 29, 1998Date of Patent: March 14, 2000Assignee: NEC CorporationInventor: Yasutaka Sakata
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Patent number: 6036822Abstract: A base is provided with a gas outlet pipe and a gas inlet pipe. A bell jar is placed on top of the base with an O-ring interposed between them. Thin-film solar cells and a Se powder are placed in a recess formed in a lower heating jig, and the lower heating jig is positioned on the base. An upper heating jig is placed on top of the lower heating jig. The upper heating jig is vertically moved by a vertically actuating mechanism. The upper and lower heating jigs are heated with a heater so as to react Se with the thin-film solar cells, whereby a CuInSe.sub.2 alloy film is formed. In a method of manufacturing a thin-film solar cell, a molybdenum layer and a copper layer are formed on a substrate by sputtering. A selenium-dispersed indium layer is formed on the copper layer in a solution, which includes indium ions and dispersed selenium colloid, by electrodeposition. The thus formed selenium-dispersed indium layer and the selenium are heated in a sealed container.Type: GrantFiled: January 20, 1998Date of Patent: March 14, 2000Assignee: Yazaki CorporationInventors: Takeshi Ikeya, Kenji Sato, Kazuhiro Toyoda, Takeshi Kamiya
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Patent number: 6023020Abstract: A solar cell utilizing a chalcopyrite semiconductor and reducing the density of defects on the junction interface of pn junctions is provided. This solar cell includes a substrate, a back electrode formed on the substrate, a p-type chalcopyrite semiconductor thin film formed on the back electrode, an n-type semiconductor thin film formed so as to constitute a pn junction with the p-type chalcopyrite semiconductor thin film, and a transparent electrode formed on the n-type semiconductor thin film. A material having a higher resistivity than the p-type chalcopyrite semiconductor is formed between the p-type chalcopyrite semiconductor thin film and the n-type semiconductor thin film. A thin film made of this material may be formed by deposition from a solution. For example, CuInS.sub.2 is formed on the surface of a p-type chalcopyrite based semiconductor such as CuInSe.sub.Type: GrantFiled: October 14, 1997Date of Patent: February 8, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mikihiko Nishitani, Takayuki Negami, Naoki Kohara, Takahiro Wada, Yasuhiro Hashimoto
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Patent number: 6001669Abstract: Epitaxial layers of II-VI semiconductor compounds having low incidence of lattice defects such as stacking faults are produced by first depositing a fraction of a monolayer of the cation species of the compound, followed by depositing a thin layer of the compound by migration enhanced epitaxy (MEE). Growth of the remainder of the layer by MBE results in much lower defects than if the entire layer had been grown by MBE. Layers are useful in devices such as LEDs and injection lasers.Type: GrantFiled: July 21, 1992Date of Patent: December 14, 1999Assignee: Philips Electronics North America CorporationInventors: James Matthew Gaines, John Petruzzello
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Patent number: 5994163Abstract: A method of manufacturing thin-film solar cells that include a layer of copper indium selenide (CuInSe.sub.2) that is applied in one manufacturing step onto a substrate that includes a metal layer that defines an electrical back contact layer of the solar cell. A layer that contains an alkali metal, such as sodium, is formed on the cell structure before the CuInSe.sub.2 layer is applied.Type: GrantFiled: April 17, 1997Date of Patent: November 30, 1999Assignee: Nordic Solar Energy ABInventors: Marika Bodeg.ang.rd, Jonas Hedstrom, Lars Stolt
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Patent number: 5989933Abstract: In one embodiment, a semiconductor structure is disclosed. The structure includes both a silicon and a cadmium telluride layer. Each may have a (100) lattice orientation. A plurality of buffer layers are disposed between the silicon layer and the cadmium telluride layer. Each of these buffer layers has a lattice constant which is greater than the lattice constant of the layer below it and less than the lattice constant of the layer above it. As examples, these buffer layers may comprise zinc sulfide, zinc selenide, zinc telluride or zinc tellurium selenide.Type: GrantFiled: September 17, 1997Date of Patent: November 23, 1999Assignee: DRS Technologies, Inc.Inventors: Malcolm J. Bevan, Hung-Dah Shih
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Patent number: 5986205Abstract: The stainless steel sheet useful as a substrate for non-single crystalline semiconductor solar cells has minute ripples with undulations along a rolling direction, and its surface roughness is controlled in the range of R.sub.z 0.3-1.4 .mu.m and R.sub.max 0.5-1.7 .mu.m. It is manufactured by finish cold rolling a stainless steel strip with a reduction ratio of at least 20% at a rolling speed of at least 400 m/min. using work rolls polished with abrasives of gage #100-#400 at a final pass, annealing the rolled strip in an open-air atmosphere and then electrolytically pickling the annealed strip in a nitric acid solution. Since minute ripples with undulations are formed on the surface of the stainless steel sheet, an energy conversion efficiency is increased by acceleration of scattering and multiple reflection of incident light rays projected into a non-single crystalline semiconductor layer.Type: GrantFiled: September 4, 1997Date of Patent: November 16, 1999Assignees: Nisshin Steel Co., Ltd., Canon Kabushiki KaishaInventors: Hisashi Matsune, Yasushi Nishimura, Takuji Okiyama, Masafumi Sano