Cleaning Of Wafer As Interim Step Patents (Class 438/906)
  • Patent number: 11456360
    Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tetsuji Ueno, Ming-Hua Yu, Chan-Lon Yang
  • Patent number: 9040385
    Abstract: Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chau Chen, Chih-Hui Huang, Yeur-Luen Tu, Cheng-Ta Wu, Chia-Shiung Tsai, Xiao-Meng Chen
  • Patent number: 9023741
    Abstract: A method for surface treatment is disclosed which relates to the technical field of producing thin-film devices by printing and solves the problem that the treatment of a substrate surface in the prior art can hardly meet the requirement for printing. The method for surface treatment includes a step of subjecting a surface of a base plate having at least two kinds of substrate patterns formed thereon to a surface treatment for forming a self-assembled monomolecular layer for at least once and a surface treatment by ultraviolet-ozone cleaning, so as to make the difference between the surface energies of the substrate patterns larger or smaller. The method for surface treatment of the invention is suitable for the surface treatment of the substrate surface during producing thin-film devices by printing.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: May 5, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xianghua Wang, Xianfeng Xiong, Longzhen Qiu, Ze Liu
  • Patent number: 8920571
    Abstract: The present invention includes methods and materials for cleaning materials, particles, or chemicals from a substrate with a brush or pad. The method comprising: engaging a surface of a rotating wafer with an outer circumferential surface of a rotating cylindrical foam roller, the cylindrical foam roller having a plurality of circumferentially and outwardly extending spaced apart nodules extending from the outer surface, each nodule defining a height extending from the outer surface of the cylindrical foam roller to a substrate engagement surface of the nodule, the substrate engagement surface of one or more of the nodules having a rounded configuration; and positioning the cylindrical foam roller on the substrate such that the one or more nodules are positioned to have only the rounded substrate engagement surface contact the substrate such that no linear surface of the one or more nodules contacts the substrate.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Entegris, Inc.
    Inventor: Briant Enoch Benson
  • Patent number: 8765571
    Abstract: A method and system are provided for manufacturing a base substrate that is used in manufacturing a semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Frederic Allibert
  • Patent number: 8758521
    Abstract: A semiconductor substrate cleaning method includes cleaning a semiconductor substrate formed with a line-and-space pattern, rinsing the substrate, supplying the rinse water to rinse the substrate, and drying the substrate. The rinsing includes supplying deionized water and hydrochloric acid into a mixing section to mix the deionized water and the hydrochloric acid into a mixture, heating the mixture in the mixing section by a heater, detecting a pH value and a temperature of the mixture by a pH sensor and a temperature sensor respectively, adjusting an amount of hydrochloric acid supplied into the mixing section so that the rinse water has a predetermined pH value indicative of acidity, and energizing or de-energizing the heater so that the temperature of the mixture detected by the temperature sensor reaches a predetermined temperature, thereby producing the rinse water which has a temperature of not less than 70° C. and is acidic.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Ogawa, Hajime Onoda, Hiroshi Kawamoto
  • Patent number: 8703605
    Abstract: A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 22, 2014
    Inventor: Byung Chun Yang
  • Patent number: 8696921
    Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Byung-Lyul Park, Jong-Myeong Lee, Zung-Sun Choi, Hye-Kyung Jung
  • Patent number: 8664012
    Abstract: A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Richard H. Gaylord, Blaze J. Messer, Kaushik A. Kumar
  • Patent number: 8664092
    Abstract: A silicon wafer after being subjected to mirror polishing but before being subjected to form an epitaxial layer thereon is subjected to an ozone gas treatment that oxidizes a surface of the silicon wafer by use of ozone gas, a hydrofluoric acid gas treatment that dissolves and removes the oxidized surface of the silicon wafer by use of hydrofluoric acid gas, and a washing treatment that removes foreign substances remaining on the surface of the silicon wafer, whereby PIDs (Polishing Induced Defects) generated by the mirror polishing are forcedly oxidized, dissolved and removed. By performing epitaxial treatment thereafter, PID-induced convex defects can be prevented from generating on the surface of the epitaxial wafer.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: March 4, 2014
    Assignee: Sumco Corporation
    Inventor: Tomonori Kawasaki
  • Patent number: 8652943
    Abstract: A method of processing a substrate is provided. The method includes providing a substrate, performing a device forming process on the substrate, and cleaning the substrate. The step of cleaning the substrate includes cleaning the substrate with an atomic spray and rinsing the substrate with deionized water.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 18, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Tsung-Hsun Tsai
  • Patent number: 8598023
    Abstract: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 3, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomokazu Kawamoto
  • Patent number: 8591809
    Abstract: A substrate transfer container comprises a housing including a plurality of substrate slots positioned within a gas chamber having an interior environment. Each substrate slot accommodates a substrate undergoing a substrate manufacturing process, the interior environment of the gas chamber being selectively sealed from an exterior environment. A detection unit at the housing is constructed and arranged to detect an environmental property of the interior environment of the gas chamber, and to generate a detection signal in response. A signal transmission module at the housing is configured to wirelessly transmit a detection signal received from the detection unit.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Koog Ra, Tae-Sik Yun, Kunhyung Lee, Hyunjoon Kim, Hyeogki Kim, KiDoo Kim
  • Patent number: 8575039
    Abstract: A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Hiroyuki Hashimoto
  • Patent number: 8545640
    Abstract: In a substrate processing method according to the present invention, a cleaning liquid nozzle supplies a rinsing liquid to a central portion of a substrate and thereafter moves from a position corresponding to the central portion of the substrate to a position corresponding to a peripheral, edge portion thereof while supplying the rinsing liquid before stopping at the position corresponding to the peripheral edge portion. Next, a drying liquid nozzle moves from the position corresponding to the peripheral edge portion to the position corresponding to the central portion while supplying a drying liquid. Then, the drying liquid nozzle is kept stationary at the position corresponding to the central portion for a predetermined period of time while supplying the drying liquid. Thereafter, a gas nozzle moves from the position corresponding to the central portion to the position corresponding to the peripheral edge portion while supplying an inert gas.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 1, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Teruomi Minami, Naoyuki Okamura, Yosuke Kawabuchi
  • Patent number: 8529707
    Abstract: Provided is a liquid processing apparatus in which a target substrate is horizontally held on a substrate holding unit and rotated around a vertical shaft, and the chemicals are supplied from a chemical supplying unit to the bottom surface of the target substrate that is rotating. In particular, the liquid processing apparatus performs a first step in which the chemicals are supplied to the target substrate while rotating the target substrate at a first rotation speed, a second step in which the supply of the chemicals is halted and the chemicals are thrown off by rotating the target substrate at a second rotation speed higher than the first rotation speed, and a third step in which the rinse liquid is supplied to the target substrate while rotating the target substrate at a third rotation speed equal to or lower than the first rotation speed.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 10, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hiromitsu Namba
  • Patent number: 8529783
    Abstract: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: September 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Ming Chen, Chun-Li Chou, Chao-Cheng Chen, Hun-Jan Tao
  • Patent number: 8501636
    Abstract: A method for fabricating silicon dioxide layer is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Next, the semiconductor substrate is cleaned with a solution containing hydrogen peroxide to form a chemical oxide layer on the semiconductor substrate. Then, the chemical oxide layer is heated in no oxygen atmosphere, such that the chemical oxide layer forms a compact layer. Then, the semiconductor substrate is heated in oxygen atmosphere to form a silicon dioxide layer between the semiconductor substrate and the compact layer.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Ying-Wei Yen, Kun-Yuan Lo, Chih-Wei Yang
  • Patent number: 8500913
    Abstract: Some embodiments include utilization of both plasma and aerosol to treat substrate surfaces. The plasma and aerosol may be utilized simultaneously, or sequentially. In some embodiments, the plasma forms a plasma sheath over the substrate surfaces, with the plasma sheath having an electric field gradient therein. The aerosol comprises liquid particles charged to a polarity, and such polarity is transferred to contaminants on the substrate surfaces through interaction with the aerosol. The polarity may be used to assist in dislodging the contaminants from the substrate surfaces. The electric field of the plasma sheath may then sweep the contaminants away from the substrate surfaces. In some embodiments, multiple different aerosols are formed to remove multiple different types of materials from substrate surfaces. Some embodiments include apparatuses configured for treating substrate surfaces with both plasma and aerosol.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Paul A. Morgan, Gurtej S. Sandhu
  • Patent number: 8486201
    Abstract: Disclosed is a method for drying a plate-like article; the method including rinsing with an aqueous rinsing liquid with subsequent rinsing with an organic solvent, wherein the organic solvent has a water content of below 20 mass-% wherein the organic solvent is supplied at a solvent temperature, which is at least 30° C. and not higher than 60° C.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 16, 2013
    Assignee: Lam Research AG
    Inventor: Aurelia Plihon
  • Patent number: 8475666
    Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 2, 2013
    Assignee: Honeywell International Inc.
    Inventors: Teresa A. Ramos, Robert R. Roth, Anil S. Bhanap, Paul G. Apen, Denis H. Endisch, Brian J. Daniels, Ananth Naman, Nancy Iwamoto, Roger Y. Leung
  • Patent number: 8470095
    Abstract: A process for surface preparation of a substrate (2), which comprises introducing or running a substrate (2) into a reaction chamber (6, 106). A dielectric barrier (14, 114) is placed between electrodes (1, 10, 110). A high-frequency electrical voltage is generated, to generate filamentary plasma (12, 112). Molecules (8, 108) are introduced into the reaction chamber (6, 106). Upon contact with the plasma, they generate active species typical of reacting with the surface of the substrate. An adjustable inductor (L) placed in parallel with the inductor of the installation is employed to reduce the phase shift between the voltage and the current generated and to increase the time during which the current flows in the plasma (12, 112).
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 25, 2013
    Assignee: AGC Glass Europe
    Inventors: Eric Tixhon, Joseph Leclercq, Eric Michel
  • Patent number: 8466071
    Abstract: An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot is spun, and a front surface of the wafer is etched with an etching solution supplied thereto. In the method, a plurality of supply nozzles are disposed above and opposite to the front surface of the wafer at different portions in the radial direction of the wafer, respectively; and then one or more conditions selected from the group consisting of temperatures, kinds, and supply flow rates of etching solutions from the plurality of supply nozzles are changed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 18, 2013
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Patent number: 8455372
    Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 4, 2013
    Assignee: Fudan University
    Inventors: Qingqing Sun, Runchen Fang, Wen Yang, Pengfei Wang, Wei Zhang
  • Patent number: 8440573
    Abstract: A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern collapse.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: May 14, 2013
    Assignee: Lam Research Corporation
    Inventors: Katrina Mikhaylichenko, Denis Syomin, Qian Fu, Glenn W. Gale, Shenjian Liu, Mark H. Wilcoxson
  • Patent number: 8419964
    Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: April 16, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Kousik Ganesan, Shanthinath Ghongadi, Tariq Majid, Aaron Labrie, Steven T. Mayer
  • Patent number: 8404052
    Abstract: A method for cleaning the surface of a silicon substrate, covered by a layer of silicon oxide includes: a) exposing the surface for 60 to 900 seconds to a radiofrequency plasma, generated from a fluorinated gas, to strip the silicon oxide layer and induce the adsorption of fluorinated elements on the substrate surface, the power density generated using the plasma being 10 mW/cm2 to 350 mW/cm2, the fluorinated gas pressure being 10 mTorrs to 200 mTorrs, and the substrate temperature being lower than or equal to 300° C.; and b) exposing the surface including the fluorinated elements for 5 to 120 seconds to a hydrogen radiofrequency plasma, to remove the fluorinated elements from the substrate surface, the power density generated using the plasma being 10 mW/cm2 to 350 mW/cm2, the hydrogen pressure being 10 mTorrs to 1 Torr, and the substrate temperature being lower than or equal to 300° C.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 26, 2013
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, Mario Moreno
  • Patent number: 8387674
    Abstract: The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Comany, Ltd.
    Inventors: Chen-Hua Yu, Jui-Pin Hung, Weng-Jin Wu, Jean Wang, Wen-Chih Chiou
  • Patent number: 8377219
    Abstract: A method for cleaning a semiconductor wafer composed of silicon directly after a process of chemical mechanical polishing of the semiconductor wafer includes transferring the semiconductor wafer from a polishing plate to a first cleaning module and spraying both side surfaces of the semiconductor wafer with water at a pressure no greater than 1000 Pa at least once while transferring the semiconductor wafer. The semiconductor wafer is then cleaned between rotating rollers with water. The side surfaces of the semiconductor wafer are sprayed with an aqueous solution containing hydrogen fluoride and a surfactant at a pressure no greater than 70,000 Pa. Subsequently, the side surfaces are sprayed with water at a pressure no greater than 20,000 Pa. The wafer is then dipped into an aqueous alkaline cleaning solution, and then cleaned between rotating rollers with a supply of water. The semiconductor wafer is then sprayed with water and dried.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 19, 2013
    Assignee: Siltronic AG
    Inventor: Reinhold Lanz
  • Patent number: 8367545
    Abstract: A monitor wafer for use in monitoring a preclean process and method of making same are described. One embodiment is a monitor wafer comprising a silicon base layer; a capping layer disposed on the silicon base layer; and a barrier layer disposed on the USG layer. The monitor wafer further comprises a copper (“Cu”) seed layer disposed on the barrier layer; and a thick Cu layer disposed on the Cu seed layer.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Liang Sung, Cheng-Hui Weng
  • Patent number: 8357615
    Abstract: The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric con
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 22, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Yuki Chiba, Eiichi Nishimura, Ryuichi Asako
  • Patent number: 8303723
    Abstract: In a liquid processing apparatus configured to remove, from a substrate including a first film and a second film formed above the first film, the first film and the second film, a first chemical-liquid supply part supplies, to a substrate W, a first liquid for dissolving the first film, a second chemical-liquid supply part supplies a second chemical liquid for weakening the second film, and a fluid supply part serving also as an impact giving part gives a physical impact to the second film so as to break the second film and supplies a fluid for washing away debris of the broken second film. A control device controls the respective parts such that, after the second liquid has been supplied and then the fluid has been supplied from the fluid supply part, the first chemical liquid is supplied.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: November 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Teruomi Minami, Fumihiro Kamimura, Kazuki Kosai, Takashi Yabuta, Kenji Yokomizo, Shogo Mizota
  • Patent number: 8293646
    Abstract: A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 23, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takashi Ozaki, Osamu Kasahara, Takaaki Noda, Kiyohiko Maeda, Atsushi Moriya, Minoru Sakamoto
  • Patent number: 8278186
    Abstract: The present invention relates to a wafer cleaning and a wafer bonding method using the same that can improve a yield of cleaning process and bonding property in bonding the cleaned wafer by cleaning the wafer using atmospheric pressure plasma and cleaning solution. The wafer cleaning method includes the steps of providing a process chamber with a wafer whose bonding surface faces upward, cleaning and surface-treating the bonding surface of the wafer by supplying atmospheric pressure plasma and a cleaning solution to the bonding surface of the wafer, and withdrawing out the wafer from the process chamber.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 2, 2012
    Assignee: Ltrin Co., Ltd.
    Inventors: Yong Won Cha, Dong Chul Kim
  • Patent number: 8268735
    Abstract: Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: September 18, 2012
    Assignees: Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Hitoshi Morinaga
  • Patent number: 8268085
    Abstract: A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Shun Wu Lin, Hui Ouyang
  • Patent number: 8263468
    Abstract: A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.
    Type: Grant
    Filed: April 24, 2010
    Date of Patent: September 11, 2012
    Assignee: International Busienss Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 8236109
    Abstract: A method for cleaning a component in a substrate processing apparatus including a processing chamber, foreign materials being attached to the component, at least a part of the component being exposed inside the processing chamber, and the substrate processing apparatus being adapted to load and unload a foreign material adsorbing member into and from the processing chamber. The method includes loading the foreign material adsorbing member into the processing chamber; generating a plasma nearer the component than the foreign material adsorbing member; extinguishing the plasma; and unloading the foreign material adsorbing member from the processing chamber, wherein the generation and the extinguishment of the plasma are repeated alternately and the foreign material adsorbing member has a positive potential at least during the extinguishment of the plasma.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: August 7, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Moriya, Akitaka Shimizu
  • Patent number: 8236485
    Abstract: Disclosed herein is a composition and method for semiconductor processing. In one embodiment, a wet-cleaning composition for removal of photoresist is provided. The composition comprises a strong base; an oxidant; and a polar solvent. In another embodiment, a method for removing photoresist is provided. The method comprises the steps of applying a wet-cleaning composition comprising about 0.1 to about 30 weight percent strong base; about one to about 30 weight percent oxidant; about 20 to about 95 weight percent polar solvent; and removing the photoresist.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: August 7, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventors: David W. Minsek, Melissa K. Murphy, David Daniel Bernhard, Thomas H. Baum
  • Patent number: 8232123
    Abstract: An organic light emitting device and a manufacturing method thereof, including a first signal line and a second signal line intersecting each other on an insulating substrate, a switching thin film transistor connected to the first signal line and the second signal line, a driving thin film transistor connected to the switching thin film transistor, and a light emitting diode (“LD”) connected to the driving thin film transistor. The driving thin film transistor includes a driving control electrode and a driving semiconductor overlapping the driving control electrode, crystallized silicon having a doped region and a non-doped region, a driving gate insulating layer disposed between the driving control electrode and the driving semiconductor, and a driving input electrode and a driving output electrode opposite to each other on the driving semiconductor, wherein the interface between the driving gate insulating layer and the driving semiconductor includes nitrogen gas.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Sik Cho, Byoung-Seong Jeong, Joon-Hoo Choi, Jong-Moo Huh
  • Patent number: 8207060
    Abstract: The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: June 26, 2012
    Inventor: Byung Chun Yang
  • Patent number: 8187389
    Abstract: A resist removing device 1 functions to remove a resist from a substrate while preventing occurrence of popping phenomenon and at the same time attains reduction in cost of energy for the resist removing and has a simplified constitution. The resist removing device 1 is equipped with a chamber 2 for containing therein a substrate 16 (for example, a substrate having a high-doze ion implanted resist), and with a pressure below the atmospheric pressure, the chamber 2 is fed with ozone gas, unsaturated hydrocarbons and water vapor. The ozone gas may be an ultra-high concentrated ozone gas that is produced by subjecting an ozone containing gas to a liquefaction-separation with the aid of a vapor pressure difference and then vaporizing the liquefied ozone. For cleaning the substrate 16 thus treated, it is preferable to use ultra-pure water. The chamber 2 is equipped with a susceptor 15 for holding the substrate 16. The susceptor 15 is heated to a temperature of 100° C. or below.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: May 29, 2012
    Assignee: Meidensha Corporation
    Inventor: Toshinori Miura
  • Patent number: 8183156
    Abstract: Disclosed is a method of structuring a material surface by dry etching, so that a passivation layer soluble in a solvent forms by the dry etching on parts of the structured material surface, sealing the passivation layer with a substance soluble in the solvent, and removing the sealed passivation layer and the substance by means of the solvent.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Maria Heidenblut, Raimund Foerg, Walter Preis
  • Patent number: 8183157
    Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 22, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Naraji B Rana, Nishant Sinha, Prashant Raghu, Jim J. Hofmann, Neil Joseph Greeley
  • Patent number: 8173934
    Abstract: Disclosed is a dry cleaning apparatus and method for removing contaminants on a surface of a workpiece. The disclosed dry cleaning apparatus comprises a laser cleaning unit having a laser beam generator for generating a laser induced shock wave in the atmosphere, the laser cleaning unit being suitable for removing an inorganic contaminant on the surface of the workpiece using the generated laser induced shock wave; and a flash cleaning unit having a flash generator for generating a flash having pulse wave, the flash cleaning unit being suitable for removing an organic contaminant on the surface of the workpiece using the generated flash.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 8, 2012
    Assignee: IMT Co. Ltd
    Inventors: Jong Myoung Lee, Saeng-Ki Lim, Sung-Ho Cho
  • Patent number: 8153518
    Abstract: In a method for fabricating a metal interconnection of a semiconductor device, a lower interconnection and a lower insulation layer are formed over a semiconductor substrate. An etch stop layer is formed over the lower insulation layer. An upper insulation layer is formed over the etch stop layer. A first via hole is formed to expose the etch stop layer corresponding to the lower interconnection. A second via hole exposing the lower interconnection is formed by a primary etching process that selectively removes the etch stop layer exposed by the first via hole. A chemical cleaning process is performed on the second via hole, wherein polymer is formed over the surface of the lower interconnection during the chemical cleaning process. The polymer is removed from the second via hole by a secondary etching process using vaporized gas.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: April 10, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chung-Kyung Jung
  • Patent number: 8153524
    Abstract: During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed to provide superior surface conditions of the sensitive dielectric material and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: April 10, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Oliver Aubel, Joerg Hohage, Frank Feustel, Axel Preusse
  • Patent number: 8153527
    Abstract: A method for fabricating a semiconductor device is provided. The method comprising forming a first layer over a substrate and a second layer over the first layer. A patterned masking layer is subsequently provided over the second layer and a patterned second layer with outwardly tapered sidewalls is formed by isotropically etching exposed portions of the second layer. A patterned first layer is the formed by etching the first layer in accordance with the patterned second layer.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: April 10, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Soon Yoong Loh, Carol Goh, Kin Wai Tang, Kim Foong Kong
  • Patent number: 8129275
    Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
  • Patent number: 8101025
    Abstract: A method for controlling corrosion of a substrate is provided herein. In one embodiment, a method for controlling corrosion of a substrate includes the steps of providing a substrate having a patterned photoresist layer with a metallic residue disposed thereon; exposing the substrate to a hydrogen-based plasma to remove the metallic residue; and removing the photoresist. The metallic residue may comprise residue from etching at least one of aluminum or copper. The metallic residue may further comprise a halogen compound from etching a metal-containing layer with a halogen-based process gas. The hydrogen-based plasma may comprise hydrogen (H2) and may further comprise at least one of nitrogen (N2) and water (H2O) vapor. The hydrogen-based plasma may further comprise an inert gas, such as argon (Ar).
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: January 24, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Eu Jin Lim, Chungdee Pong, Changhun Lee, Mark Kawaguchi, Guowen Ding