Cleaning Of Wafer As Interim Step Patents (Class 438/906)
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Patent number: 8097538Abstract: A metal member layer on a silicon member layer is patterned. A sidewall film is formed on a surface of the metal member layer. The silicon member layer is patterned to form a structure including the silicon member layer and the metal member layer, the surface of which is covered with the sidewall film. After the surface of the structure is cleaned, a water-repellent protective film is formed on the surface of the structure before the surface of the structure is dried.Type: GrantFiled: March 2, 2010Date of Patent: January 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuhiko Koide, Hisashi Okuchi, Hidekazu Hayashi, Hiroshi Tomita
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Patent number: 8093137Abstract: A device layer is formed on at least the upper surface of a prime wafer by an epitaxial growth method. Then, a protective film is formed to cover at least the device layer. The lower surface of the prime wafer is ground to have a flat lower surface.Type: GrantFiled: March 13, 2009Date of Patent: January 10, 2012Assignee: Lapis Semiconductor Co., Ltd.Inventor: Masatsugu Desaki
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Patent number: 8092760Abstract: Provided is a scanning arm which moves to collect pollutants on the surface of a semiconductor wafer, for use in a semiconductor wafer pollutant measurement apparatus, and a scanning device using the same. The scanning arm includes: an X-axis portion; a Z-axis portion which is perpendicularly installed with the X-axis portion so as to move forward and backward along the X-axis portion; and a Y-axis portion which is perpendicularly installed with the Z-axis portion so as to move up and down with respect to the Z-axis portion.Type: GrantFiled: September 8, 2008Date of Patent: January 10, 2012Assignee: Korea Techno Co., LtdInventors: Ho Jin Kim, Hyoung Bae Kim
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Patent number: 8083862Abstract: A method and system for measuring contamination, such as metal contamination, on a substrate. A dry cleaning system is utilized for non-destructive, occasional removal of contamination, such as metal containing contamination, on a substrate, whereby a monitoring system coupled to the exhaust of the dry cleaning system is employed to determine the relative level of contamination on the substrate prior to dry cleaning.Type: GrantFiled: March 9, 2007Date of Patent: December 27, 2011Assignee: Tokyo Electron LimitedInventor: Ian J. Brown
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Patent number: 8034190Abstract: A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, and an interface block. An exposure device is arranged adjacent to the interface block. The interface block comprises washing processing units and an interface transport mechanism. Before a substrate is subjected to exposure processing by the exposure device, the substrate is transported to a washing processing unit by the interface transport mechanism. The substrate is washed and dried by the washing processing unit.Type: GrantFiled: March 8, 2010Date of Patent: October 11, 2011Assignee: Sokudo Co., Ltd.Inventors: Shuichi Yasuda, Masashi Kanaoka, Koji Kaneyama, Tadashi Miyagi, Kasuhito Shigemori, Toru Asano, Akihiro Hisai, Hiroshi Kobayashi, Tsuyoshi Okumura
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Patent number: 8021565Abstract: A surface treatment method includes: removing a fluorocarbon-containing reaction product from a surface of a workpiece by oxygen gas plasma processing. The workpiece includes a plurality of layers. The fluorocarbon-containing reaction product is deposited by successively etching the layers of the workpiece. The method further includes after removing the reaction product, removing an oxide-containing reaction product from the surface of the workpiece using hydrogen fluoride gas.Type: GrantFiled: March 24, 2008Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Aoki, Naoya Hayamizu, Kei Hattori, Yukihiro Oka, Hidemi Kanetaka, Makoto Hasegawa
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Patent number: 8007594Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.Type: GrantFiled: July 12, 2010Date of Patent: August 30, 2011Assignee: Hynix Semiconductor Inc.Inventors: Young Bang Lee, Kwang Kee Chae, Ok Min Moon
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Patent number: 7994063Abstract: Disclosed is a method for cleaning a semiconductor substrate that can solve a problem of a conventional cleaning method which should include at least five steps for cleaning a substrate such as a semiconductor substrate. The method for cleaning a semiconductor substrate comprises a first step of cleaning a substrate with ultrapure water containing ozone, a second step of cleaning the substrate with ultrapure water containing a surfactant, and a third step of removing an organic compound derived from the surfactant, with a cleaning liquid containing ultrapure water and 2-propanol. After the third step, plasma of noble gas such as krypton is applied to the substrate to further remove the organic compound derived from the surfactant.Type: GrantFiled: April 10, 2009Date of Patent: August 9, 2011Assignees: National University Corporation Tohoku University, Stella Chemifa CorporationInventors: Tadahiro Ohmi, Akinobu Teramoto, Rui Hasebe, Masayuki Miyashita
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Patent number: 7994066Abstract: A method is disclosed for the cleaning of a Si surface at low temperatures. Oxide on the Si surface is brought into contact with Ge, which then sublimates off the surface. The Ge contamination remaining after the oxide removal is cleared away by an exposure to an alkali halide. The disclosed cleaning method may by used in semiconductor circuit fabrication for preparing surfaces ahead of epitaxial growth.Type: GrantFiled: October 13, 2007Date of Patent: August 9, 2011Assignee: Luxtera, Inc.Inventors: Giovanni Capellini, Gianlorenzo Masini, Lawrence C. Gunn, III, Jeremy Witzens, Joseph W. White
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Patent number: 7977244Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.Type: GrantFiled: December 18, 2006Date of Patent: July 12, 2011Assignee: United Microelectronics Corp.Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Patent number: 7977241Abstract: A method of fabricating highly reliable tungsten interconnects takes into consideration the effects of charging that can occur within a CMP apparatus due to unrestricted DI water flow, limited only by house supply. Such effects are addressed with the use of a variable pressure input constant flow output in-line controller to the DI water line coupled to the head cleaning loading and unloading module of the CMP apparatus.Type: GrantFiled: December 20, 2007Date of Patent: July 12, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Edward R. Gutierrez, William J. Bellamak, Daniel Davison, Gregory D. Hale, James F. Vannell
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Patent number: 7964495Abstract: A method of manufacturing a CMOS image sensor manufacturing includes forming a plurality of metal pads over a semiconductor substrate; electrically connecting the metal pads to lower conductive film patterns of multi-layer metal wires using metal contacts; depositing an insulation film over the metal pads; patterning the insulation film to expose at least a portion of the upper surface of the metal pads; and removing impurities from an uppermost surface of the metal pads.Type: GrantFiled: October 9, 2007Date of Patent: June 21, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Han-Choon Lee
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Patent number: 7955440Abstract: After a water film is formed on a wafer front surface in a chamber, the water film is supplied sequentially with an oxidizing component of an oxidation gas, an organic acid component of an organic acid mist, an HF component of an HF gas, the organic acid mist, and the oxidizing component of the oxidation gas. As a result, the HF component and the organic acid component provide cleaning effect on the wafer surface, and a concentration of the cleaning components in the water film within a wafer surface can be even.Type: GrantFiled: November 21, 2008Date of Patent: June 7, 2011Assignee: Sumco CorporationInventors: Shigeru Okuuchi, Kazushige Takaishi
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Patent number: 7939373Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.Type: GrantFiled: June 20, 2008Date of Patent: May 10, 2011Assignee: Sanyo Electric Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Takeshi Nakamura
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Patent number: 7923424Abstract: A method of cleaning a substrate includes contacting a surface of a semiconductor substrate with a composition comprising a superacid. The semiconductor substrate may be a wafer.Type: GrantFiled: February 10, 2006Date of Patent: April 12, 2011Assignee: Advanced Process Technologies, LLCInventor: Robert J. Small
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Patent number: 7879724Abstract: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.Type: GrantFiled: March 20, 2008Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoki Idani
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Patent number: 7875486Abstract: Embodiments of the present invention generally provide an apparatus and method for forming an improved thin film single or multi-junction solar cell in a substrate processing device. One embodiment provides a system that contains at least one processing chamber that is adapted to deposit one or more layers that form a portion of a solar cell device. In one embodiment, a method is employed to reduce the contamination of a substrate processed in the processing chamber by performing a cleaning process on the inner surfaces of the processing chamber prior to depositing the one or more layers on a substrate. The cleaning process may include depositing a layer, such as a seasoning layer or passivation layer, that tends to trap contaminants found in the processing chamber. Other embodiments of the invention may provide scheduling and/or positioning the cleaning processing steps at desirable times within a substrate processing sequence to improve the overall system substrate throughput.Type: GrantFiled: July 9, 2008Date of Patent: January 25, 2011Assignee: Applied Materials, Inc.Inventors: Soo Young Choi, Liwei Li
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Patent number: 7867789Abstract: Method for recovering treated metal silicide surfaces or layers are provided. In at least one embodiment, a substrate having an at least partially oxidized metal silicide surface disposed thereon is cleaned to remove the oxidized regions to provide an altered metal silicide surface. The altered metal silicide surface is then exposed to one or more silicon-containing compounds at conditions sufficient to recover the metal silicide surface.Type: GrantFiled: June 23, 2009Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Xinliang Lu, Chien-Teh Kao, Chiukin Steve Lai, Mei Chang
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Patent number: 7857982Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.Type: GrantFiled: July 19, 2005Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock
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Patent number: 7846845Abstract: A method and system for removing volatile residues from a substrate are provided. In one embodiment, the volatile residues removal process is performed en-routed in the system while performing a halogen treatment process on the substrate. The volatile residues removal process is performed in the system other than the halogen treatment processing chamber and a FOUP. In one embodiment, a method for volatile residues from a substrate includes providing a processing system having a vacuum tight platform, processing a substrate in a processing chamber of the platform with a chemistry comprising halogen, and treating the processed substrate in the platform to release volatile residues from the treated substrate.Type: GrantFiled: February 16, 2007Date of Patent: December 7, 2010Assignee: Applied Materials, Inc.Inventors: Kenneth J. Bahng, Matthew Fenton Davis, Thorsten Lill, Steven H. Kim
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Patent number: 7838425Abstract: A method of treating the surface of a semiconductor substrate has cleaning the semiconductor substrate having a pattern formed thereon by using a chemical solution, removing the chemical solution by using pure water, forming a water repellent protective film on the surface of the semiconductor substrate, rinsing the semiconductor substrate by using pure water, and drying the semiconductor substrate.Type: GrantFiled: October 24, 2008Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Tomita, Hiroyasu Iimori, Hisashi Okuchi, Tatsuhiko Koide, Linan Ji
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Patent number: 7816272Abstract: A process of cleaning a semiconductor manufacturing system, and a method of manufacturing a semiconductor device. The cleaning process includes, for example, positioning a ceramic cover on the electrostatic chuck in tight contact with the chuck, and feeding a fluoride-based cleaning gas into a chamber. After the cleaning process, a process of forming a semiconductor film (deposition process) is performed. It is possible to prevent fluorine degasification from a substrate-supporting electrode (electrostatic chuck) during the deposition process. A semiconductor film can be formed without causing a temperature drop near the substrate. This prevents irregular film thickness, defective etching, film flaking, etc.Type: GrantFiled: March 31, 2009Date of Patent: October 19, 2010Assignee: Oki Electric Industry Co., Ltd.Inventor: Hiroomi Tsutae
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Patent number: 7807585Abstract: A dielectric insulating film including HfO or the like is formed by: cleaning a surface of a semiconductor substrate by exposing the substrate surface to a fluorine radical; performing hydrogen termination processing with a fluorine radical or a hydride (SiH4 or the like); sputtering Hf or the like; and then performing oxidation/nitridation. These steps are carried out without exposing the substrate to atmosphere, thereby making it possible to obtain a C-V curve with less hysteresis and realize a MOS-FET having favorable device characteristics.Type: GrantFiled: November 2, 2009Date of Patent: October 5, 2010Assignee: Canon Anelva CorporationInventors: Takuya Seino, Manabu Ikemoto, Hiroki Date
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Patent number: 7803721Abstract: A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the deposited-type insulating film and the coating-type insulating film and having a film density which is intermediate between the film density of the deposited-type insulating film and the film density of the coating-type insulating film.Type: GrantFiled: March 14, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Iwasawa
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Patent number: 7799700Abstract: A method for applying a resin film to the face of a semiconductor wafer, comprising: an assembly holding step of holding an assembly on the surface of chuck means, with the back of the assembly being opposed to the surface of the chuck means, the assembly including a frame having a mounting opening formed in a central portion of the frame, and a semiconductor wafer mounted in the mounting opening of the frame by sticking a mounting tape to the back of the frame and the back of the semiconductor wafer; a liquid droplet supply step of supplying liquid droplets of a solution having a resin dissolved therein onto the face of the semiconductor wafer in the assembly after the assembly holding step; and a spreading step of rotating the chuck means subsequently to the liquid droplet supply step, thereby spreading the liquid droplets throughout the face of the semiconductor wafer.Type: GrantFiled: September 5, 2006Date of Patent: September 21, 2010Assignee: Disco CorporationInventors: Kentaro Iizuka, Takashi Sampei, Nobuyasu Kitahara, Yohei Yamashita
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Patent number: 7790477Abstract: Contaminants from surfaces of temperature sensitive substrates, such as glass substrates are removed by exposing the surfaces to a hydrogen Surface-mixed diffusion flame for a predetermined duration of time. The predetermined duration of time being insufficient to heat up the surfaces substantially thereby causing damage to the temperature sensitive substrates.Type: GrantFiled: February 6, 2009Date of Patent: September 7, 2010Assignee: Agency For Science, Technology And ResearchInventors: David Tee Liang, Tuti Mariana Lim, Sau Ngen Chen
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Patent number: 7785957Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern.Type: GrantFiled: December 26, 2008Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Jinhan Choi, Randall W. Pak
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Patent number: 7781314Abstract: Affords a manufacturing method enabling nitride-based semiconductor devices containing epitaxial films excelling in flatness and crystallinity to be easily produced. Method of manufacturing nitride semiconductor devices that are formed onto a semiconductor substrate being a compound containing nitrogen, and a Group IIIA element for forming compounds with nitrogen, including steps of: heating the semiconductor substrate (1) to a film-deposition temperature; supplying to the substrate a film-deposition gas containing a source gas for the Group IIIA element and a nitrogen source gas; and epitaxially growing onto the semiconductor substrate a thin film (2) of a compound containing nitrogen and the Group IIIA element; and being furnished with a step, in advance of the epitaxial growth step, of heating the semiconductor substrate to a pretreating temperature less than the film-deposition temperature, to clean the surface of the semiconductor substrate.Type: GrantFiled: December 17, 2007Date of Patent: August 24, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Kyono, Masaki Ueno
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Patent number: 7767585Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.Type: GrantFiled: September 5, 2006Date of Patent: August 3, 2010Assignees: Sony Corporation, Mitsubishi Gas Chemical Company, Inc.Inventors: Koichiro Saga, Kenji Yamada, Tomoyuki Azuma, Yuji Murata
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Patent number: 7754609Abstract: The cleaning of silicon carbide materials on a large-scale is described. Certain silicon carbide materials in the form of wafer-lift pins, wafer-rings and/or wafer-showerheads are cleaned by using a combination of two of more of the following steps, comprising: high temperature oxidation, scrubbing, ultrasonic assisted etching in an aqueous acid solution, ultrasonication in deionized water, immersion in an aqueous acid solution, and high temperature baking. The silicon carbide materials may either be sintered or formed by chemical vapor deposition.Type: GrantFiled: October 28, 2003Date of Patent: July 13, 2010Assignee: Applied Materials, Inc.Inventor: Samantha S. H. Tan
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Patent number: 7755064Abstract: A resist pattern processing apparatus comprises a stage for mounting a substrate having a patterned photoresist arranged on a surface thereof, a UV-emitting part for emitting UV rays to the stage, and an annular member for surrounding the whole periphery of the substrate. This allows the annular member to restrain ozone supplied near a mounting surface for the substrate on the stage from diffusing to the periphery of the stage, whereby the ozone concentration becomes even in the surface of the substrate mounted on the stage.Type: GrantFiled: March 7, 2007Date of Patent: July 13, 2010Assignee: TDK CorporationInventors: Hitoshi Hatate, Akifumi Kamijima
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Patent number: 7744769Abstract: The invention relates to a gas for removing deposits by a gas-solid reaction. This gas includes a hypofluorite that is defined as being a compound having at least one OF group in the molecule. Various deposits can be removed by the gas, and the gas can easily be made unharmful on the global environment after the removal of the deposits, due to the use of a hypofluorite. The gas may be a cleaning gas for cleaning, for example, the inside of an apparatus for producing semiconductor devices. This cleaning gas comprises 1-100 volume % of the hypofluorite. Alternatively, the gas of the invention may be an etching gas for removing an unwanted portion of a film deposited on a substrate. The unwanted portion can be removed by this etching gas as precisely as originally designed, due to the use of a hypofluorite. The invention further relates to a method for removing a deposit by the gas.Type: GrantFiled: October 6, 2006Date of Patent: June 29, 2010Assignee: Central Glass Company, LimitedInventors: Isamu Mouri, Tetsuya Tamura, Mitsuya Ohashi
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Patent number: 7740768Abstract: A method and apparatus for cleaning a wafer. The wafer is heated and moved to a processing station within the apparatus that has a platen either permanently in a platen down position or is transferable from a platen up position to the platen down position. The wafer is positioned over the platen so as not to contact the platen and provide a gap between the platen and wafer. The gap may be generated by positioning the platen in a platen down position. A plasma flows into the gap to enable the simultaneous removal of material from the wafer front side, backside and edges. The apparatus may include a single processing station having the gap residing therein, or the apparatus may include a plurality of processing stations, each capable of forming the gap therein for simultaneously removing additional material from the wafer front side, backside and edges.Type: GrantFiled: October 12, 2006Date of Patent: June 22, 2010Assignee: Novellus Systems, Inc.Inventors: Haruhiro H Goto, David Cheung
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Patent number: 7737005Abstract: A cleaning process is performed on the surface of a nickel silicide film serving as an underlayer. Then, a Ti film is formed to have a film thickness of not less than 2 nm but less than 10 nm by CVD using a Ti compound gas. Then, the Ti film is nitrided. Then, a TiN film is formed on the Ti film thus nitrided, by CVD using a Ti compound gas and a gas containing N and H.Type: GrantFiled: April 8, 2005Date of Patent: June 15, 2010Assignee: Tokyo Electron LimitedInventors: Kunihiro Tada, Kensaku Narushima, Satoshi Wakabayashi
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Patent number: 7732284Abstract: A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.Type: GrantFiled: December 26, 2008Date of Patent: June 8, 2010Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Jinhan Choi, Deborah J. Riley
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Patent number: 7727812Abstract: Provided is a singulation method of a semiconductor device that can perform a sawing process while protecting a pad. In the singulation method for forming a semiconductor device including a scribe lane region and a chip region, pads are formed in the chip region. Photoresist patterns exposing the scribe lane region and covering the pads are formed, and a substrate in the scribe lane region is cut and a washing solution is sprayed on the scribe lane region. According to the method, wafers can be stably separated from each other while pads of a semiconductor device are protected, so that stabilization in the fabrication process can be realized and pad corrosion caused by DI water is prevented during a sawing process. Accordingly, a defective device is minimized and reliability of a device can improve.Type: GrantFiled: December 19, 2007Date of Patent: June 1, 2010Assignee: Dongbu Hitek Co., Ltd.Inventor: Meng An Jung
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Patent number: 7700497Abstract: A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace disposed on a semiconductor substrate. Sidewalls of the via may be coated with a residue layer including a distinct oxide polymer component and a distinct metal polymer component. The two-step via cleaning process comprises subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component. The oxide polymer and metal polymer residues may also be removed during the fabrication of the via by removing them directly after their respective formations.Type: GrantFiled: December 22, 2008Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventor: Li Li
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Patent number: 7699998Abstract: A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NH4F, (NH4)HF2, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers such as shallow trench isolation fill oxide layers, or to layers having a non-homogeneous composition or density at different depths within the layers, such as spin-on-glass or spin-on-dielectric films.Type: GrantFiled: August 22, 2005Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventors: Janos Fucsko, Grady Waldo, Bob Carstensen, Satish Bedge
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Patent number: 7682517Abstract: A method of processing a substrate that enables the amount removed of a surface damaged layer to be controlled easily, and enable a decrease in wiring reliability to be prevented. A surface damaged layer having a reduced carbon concentration of a carbon-containing low dielectric constant insulating film on a substrate is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The surface damaged layer that has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.Type: GrantFiled: February 14, 2006Date of Patent: March 23, 2010Assignee: Tokyo Electron LimitedInventors: Eiichi Nishimura, Kenya Iwasaki
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Patent number: 7678699Abstract: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment is performed on the basis of an ammonium/nitrogen mixture in the absence of any plasma ambient.Type: GrantFiled: September 12, 2006Date of Patent: March 16, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Joerg Hohage, Matthias Lehr, Volker Kahlert
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Patent number: 7674725Abstract: A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapor, and is used in a cleaning apparatus employing a Marangoni dryer.Type: GrantFiled: May 25, 2005Date of Patent: March 9, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Janos Farkas, Sebastien Petitdidier
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Patent number: 7674695Abstract: An electromegasonic wafer cleaning system is disclosed that is extremely important, if not essential, in the fabrication of advanced microelectronic devices having a line width or feature size of from 0.05 to 0.10 micron. A unique synergistic combination is provided wherein piezoelectric transducer means are operated at a tolerable power level, such as from 1 to 2 watts per square centimeter, to minimize the risk of harm to the extremely delicate microcircuits and wherein the face of each wafer is negatively charged to a temperate voltage, such as from 5 to 20 volts, sufficient to cause effective removal of colloidal or sub 0.4-micron contaminant particles. This unique wafer cleaning system supersedes and replaces the standard megasonic-assisted RCA-type wet wafer cleaning systems which have never been able to eliminate or provide efficient purging of harmful sub 0.1-micron particles.Type: GrantFiled: October 25, 2004Date of Patent: March 9, 2010Inventor: Ted A. Loxley
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Patent number: 7659201Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.Type: GrantFiled: May 27, 2008Date of Patent: February 9, 2010Assignee: Renesas Technology Corp.Inventors: Naofumi Ohashi, Junji Noguchi, Toshinori Imai, Hizuru Yamaguchi, Nobuo Owada, Kenji Hinode, Yoshio Homma, Seiichi Kondo
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Patent number: 7655095Abstract: Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is transmitted in a homogenous manner throughout a carrier fluid. The mechanical energy provided in methods shown can also be used with delicate surface features.Type: GrantFiled: November 28, 2006Date of Patent: February 2, 2010Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7645344Abstract: Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is transmitted in a homogenous manner throughout a carrier fluid. The mechanical energy provided in methods shown also can also be used with delicate surface features.Type: GrantFiled: October 8, 2003Date of Patent: January 12, 2010Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 7645695Abstract: A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening, forming a metal wiring line protecting film in the opening, such that the metal wiring line protecting film covers the lower metal wiring layer, washing the opening to remove the metal wiring line protecting film, such that a top surface of the lower metal wiring layer is exposed, and drying the substrate.Type: GrantFiled: April 3, 2007Date of Patent: January 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-hwan Oh, Hong-seong Son, Sang-min Lee, Ju-hyuck Chung
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Patent number: 7635016Abstract: In a board cleaning method for dry cleaning of connection sites on resin-based boards, one or more gases selected from a group consisting of gas that contains a hydrogen element and gas that contains a fluorine element are supplied at least to the connection sites, plasma is generated from the supplied gas, and the boards are cleaned by radicals and ions that are produced by the generated plasma.Type: GrantFiled: October 7, 2002Date of Patent: December 22, 2009Assignee: Panasonic CorporationInventors: Naoki Suzuki, Youichi Nakamura, Kazuyuki Tomita
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Patent number: 7628866Abstract: A method of cleaning a wafer after an etching process is provided. A substrate having an etching stop layer, a dielectric layer, a patterned metal hard mask sequentially formed thereon is provided. Using the patterned metal hard mask, an opening is defined in the dielectric layer. The opening exposes a portion of the etching stop layer. A dry etching process is performed in the environment of helium to remove the etching stop layer exposed by the opening. A dry cleaning process is performed on the wafer surface using a mixture of nitrogen and hydrogen as the reactive gases. A wet cleaning process is performed on the wafer surface using a cleaning solution containing a trace amount of hydrofluoric acid.Type: GrantFiled: November 23, 2006Date of Patent: December 8, 2009Assignee: United Microelectronics Corp.Inventors: Miao-Chun Lin, Cheng-Ming Weng, Chun-Jen Huang
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Patent number: 7597816Abstract: A method of forming a semiconductor device is provided. A wafer with a dielectric layer disposed under a photoresist mask is placed in an etch chamber. The dielectric layer is etched. The wafer is raised. A cleaning gas is provided. A plasma is formed from the cleaning gas. A polymer that has formed on the bevel of the wafer is removed using the plasma from the cleaning gas. The wafer is removed from the etch chamber.Type: GrantFiled: September 3, 2004Date of Patent: October 6, 2009Assignee: Lam Research CorporationInventors: Jeremy Chang, Andreas Fischer, Peter Loewenhardt
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Patent number: 7582536Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.Type: GrantFiled: August 14, 2008Date of Patent: September 1, 2009Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, Mary Y. Chen, Steven S. Bui, David H. Chow, James Chingwei Li, Mehran Mokhtari, Marko Sokolich