Cleaning Of Wafer As Interim Step Patents (Class 438/906)
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Patent number: 7156927Abstract: A method is provided for treating an object. In this method, a treating chemical is introduced to a bath under conditions effective to at least partially envelop the object to be treated in eddy currents of the bath liquid, followed by introducing non-treating liquid into the bath under conditions effective to at least partially envelop the object to be treated in eddy currents of the bath liquid. An apparatus for carrying out this method is also provided. This method is particularly beneficial for objects used in precision manufacturing by treatment with solutions, such as semiconductor wafers or similar substrates.Type: GrantFiled: April 3, 2002Date of Patent: January 2, 2007Assignee: FSI International, Inc.Inventors: Kurt Karl Christenson, Nam Pyo Lee, Gary William Michalko, Christina Ann Rathman
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Patent number: 7151026Abstract: Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation, a semiconductor wafer backside is mechanically scrubbed to remove an undesired material prior to forming a final passivation layer over an oppositely facing semiconductor wafer frontside. In another implementation, the wafer backside is treated to remove the undesired material while treatment of the wafer frontside is restricted. In another implementation, the mechanical scrubbing of the wafer backside is conducted in connection with a polishing solution which is effective to facilitate removal of undesired material from the wafer backside. In a preferred implementation, dynamic random access memory storage capacitors are formed and the undesired material constitutes remnant polysilicon which adheres to the wafer backside during formation of a frontside capacitor storage node.Type: GrantFiled: December 1, 2005Date of Patent: December 19, 2006Assignee: Micron Technology, Inc.Inventor: Michael T. Andreas
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Patent number: 7132372Abstract: A method for preparing a semiconductor substrate surface (28) for semiconductor device fabrication, includes providing a semiconductor substrate (20) having a pure Ge surface layer (28) or a Ge-containing surface layer (12), such as SiGe. The semiconductor substrate (20) is cleaned using a first oxygen plasma process (14) to remove foreign matter (30) from the surface (28) of the substrate (20). The substrate surface (28) is next immersed in a hydrochloric acid solution (16) to remove additional foreign matter (30) from the surface (28) of the substrate (20). The immersion step is followed by a second oxygen plasma etch process (18), passivate the surface with a passivation layer (34), and provide for an atomically smooth surface for subsequent epitaxial or gate dielectric growth.Type: GrantFiled: July 29, 2004Date of Patent: November 7, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Steven M. Smith, Diana J. Convey, Andy E. Hooper, Yi Wei
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Patent number: 7129185Abstract: A substrate processing method includes the steps of removing carbon from a surface of a silicon substrate by irradiating an ultraviolet light on the surface in an essentially ultraviolet nonreactive gas atmosphere and forming an oxide film or an oxynitride film on the surface of the silicon substrate by irradiating an ultraviolet light thereon in an essentially ultraviolet reactive gas atmosphere. Further, a computer readable storage medium stores therein a program for controlling the substrate processing method.Type: GrantFiled: October 19, 2004Date of Patent: October 31, 2006Assignee: Tokyo Electron LimitedInventors: Shintaro Aoyama, Masanobu Igeta, Hiroshi Shinriki
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Patent number: 7125783Abstract: A method for preventing the formation of watermark defects includes the steps of forming a pad oxide, a silicon nitride layer and a silicon oxynitride layer over a semiconductor substrate. A photoresist mask is formed over the resulting structure, with the silicon oxynitride layer being used as an anti-reflective coating during exposure of the photoresist material. An etch is performed through the photoresist mask, thereby forming a trench in the substrate. The photoresist mask is stripped, and the silicon oxynitride layer is conditioned. For example, the silicon oxynitride layer may be conditioned by a rapid thermal anneal in the presence of oxygen or nitrogen. A wet clean step is subsequently performed to remove a native oxide layer in the trench. The conditioned silicon oxynitride layer prevents the formation of watermarks during the wet clean process.Type: GrantFiled: April 18, 2001Date of Patent: October 24, 2006Assignee: Integrated Device Technology, Inc.Inventors: Guo-Qiang Lo, Ohm-Guo Pan, Zhenjiang Yu, Yu-Lung Mao, Tsengyou Syau, Shih-Ked Lee
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Patent number: 7125784Abstract: The present invention relates to a method for forming an isolation film in a semiconductor device. After a trench for isolation is formed, a polymer film is stripped by a post cleaning process using BFN. A pre-treatment cleaning process using only SC-1 is performed and a sidewall oxidization process is then carried out. It is therefore possible to improve fail of the roughness of the trench sidewall and to easily strip polymer. Furthermore, since a conventional PET process is omitted, an isolation film manufacturing process is simplified. It is also possible to prohibit out-diffusion of dopants injected into a semiconductor substrate through a pre-treatment cleaning process using CLN N before the sidewall oxidization process. Incidentally, by forming a slope at the top corner of the trench, it is possible to prevent a gate oxide film thinning phenomenon that the gate oxide film thinner than a desired thickness is deposited at the trench corner.Type: GrantFiled: June 24, 2004Date of Patent: October 24, 2006Assignee: Hynix Semiconductor Inc.Inventors: Cha Deok Dong, II Keoun Han
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Patent number: 7119052Abstract: A composition including supercritical fluid and at least one additive selected from fluoro species, and primary and/or secondary amines, optionally with co-solvent, low k material attack-inhibitor(s) and/or surfactant(s). The composition has particular utility for cleaning of semiconductor wafers to remove post-ashing residues therefrom.Type: GrantFiled: June 24, 2003Date of Patent: October 10, 2006Assignee: Advanced Technology Materials, Inc.Inventors: Michael B. Korzenski, Chongying Xu, Thomas H. Baum, David Minsek, Eliodor G. Ghenciu
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Patent number: 7111629Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 gas is used as a first processing gas. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching is removed in annealing step with H2 flow. The environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process repeatability is improved.Type: GrantFiled: May 20, 2004Date of Patent: September 26, 2006Assignee: APL Co., Ltd.Inventors: Jeong-Ho Kim, Gil-Gwang Lee
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Patent number: 7104268Abstract: A wafer cleaning method and system including a combined high frequency signal, a low frequency signal, and in one embodiment a biased voltage signal, allows cleaning particles and impurities off of fine-structured wafers, through application of an acoustic field to the wafer through a cleaning liquid which fosters micro-bubble formation for effective cleaning while buffering micro-bubble growth which would otherwise damage the wafer.Type: GrantFiled: January 10, 2003Date of Patent: September 12, 2006Assignee: Akrion Technologies, Inc.Inventors: Yi Wu, Cole S. Franklin, Brian Fraser, Thomas Nicolosi
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Patent number: 7096873Abstract: A method for manufacturing a group III nitride compound semiconductor device includes irradiating a surface of a wafer with ultraviolet rays to thereby clean a resist residue from the surface of the wafer, the surface including a group III nitride compound semiconductor. The ultraviolet rays cause a reaction of oxygen molecules to form stimulated oxygen atoms having a strong oxidative power at the surface.Type: GrantFiled: August 24, 2001Date of Patent: August 29, 2006Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naoki Nakajo
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Patent number: 7087538Abstract: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.Type: GrantFiled: August 16, 2004Date of Patent: August 8, 2006Assignee: Intel CorporationInventors: David Staines, Grant M. Kloster, Shriram Ramanathan
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Patent number: 7077916Abstract: A substrate is cleaned by supplying an ultrasonically-agitated cleaning liquid onto the substrate from a nozzle provided above the substrate while spinning the substrate. The substrate being cleaned is spun at a rotational speed of 2600 rpm or more and 3500 rpm or less, or at a rotational speed of 260×V/D (rpm) or more and 350×V/D (rpm) or less, where D (mm) is a diameter of the nozzle and V (mm/sec) is a moving velocity of the nozzle.Type: GrantFiled: March 7, 2003Date of Patent: July 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yasuyuki Deguchi
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Patent number: 7078300Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.Type: GrantFiled: September 27, 2003Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Evgeni Gousev, Huiling Shang, Christopher P. D'Emic, Paul M. Kozlowski
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Patent number: 7067015Abstract: A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment of the present invention, a cleaning chemistry comprising nitric acid, hydrofluoric acid, and phosphoric acid in solution with deionized water is applied to the wafer surface to be cleaned preferably while subjected to megasonic assist cleaning. The wafer is preferably then subjected to brush scrubbing and a deionized water rinse with megasonic assist cleaning.Type: GrantFiled: October 31, 2002Date of Patent: June 27, 2006Assignee: Texas Instruments IncorporatedInventors: Changfeng Xia, Linlin Chen
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Patent number: 7067016Abstract: A method for post-etch cleaning of a substrate with MRAM structures and MJT structures and materials is disclosed. The method includes inserting the substrate into a first brush box configured for double-sided mechanical cleaning of the substrate. A non-HF, copper compatible chemistry is introduced into the first brush box for cleaning the active and backside surfaces of the substrate. The substrate is then inserted into a second brush box which is also configured to provide double-sided mechanical cleaning of the active and backside surfaces of the substrate. A burst of chemistry is introduced into the second brush box followed by a DIW rinse. The substrate is then processed through an SRD apparatus for final rinse and dry.Type: GrantFiled: March 31, 2003Date of Patent: June 27, 2006Assignee: Lam Research CorporationInventors: Katrina Mikhaylichenko, Michael Ravkin
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Patent number: 7067417Abstract: A contact hole can be formed in an insulating layer to expose a surface of an underlying silicon layer at a bottom of the contact hole having a first size. A metal silicide layer can be formed beneath the bottom of the contact hole and removed to form a void beneath the contact hole having a second size that is greater than the first size.Type: GrantFiled: June 30, 2004Date of Patent: June 27, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-sook Park, Gil-heyun Choi, Jong-myeong Lee
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Patent number: 7067428Abstract: A method for cleaning polysilicon comprises steps of cleaning solid or granular polysilicon with an aqueous solution of dissolved ozone, and of cleaning with hydrofluoric acid the polysilicon receiving the above cleaning based on an aqueous solution of dissolved ozone, wherein the above steps are executed once in this order, or the above steps are repeated once or more in this order. Subsequent to the last cleaning step using hydrofluoric acid, a still other step of cleaning the polysilicon with pure water and then drying it is preferably added. This method for cleaning polysilicon allows organic materials, particles and metal impurities adsorbed on the surface of polysilicon to be removed at a low cost, and to increase the freeing rate.Type: GrantFiled: June 27, 2002Date of Patent: June 27, 2006Assignee: Mitsubishi Materials Silicon Corp.Inventor: Kenji Hori
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Patent number: 7047989Abstract: In accordance with one embodiment there is provided a method of improving the performance of a substrate cleaner of the type having a megasonic probe with a probe shaft extending generally parallel to a surface of a rotating substrate, and at least one dispenser for applying a cleaning liquid onto the surface of the substrate, wherein the megasonic probe agitates the liquid on the surface. The method comprising dissolving gas in the liquid before the liquid reaches the dispenser. In accordance with another embodiment, an apparatus for cleaning substrates comprises a rotary fixture which is adapted to support a substrate and rotate the substrate about a first axis, a probe having a probe shaft extending generally parallel to a surface of the substrate, and a megasonic transducer in acoustically coupled relation to the probe.Type: GrantFiled: December 19, 2003Date of Patent: May 23, 2006Assignee: Akrion Technologies, Inc.Inventors: Tom Nicolosi, Yi Wu
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Patent number: 7033946Abstract: A method of removing an oxide layer from an article. The article may be located in a reaction chamber into which an interhalogen compound reactive with the oxide layer is introduced. A temperature of the reaction chamber may be modified so as to remove the oxide layer. The interhalogen compound may form volatile by-product gases upon reaction with the oxide layer. Unreacted interhalogen compound and volatile by-product gases may then be removed from the reaction chamber.Type: GrantFiled: December 4, 2002Date of Patent: April 25, 2006Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Donald L. Westmoreland
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Patent number: 7030036Abstract: Provided is related to a method of forming an oxide layer of a semiconductor device. In the method, a first oxide layer is formed with a first thickness on a semiconductor substrate, that is comparted into first and second fields, and then a second oxide layer is formed on the first field with a second thickness, while preventing damages on the surface of the semiconductor substrate, after removing the first oxide layer on the first field. By the method, oxide layers different in thickness can be formed in separate field on the semiconductor substrate, without damages due to an etching process while enhancing the physical quality of the oxide layers.Type: GrantFiled: June 29, 2004Date of Patent: April 18, 2006Assignee: Hynix Semiconductor Inc.Inventor: Ho Min Son
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Patent number: 7022537Abstract: A liquid crystal display device includes a substrate, an organic insulating film formed on the substrate, an alignment film having a first etch rate formed on the organic insulating film, and a silicon nitride layer having a second etch rate formed between the alignment film and the organic insulating film, wherein the first etch rate is different from the second etch rate.Type: GrantFiled: November 3, 2003Date of Patent: April 4, 2006Assignee: LG.Philips LCD Co., Ltd.Inventors: Kyo Ho Moon, Yong In Park
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Patent number: 7018552Abstract: A method of manufacturing an electronic device comprises forming a wiring material layer made of aluminum or an aluminum alloy on the surface of an insulating film on a substrate, patterning the wiring material layer by a reactive ion etching treatment with a resist pattern used as a mask so as to form a wiring, and treating the surface of the insulating film including the wiring with an aqueous solution for removing the etching residue, the aqueous solution containing a peroxosulfate, a fluorine-containing compound and an acid for adjusting the pH value and having a pH value of ?1 to 3.Type: GrantFiled: March 18, 2003Date of Patent: March 28, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Ikuo Uematsu, Naoya Hayamizu
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Patent number: 7015183Abstract: The present invention relates to a resist remover composition for removing resists during manufacturing processes of semiconductor devices such as integrated circuits, large scale integrated circuits and very large scale integrated circuits. The composition comprises (a) 10 to 40 wt. % of a water-soluble organic amine compound, (b) 40 to 70 wt. % of water-soluble organic solvents selected from a group consisting of dimethyl sulfoxide (DMSO), N-methyl pyrrolidone (NMP) dimethylacetamide (DMAc), dimethylformamide (DMF) and a mixture thereof, (c) 10 to 30 wt. % of water, (d) 5 to 15 wt. % of an organic phenol compound containing two or three hydroxyl groups, (e) 0.5 to 5 wt. % of anion type compound containing perfluoroalkyl, and (f) 0.01 to 1 wt. % of a polyoxyethylenealkylamine ether-type surfactant.Type: GrantFiled: May 21, 2001Date of Patent: March 21, 2006Assignee: Dongjin Semichem Co., Ltd.Inventors: Ji-Hum Baik, Chang-Il Oh, Chong-Soon Yoo
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Patent number: 7001086Abstract: A developing method comprises determining in advance the relation of resist dissolution concentration in a developing solution and resist dissolution speed by the developing solution, estimating in advance the resist dissolution concentration where the resist dissolution speed is a desired speed or more from the relation, and developing in a state in which the resist dissolution concentration in the developing solution is the estimated dissolution concentration or less.Type: GrantFiled: October 21, 2004Date of Patent: February 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masamitsu Itoh, Ikuo Yoneda, Hideaki Sakurai
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Patent number: 6992023Abstract: The invention provides methods and apparatus for drying the backside of semiconductor wafers in a spin-coating environment. Solvent is evaporatively dried from a semiconductor wafer held in a spin mechanism. The undried wafer is sprayed with one or more jets of pressurized gas from gas ports disposed about the spin mechanism.Type: GrantFiled: December 20, 2002Date of Patent: January 31, 2006Assignee: Texas Instruments IncorporatedInventor: David C. Hall
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Patent number: 6992016Abstract: Air trapped in a blind hole during processing of the blind hole with a liquid is eliminated by circulating the liquid along a surface-to-be-processed in substantially a single direction at all times and by setting a velocity gradient of the liquid over the surface to at least 300/second.Type: GrantFiled: December 2, 2004Date of Patent: January 31, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeo Nakamoto, Katsuya Kosaki, Masaru Kinugawa
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Patent number: 6973934Abstract: The purpose of the present invention is to remove minute particles adhered to the surface of semiconductor wafers effectively in the cleaning process of semiconductor wafers. In the final rinsing step using ultra-pure water or hydrogen water and carried out after cleaning of semiconductor wafers with HF solution, ultrasonic waves are irradiated in the cleaning solution after a prescribed time delay (preferably 20-30 sec or more).Type: GrantFiled: February 8, 2002Date of Patent: December 13, 2005Assignee: Texas Instruments IncorporatedInventors: Toshihito Tsuga, Minoru Fube, Kazutaka Nakayama
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Patent number: 6972227Abstract: Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation, a semiconductor wafer backside is mechanically scrubbed to remove an undesired material prior to forming a final passivation layer over an oppositely facing semiconductor wafer frontside. In another implementation, the wafer backside is treated to remove the undesired material while treatment of the wafer frontside is restricted. In another implementation, the mechanical scrubbing of the wafer backside is conducted in connection with a polishing solution which is effective to facilitate removal of undesired material from the wafer backside. In a preferred implementation, dynamic random access memory storage capacitors are formed and the undesired material constitutes remnant polysilicon which adheres to the wafer backside during formation of a frontside capacitor storage node.Type: GrantFiled: August 13, 2002Date of Patent: December 6, 2005Assignee: Micron Technology, Inc.Inventor: Michael T. Andreas
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Patent number: 6969682Abstract: A system for processing wafers includes a robot moveable within an enclosure to load and unload workpieces into and out of workpiece processors. A processor includes an upper rotor having alignment pins, and a lower rotor having one or more openings for receiving the alignment pins to form a processing chamber around the workpiece. The alignment pins center the workpiece relative to a rotor spin axis and to an etch or drain groove in the upper rotor. A first fluid outlet delivers processing fluid to a central region of the workpiece. The processing fluid is distributed across the workpiece surface via centrifugal force generated by spinning the processing chamber. Purge gas is optionally delivered into the processing chamber through an annular opening around the first fluid outlet to help remove processing fluid from the processing chamber.Type: GrantFiled: October 24, 2003Date of Patent: November 29, 2005Assignee: Semitool, Inc.Inventors: Kyle M. Hanson, Paul Z. Wirth, Steven L. Peace, Jon Kuntz, Scott A. Bruner
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Patent number: 6967176Abstract: Method and apparatus for forming thin silicon oxide films on silicon carbide substrates utilizing an afterglow thermal reactor. The method of forming thin silicon oxide film includes the steps of loading a silicon carbide substrate within a tube, which tube is heated, and the contents pressure is controlled. An oxidizing gas is then passed through an afterglow reactor source or microwave cavity where the gas achieves an excited state of energy. When the neutral species of the excited gas contact the silicon carbide substrate within the heated region of the the tube, a thin silicon oxide film forms on the substrate, at a faster rate and lower temperature than has been known. The tube contents are maintained at a temperature between 600° C. to 1,200° C., and at a pressure less than 50 torr.Type: GrantFiled: October 13, 2003Date of Patent: November 22, 2005Assignee: University of South FloridaInventor: Andrew M. Hoff
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Patent number: 6962630Abstract: A lift-off procedure is provided which enables prevention of damage to a wiring pattern caused by contact of a metal being peeled off from a wafer with a wiring pattern at a time of lift-off procedure. A wafer having a surface on which a pattern is formed which contains a pattern portion to be removed is soaked into a chemical liquid at an angle at which the surface faces downward.Type: GrantFiled: October 3, 2002Date of Patent: November 8, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Masaru Suzuki, Yoshiki Nitta, Kazuhiko Ohmuro
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Patent number: 6949411Abstract: A method for cleaning a semiconductor wafer is provided which includes plasma etching a feature into a low K dielectric layer having a photoresist mask where the plasma etching generates etch residues. The method also includes ashing the semiconductor wafer to remove the photoresist mask where the ashing generating ashing residues. The method further includes removing the etching residues and the ashing residues from the low K dielectric layer where the removing is enhanced by scrubbing the low K dielectric layer of the semiconductor wafer with a wet brush that applies a fluid mixture including a cleaning chemistry and a wetting agent.Type: GrantFiled: December 27, 2001Date of Patent: September 27, 2005Assignee: Lam Research CorporationInventors: Katrina Mikhaylichenko, Michael Ravkin, John deLarios
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Patent number: 6946036Abstract: The method for removing particles that adhere to the surface of semiconductor wafers is constituted so as to sequentially carry out a first cleaning process in which semiconductor wafers 100 are cleaned for a prescribed time in cleaning tank 104 containing a first cleaning solution consisting of ozone water, and, after said first cleaning process, a second cleaning process in which said semiconductor wafers 100 are cleaned for a prescribed time in cleaning tank 106 containing a second cleaning solution consisting of hydrogen water.Type: GrantFiled: February 28, 2002Date of Patent: September 20, 2005Assignee: Texas Instruments IncorporatedInventors: Toshihito Tsuga, Minoru Fube, Kazutaka Nakayama
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Patent number: 6943062Abstract: The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.Type: GrantFiled: October 20, 2003Date of Patent: September 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Miao Chen, Yu-Chang Jong, Huan-Chi Tseng
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Patent number: 6938638Abstract: A gas-circulating processing apparatus which comprises a processing chamber, a gas feeding piping, a gas supply piping, a first exhaust mechanism discharging a gas from the processing chamber, a second exhaust mechanism discharging a portion of a gas discharged from the first exhaust mechanism, a back pressure adjusting mechanism interposed between the first exhaust mechanism and the second exhaust mechanism to adjust a back pressure of the first exhaust mechanism, and a gas circulating piping which is configured to combine another portion of the gas that has been discharged from the first exhaust mechanism with a processing gas supplied from the gas supply piping, wherein the gas feeding piping has a larger inner diameter than that of the gas supply, or the processing gas is introduced into the first exhaust mechanism, or a first heater is provided to heat at least part of the circulating route.Type: GrantFiled: December 27, 2001Date of Patent: September 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kubota, Rempei Nakata, Naruhiko Kaji, Itsuko Sakai, Takashi Yoda
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Patent number: 6933157Abstract: A method of manufacturing a semiconductor wafer including cleaning a surface of the wafer during a first time period and forming a layer over the surface during a second time period. The first time period includes a cleaning delay period prior to a cleaning portion of the first time period, the cleaning delay period configured such that an end time of the first time period substantially coincides with a start time of the second time period.Type: GrantFiled: November 13, 2003Date of Patent: August 23, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen
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Patent number: 6930046Abstract: A system and method for processing a workpiece, includes workpiece processors. A robot is moveable within an enclosure to load and unload workpieces into and out of the processors. A processor includes an upper rotor having a central air flow opening. The upper rotor is magnetically driven into engagement with a lower rotor to form a workpiece processing chamber. A moveable drain mechanism aligns different drain paths with the processing chamber so that different processing fluids may be removed from the processing chamber via different drain paths. A moveable nozzle positioned in the air flow opening distributes processing fluid to the workpiece. The processing fluid is distributed across the workpiece surface, via centrifugal force generated by spinning the processing chamber, and removed from the processing chamber via the moveable drain mechanism.Type: GrantFiled: October 21, 2003Date of Patent: August 16, 2005Assignee: Semitool, Inc.Inventors: Kyle M. Hanson, Eric Lund, Coby Grove, Steven L. Peace, Paul Z. Wirth, Scott A. Bruner, Jonathan Kuntz
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Patent number: 6911097Abstract: Provided is a process and apparatus characterized by a gas distribution plate in which a gas supply manifold directs gas bubbles from the bottom of a process tank upward and between wafers contained in a cassette and supported therewithin. This improved method and apparatus is used for effectively stripping photoresist from the larger semiconductor wafers having dense top conductive patterns with protuberant sidewalls. The method provides a scrubbing action that is parallel to the device array being formed on the wafer's surface. Broadly stated, the method of a chemical action on large substrates supported adjacent respective edge portions thereof in a carrier includes submerging the carrier and substrates supported thereby in a process tank containing a liquid chemical, and a gas distribution plate disposed on the bottom of the tank for directing gas bubbles upward and parallel to the surfaces of each substrate contained in the carrier to ensure that a uniform chemical action occurs.Type: GrantFiled: July 31, 2000Date of Patent: June 28, 2005Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chie-Chi Chen, Wen-Hsiang Tseng, Sheng-Liang Pan, Jen-Shiang Fang
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Patent number: 6911096Abstract: A method of collecting impurities existing on the surface of a semiconductor wafer and in a thin film formed on the semiconductor wafer is provided with a process for dripping collecting liquid on the surface of the semiconductor wafer to which hydrophobic processing is applied, a process for elongating the collecting liquid dripped and turned spherical by surface tension in a direction of the radius of the semiconductor wafer with the surface tension kept, a process for relatively rolling and scanning the elongated collecting liquid, touching the collecting liquid to the surface of the semiconductor wafer and incorporating impurities into the collecting liquid, a process for restoring the elongated collecting liquid to the original spherical shape after the impurities are incorporated and a process for withdrawing the collecting liquid restored to the spherical shape from the surface of the semiconductor wafer.Type: GrantFiled: November 6, 2002Date of Patent: June 28, 2005Assignee: NEC Electronics CorporationInventor: Kaori Watanabe
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Patent number: 6905965Abstract: The present invention generally provides a precleaning process prior to metallization for submicron features on substrates. The method includes cleaning the submicron features with radicals from a plasma of a reactive gas such as oxygen, a mixture of CF4/O2, or a mixture of He/NF3, wherein the plasma is preferably generated by a remote plasma source and the radicals are delivered to a chamber in which the substrate is disposed. Native oxides remaining in the submicron features are preferably reduced in a second step by treatment with radicals from a plasma containing hydrogen. Following the first or both precleaning steps, the features can be filled with metal by available metallization techniques which typically include depositing a barrier/liner layer on exposed dielectric surfaces prior to deposition of aluminum, copper, or tungsten. The precleaning and metallization steps can be conducted on available integrated processing platforms.Type: GrantFiled: February 17, 2004Date of Patent: June 14, 2005Assignee: Applied Materials, Inc.Inventors: Suchitra Subrahmanyan, Liang-Yuh Chen, Roderick Craig Mosely
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Patent number: 6892738Abstract: The present invention provides a megasonic cleaning apparatus configured to provide effective cleaning of a substrate without causing damage to the substrate. The apparatus includes a probe having one of a variety of cross-sections configured to decrease the ratio of normal-incident waves to shallow-angle waves. One such cross-section includes a channel running along a portion of the lower edge of the probe. Another cross-section includes a narrow lower edge of the probe. Another cross-section is elliptical. Another cross-section includes transverse bores originating in the lower edge of the probe. As an alternative to, or in addition to, providing a probe having a cross-section other than circular, the present invention may also provide a probe having a roughened lower surface.Type: GrantFiled: January 20, 2004Date of Patent: May 17, 2005Assignee: Goldfinger Technologies, LLCInventors: Mario E. Bran, Michael B. Olesen, Yi Wu
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Patent number: 6890853Abstract: A method of depositing a metal film on a substrate includes a supercritical preclean step, a supercritical desorb step, and a metal deposition step. Preferably, the preclean step includes maintaining supercritical carbon dioxide and a chelating agent in contact with the substrate in order to remove an oxide layer from a metal surface of the substrate. More preferably, the preclean step includes maintaining the supercritical carbon dioxide, the chelating agent, and an acid in contact with the substrate. Alternatively, the preclean step includes maintaining the supercritical carbon dioxide and an amine in contact with the oxide layer. The desorb step includes maintaining supercritical carbon dioxide in contact with the substrate in order to remove adsorbed material from the substrate.Type: GrantFiled: April 24, 2001Date of Patent: May 10, 2005Assignee: Tokyo Electron LimitedInventors: Maximilian A. Biberger, Paul E. Schilling
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Patent number: 6887788Abstract: Disclosed is a method of manufacturing a semiconductor device. The method comprises the steps of: preparing a silicon substrate having a predetermined lower structure including a gate and a bonding area; forming an interlayer dielectric film on the top side of the substrate; forming a photosensitive film pattern, which exposes an area for providing contact, on the interlayer dielectric film; forming a contact hole exposing a bonding area of the substrate by etching the exposed part of the interlayer dielectric film; removing the photosensitive film pattern; performing a dry cleaning on the exposed bonding area of the substrate so that CF based polymer formed in the etching step is removed; and performing a nitrogen-hydrogen plasma processing on the surface of the exposed bonding area of the substrate so that oxygen polymer and remaining CF-based polymer are removed. Therefore, since hydrogen plasma processing is performed after contact etching, ohmic contact characteristics can be secured.Type: GrantFiled: November 7, 2003Date of Patent: May 3, 2005Assignee: Hynix Semiconductor Inc.Inventors: Jun Hee Cho, Il Wook Kim, Seok Kiu Lee, Tae Hang Ahn, Sung Eon Park
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Patent number: 6884701Abstract: A process for fabricating a semiconductor device having a buried layer comprises the steps of implanting an impurity ion into where the buried layer to be formed in a substrate, providing the substrate inside a reactor furnace, preparing a nonoxidizing atmosphere inside of the reactor furnace, annealing the substrate to activate and diffuse the implanted impurity ion region while increasing inside temperature of the reactor furnace up to a first temperature, and shifting the inside temperature of the reactor furnace from the first temperature to a second temperature in which a epitaxial crystal starts to grow and introducing a epitaxial growth gas into the reactor furnace to grow an epitaxial layer on a surface of the substrate.Type: GrantFiled: December 16, 1998Date of Patent: April 26, 2005Inventor: Hidemi Takasu
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Patent number: 6878213Abstract: Semiconductor substrates, particularly metallized substrates such as partially processed wafers, are rinsed with an aqueous medium, preferably deionized water, which further contains an anti-corrosive chemical agent or agents selected so as to minimize corrosion of metals resulting from contact with the water. The amount of anti-corrosive chemical agent is maintained in a controlled manner at a predetermined level or within a predetermined range preferably the rinsing with aqueous medium containing anticorrosive chemical agent is also carried out for a specified time, followed by further rinsing with deionized water alone. The rinsing may be combined, either in the same vessel or in a different vessel, with a subsequent drying step, such as a drying process utilizing a drying vapor introduced into the rinse tank or into a downstream vessel.Type: GrantFiled: September 29, 1999Date of Patent: April 12, 2005Assignee: SCP Global Technologies, Inc.Inventors: John J. Rosato, Jane Fahrenkrug, Curtis R. Olson, Paul G. Lindquist
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Patent number: 6872598Abstract: A semiconductor device wafer 11 is integrated with a supporting board 13 by a double-faced thermally foaming adhesive sheet 12, and this assembly is fixed to a vacuum sucking pedestal 14 under vacuum sucking. A thermally foaming adhesive layer of the adhesive sheet 12 functions as a shock absorber, whereby the wafer 11 hardly cracks during a high-speed grinding operation even if the wafer uses a GaAs substrate which is susceptible to damages. Neither fixing of the wafer 11 using wax nor abrasion using an oil abrasive agent is necessary, so that contamination of wax and oil is prevented and cleaning of the wafer becomes easy. Heating at 130° C. makes the thermally foaming adhesive layer of the adhesive sheet 12 expand so that the wafer 11 is readily separated from the adhesive sheet.Type: GrantFiled: February 27, 2003Date of Patent: March 29, 2005Assignee: Sharp Kabushiki KaishaInventor: Yi Liu
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Patent number: 6869810Abstract: A manufacturing method of a semiconductor device, including the steps of forming a metal wire on a circuit formed on a semiconductor substrate, forming an insulating film on the metal wire, forming a via hole in the insulating film so as to expose a surface of the metal wire by selectively etching the insulating film by a plasma dry etching method, measuring a first level difference between the surface of the metal wire and the surface of the insulating film by a non-contact measurement method, removing the metal oxide film on the surface of the metal film by cleaning the surface of the metal film, measuring a second level difference between the surface of the metal film and the surface of the insulating film by a non-contact measurement method, and determining an amount of oxidation of the metal wire from a difference between the first and the second level differences.Type: GrantFiled: May 12, 2004Date of Patent: March 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masahiro Joei
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Patent number: 6866723Abstract: A wet treatment method useful in one of a chemical processing and a rinsing step performed upon fabrication of semiconductor devices. A substrate is treated with a desired liquid while revolving the substrate around an axis of rotation outside the substrate such that the liquid flowing on a surface of the substrate is maintained flowing under a centrifugal force greater than gravitation. The substrate is treated while supplying the liquid at a flow rate at least equal to a discharge rate of the liquid only in a direction conforming with that of the centrifugal force or with that of a flow of the liquid flowing on the surface of the substrate under the centrifugal force. The substrate surface is evenly treated with the liquid while avoiding flows of the liquid running against each other or a flow of the liquid stagnating on the surface of the substrate.Type: GrantFiled: August 6, 2001Date of Patent: March 15, 2005Assignee: m.FSI Ltd.Inventors: Takeji Ueda, Koji Oka, Sanae Sumi
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Patent number: 6867120Abstract: In a semiconductor device, particles are removed from the surface of a gold conductive layer before an intermediate insulating layer of an amino silane compound is formed. An organic insulating layer is formed on the intermediate insulating layer. As a result, adhesion strength between the conductive layer and the intermediate insulating layer can be improved.Type: GrantFiled: January 29, 2003Date of Patent: March 15, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Takehiko Okajima, Masahisa Ikeya
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Patent number: RE38760Abstract: Oxides are etched with a halide-containing species and a low molecular weight organic molecule having a high vapor pressure at standard conditions, where etching is performed at preset wafer temperature in an enclosed chamber at a pressure such that all species present in the chamber, including water, are in the gas phase and condensation of species present on the etched surface is controlled. Thus all species involved remain in the gas phase even if trace water vapor appears in the process chamber. Preferably, etching is performed in a cluster dry tool apparatus.Type: GrantFiled: July 30, 1997Date of Patent: July 19, 2005Assignee: Penn State Research FoundationInventors: Robert W. Grant, Jerzy Ruzyllo, Kevin Torek