Abstract: An imaging device is provided and includes: a photoelectric conversion layer that has a silicon crystal structure and generates signal charges upon incidence of light; a multiplication and accumulation layer that multiplies the signal charges by a phenomenon of avalanche electron multiplication; and a wiring substrate that reads the signal charges from the multiplication and accumulation layer and transmits the read signal charges.

Abstract: A semiconductor light-receiving device and its manufacturing method are provided which are capable of suppressing dark current and deterioration. Semiconductor crystals were sequentially grown over an n-type InP substrate, including an n-type InP buffer layer, an undoped GaInAs light absorption layer, an undoped InP diffusion buffer layer, and a p-type InP window layer. Next, a first mesa was formed by removing a part from the p-type InP window layer to the n-type InP buffer layer with a Br-based etchant having low etching selectivity, so as to form a sloped “normal” mesa structure. Next, a second mesa having a smaller diameter than the first mesa was formed by dry etching, by precisely removing a part from the p-type InP window layer to a certain mid position of the undoped InP diffusion buffer layer.

Abstract: A single-photon avalanche detector is disclosed that is operable at wavelengths greater than 1000 nm and at operating speeds greater than 10 MHz. The single-photon avalanche detector comprises a thin-film resistor and avalanche photodiode that are monolithically integrated such that little or no additional capacitance is associated with the addition of the resistor.

Abstract: A high power diode includes a cathode for emitting a primary electron discharge, an anode, and a porous dielectric layer, e.g. a honeycomb ceramic, positioned between the cathode and the anode for receiving the primary electron discharge and emitting a secondary electron discharge. The diode can operate at voltages 50 kV and higher while generating an electron beam with a uniform current density in the range from 1 A/cm2 to >10 kA/cm2 throughout the area of the cathode. It is capable of repetitively pulsed operation at a few Hz with pulse duration from a few nanoseconds to more than a microseconds, while the total number of pulses can be >107 pulses. The diode generates minimal out-gassing or debris, i.e. with minimal ablation, providing a greater diode lifetime, and can operate in a high vacuum environment of 10?4 Torr. The high power diode is useful in many applications requiring a high current electron beam.

Abstract: A method of forming a diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The method including forming an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. Forming isolation regions such that the cathode and anode are disposed between and bounded by adjacent isolation regions.

Abstract: An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components.

Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a mesa structure defined in a first type of semiconductor. The first type of semiconductor material includes an absorption region optically coupled to receive and absorb an optical beam. The apparatus also includes a planar region proximate to and separate from the mesa structure and defined in a second type of semiconductor material. The planar region includes a multiplication region including a p doped region adjoining an n doped region to create a high electric field in the multiplication region. The high electric field is to multiply charge carriers photo-generated in response to the absorption of the optical beam received in the mesa structure.

Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

Abstract: The present invention related to a method of manufacturing an LED, including the steps of: first, forming a tape coppery metal strip; then, continuously pressing circuits on the tape coppery metal strip so as to form a carrier having circuit patterns of electric contacts on which the diode dies can be placed; next, electroplating a plurality of metal layers on the surface of the carrier; then, performing continuous injection molding on the carrier so as to form a protector having a designated shape; and curing and fixing the diode die on the carrier to connect to the terminal contact of the carrier via metal wire. A conductive or non-conductive adhesive is dropped onto the bonding position between the metal wire and the terminal of the carrier, and a soft paste is Anther applied to cover the diode die, the metal wire and the terminal.

Abstract: A method is provided for forming a semiconductor-detection device that provides internal gain. The method includes forming a plurality of bottom trenches in a bottom surface of an n-doped semiconductor wafer; and forming a second plurality of top trenches in a top surface of the semiconductor wafer. The bottom surface and the top surface are opposed surfaces. Each of the bottom trenches is substantially parallel to and substantially juxtaposed to an associated one of the top trenches. The method further includes doping the semiconductor wafer with at least one p-type dopant to form a p-region that defines at least one n-well within the p-region, wherein a p-n junction is formed substantially at an interface of the n-well and the p-region; and removing a portion of the bottom surface to form a remaining-bottom surface, wherein a portion of the n-well forms a portion of the remaining-bottom surface.

Abstract: A method for manufacturing a mask for integrated circuit devices. The method includes providing a quartz substrate having a surface and forming a MoSi film overlying the surface of the quartz substrate. The method also includes patterning the MoSi film overlying the quartz substrate to form a mask pattern. A step of forming an opaque edge structure comprising a carbon bearing material on a portion of the surface around a peripheral region of the mask pattern is also included.

Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: A process for producing a cold cathode field emission device. A cathode electrode is formed on a front surface of a support member that transmits exposure light. An insulating layer is formed on an entire surface. A gate electrode is formed on the insulating layer. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure. An electron-emitting-portion-forming-layer composed of a photosensitive material is formed at least inside the opening portion. The support member is irradiated with exposure light from a back surface side of the support member through the hole as a mask for exposure.

Abstract: A semiconductor photodetection device includes a semiconductor structure including an optical absorption layer having a photo-incidence surface on a first side thereof, a dielectric reflecting layer formed on a second side of the semiconductor structure opposite to the first side, a contact electrode surrounding the dielectric reflecting layer and contacting with the semiconductor structure, and a close contact electrode covering the dielectric reflecting layer and contacting with the contact electrode and the dielectric reflecting layer, wherein the close contact electrode adheres to the dielectric reflecting layer more strongly than to the contact electrode.

Abstract: In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate.

Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.

Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.

Abstract: There is provided a semiconductor photodetector which comprises (i) an InP substrate(1), (ii) an optical waveguide(5) having an N-type semiconductor layer(32) formed on the InP substrate(1), an optical waveguide core layer(3) formed on a partial area of the N-type semiconductor layer(32), and an upper cladding layer(4) formed on the optical waveguide core layer(3), and (iii) an avalanche photodiode(17) constructed by forming a photo absorbing layer(33), a heterobarrier relaxing layer(34), an underlying layer(14a) of a N-type field dropping layer(35), an overlying layer(14b) of the N-type field dropping layer(35), a carrier multiplying layer(36), and a P-type semiconductor layer(37) in sequence on another area of the N-type semiconductor layer(32), and coupled to the optical waveguide(5), wherein a side surface of the underlying layer(14a) of the N-type field dropping layer(35) comes into contact with a side surface of the optical waveguide core layer(3), and a part of the overlying layer(14b) of the N-type fi

Abstract: A high efficiency light emitting diode (LED) with metal reflector and the method of making the same is disclosed. The metal reflector is composed of at least two layers with one transparent conductive layer and the other highly reflective metal layer. The transparent conductive layer allows most of the light passing through without absorption and then reflected back by the highly reflective metal layer. The transparent conductive layer is selected from one of the materials that have very little reaction with highly reflective metal layer even in high temperature to avoid the reflectivity degradation during the chip processing. With this at least two layer metal reflector structure, the light emitting diode with vertical current injection can be fabricated with very high yield.

Abstract: A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.

Abstract: In order to subdivide a wafer (1) into chips, recesses (7) are introduced from a rear side (6), said recesses weakening the wafer (1) at the breaking points. As a result, it is possible to produce chips whose length dimensions are less than twice the thickness of the chips.

Abstract: The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

Abstract: A single-electrode, push-pull semiconductor PIN Mach-Zehnder modulator (10) that includes first and second PIN devices (12, 14) on a substrate (16). Intrinsic layers (22, 28) of the devices (12, 14) are the active regions of two arms (50, 52) of a Mach-Zehnder interferometer. An outer electrode (38) is connected to the N layer (24) of the first PIN device (12) and a center electrode (40) is connected to the P layer (20) of the first PIN device (12). An outer electrode (42) is connected to the P layer (26) of the second PIN device (14) and the center electrode (40) is connected to the N layer (30) of the second PIN device (14). An RF modulation signal biases the PIN devices (12, 14) in opposite directions and causes the index refraction of the intrinsic layers (22, 28) to change in opposite directions to give a push-pull modulation effect.

Abstract: A method for manufacturing an improved APD structure and an improved manner of operating APD's particularly beneficial for a single photon detection applications are provided. An APD is provided having an absorption region, a control region, and a multiplication region, wherein the multiplication region has a k value of approximately 1. In one example the multiplication region comprises a doped InP layer. The field control layer is designed so as to produce a reduction of electric field that is equal to the multiplication region's breakdown electric field, plus or minus 5V/&mgr;m. The method comprises applying a potential across the APD so as to induce an electric field across the multiplication region that exceeds the breakdown field; while having the control region shield the absorption region to prevent excessive noise.

Abstract: The present invention relates to an impact ionisation avalanche transit time (IMPATT) diode device comprising an avalanche region and a drift region, wherein at least one narrow bandgap region, with a bandgap narrower than the bandgap in the avalanche region, is located adjacent to or within the avalanche region in order to generate within the narrow bandgap region a tunnel current which is injected into the avalanche region. This improves the predictability with which a current can be injected into the avalanche region and enables a relatively narrow pulse of current to be injected into the avalanche region in order to enable a relatively noise free avalanche multiplication. The narrow bandgap region may be located between a heavily doped contact region and the avalanche region and is preferably arranged to generate a tunnel current at the peak reverse bias applied to the diode.

Abstract: An Indium/Gallium/Arsenide (InGaAs) detector having avalanche photodiodes (APD's) and p-i-n photodiodes on a single chip is provided. A method of fabricating the InGaAs device is also provided. The bias on the APD and p-i-n photodiodes are separately controlled.

Abstract: There is provided a semiconductor photodetector which comprises (i)an InP substrate(1), (ii)an optical waveguide(5) having an N-type semiconductor layer(32) formed on the InP substrate(1), an optical waveguide core layer(3) formed on a partial area of the N-type semiconductor layer(32), and an upper cladding layer(4) formed on the optical waveguide core layer(3), and (iii)an avalanche photodiode(17) constructed by forming a photo absorbing layer(33), a heterobarrier relaxing layer(34), an underlying layer(14a) of a N-type field dropping layer(35), an overlying layer(14b) of the N-type field dropping layer(35), a carrier multiplying layer(36), and a P-type semiconductor layer(37) in sequence on another area of the N-type semiconductor layer(32), and coupled to the optical waveguide(5), wherein a side surface of the underlying layer(14a) of the N-type field dropping layer(35) comes into contact with a side surface of the optical waveguide core layer(3), and a part of the overlying layer(14b) of the N-type field

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active layer. An anode electrode and a cathode electrode are formed on the uppermost contact layer. A high resistance region around the cathode electrode is formed at least in an uppermost contact layer by ion implantation using the cathode and anode electrode as a mask. A region under the cathode electrode functions as a Gunn diode and a region under the anode electrode function as a conductive path from the anode electrode to the active layer. These two regions are defined by the high resistance region.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: A structure with an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 for the anode emitter, especially on its surface 1019 dopant atoms per cm3or more for the cathode emitter and approximately 1016 dopant atoms per cm3 for the blocking function of an anode-side zone.

Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output.

Abstract: A photodiode array device having an absorption layer and a cladding layer formed on one surface of a single substrate, anodes formed on the cladding layer, a cathode formed on the other surface of the substrate, and a plurality of light-receiving regions; a photodiode module including the photodiode array device; and a structure for connecting the photodiode module and an optical connector. The photodiode array device has trenches formed on the one surface of the substrate and having such a depth as to divide the absorption layer into subdivisions, for cutting off propagation of light between adjacent light-receiving regions.

Abstract: An avalanche photodiode fabricating method with a simplified fabrication process and an improved reproducibility is disclosed.

Abstract: A non-hermetic APD for operation in a moisture-containing ambient comprises an InP/InGaAsP-containing Group III-V compound semiconductor body and a p-n junction formed in the body. Typically the junction intersects a top surface of the body. A patterned dielectric layer is formed on the surface so as to cover at least those regions of the surface that are intersected by the junction. An electrode is formed in an opening in the dielectric layer so as to make electrical contact with one side of the junction. Importantly, the thickness of the dielectric layer is sufficient to reduce the leakage current through it to less than about 1 nA when the operating voltage is in the range of about 20-100 V. In accordance with a preferred embodiment, the thickness of the dielectric layer is greater than about 2 &mgr;m when the applied voltage is in excess of about 20 V. Moreover, the composition of dielectric layer may be either inorganic (e.g., a silicon nitride) or a combination of inorganic and organic materials.

Abstract: A method of improving the speed of a heterojunction bipolar device without negatively impacting ruggedness of the device is provided. This method includes the steps of providing a structure that includes at least a bipolar device region, the bipolar device region comprising at least a collector region formed over a sub-collector region; and forming an n-type dopant region within the collector region, wherein the n-type dopant region has a vertical width that is less than about 2000 Å and a peak concentration that is greater than a peak concentration of the collector region. The present invention also provides a method of fabricating a heterojunction bipolar transistor device as well as the device itself which can be used in various applications including as a component for a mobile phone, a component of a personal digital assistant and other like applications wherein speed and ruggedness are required.

Abstract: An integrated optoelectronic circuit chip for optical data communication systems includes a silicon substrate, at least one MOS field effect transistor (MOSFET) formed on a portion of the silicon substrate, and an avalanche photodetector operatively responsive to an incident optical signal and formed on another portion of the substrate. The avalanche photodetector includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is ionizable by the incident optical signal to form freed charge carriers in the light absorbing region. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth of less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A solar cell comprises a superstrate formed from a material that is transparent to light, a first layer formed of delta doped silicon, a plurality of layers formed from semiconductor materials, each characterized by multi-quantum wells and multiple band gaps, a first semiconductor layer having a band gap energy state that is the smallest, the last semiconductor layer having-a band gap that is the largest, and the intermediate semiconductor layers having band gaps transitioning from the smallest to the largest, a second layer overlying the semiconductor layers and formed of delta doped silicon, an n-cap layer formed on the second delta doped layer, and a metal layer formed on the n-cap layer and serving to reflect light into the semiconductor.

Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Abstract: The present invention is related to a method for forming a CMOS image sensor device. A CMOS image device has a first MOS device acting as a source follower of an active pixel, a second MOS device acting as a row select of the active pixel. An amorphous silicon layer acts as a photo-diode area for collecting incident light over the first MOS device and the second MOS device. The amorphous silicon layer has both N-type and P-type dopants.

Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed flexible planar interface material contacting the deformable material.

Abstract: By using wafer fusion, various structures for photodetectors and photodetectors integrated with other electronics can be achieved. The use of silicon as a multiplication region and III-V compounds as an absorption region create photodetectors that are highly efficient and tailored to specific applications. Devices responsive to different regions of the optical spectrum, or that have higher efficiencies are created.

Abstract: The quantum efficiency of a photodiode is substantially increased by forming the photodiode on a heavily-doped layer of semiconductor material which, in turn, is formed on a semiconductor substrate. The heavily-doped layer of semiconductor material tends to repel information carriers in the photodiode from being lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photodiode. In addition, the red and blue photoresponses are balanced by adjusting the depth of the photodiode.

Abstract: A fabrication process for a semiconductor device including a plurality of semiconductor layers, the plurality of semiconductor layers including at least a nitrogen-containing alloy semiconductor AlaGabIn1-a-bNxPyAszSb1-x-y-z (0≦a≦1, 0≦b≦1, 0<x<1, 0≦y<1, 0≦z<1), and a method of making the semiconductor device and apparatus. For at least two semiconductor layers out of the plurality of semiconductor layers, a value of lattice strain of said at least two semiconductor layers is set at less than a critical strain at which misfit dislocations are generated at an interface between said two adjacent semiconductor layers.