Abstract: A method for forming a pattern in a semiconductor device is disclosed which can increase the contact area between a photoresist and an anti-reflective film by performing an etching process on the anti-reflective film in a process of forming a photoresist pattern for a semiconductor device so as to form fine irregularities, thereby preventing collapse of a photoresist pattern. The disclosed method includes (a) forming an organic anti-reflective film by coating an organic anti-reflective coating composition onto an upper portion of a layer to be etched, and performing a baking process thereto; (b) forming fine irregularities on the organic anti-reflective film by performing an etching process on the formed organic anti-reflective film; and (c) forming a photoresist pattern by coating a photoresist on the upper portion of the organic anti-reflective film, exposing the photoresist and then developing the same.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

Abstract: A split-gate semiconductor device is fabricated by forming floating gates on the sidewalls of the control gates of transistors, then using a bottom anti-reflective coating as a mask while removing unnecessary floating gates, preferably by an isotropic dry etching process that removes floating-gate material from the sidewalls faster than it removes dielectric material from the upper parts of the control gates. Alternatively, control gate structures are formed, floating-gate material is deposited, removed, then deposited again to form floating gates on the sidewalls of the control gate structures, and the central parts of the control gate structures are etched to leave control gates with floating gates on one sidewall each.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

Abstract: A method for forming patterns of a semiconductor device is disclosed which inhibits collapse of photoresist patterns in photoresist pattern-forming processes of the semiconductor device by forming micro-bends in an anti-reflective film to increase the contact area between a photoresist and the anti-reflective film and, simultaneously prevents critical dimension (CD) alteration of the photoresist pattern by creating micro-bends and double-laminating of anti-reflective films with different refractive indices and light-absorbencies.

Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.

Abstract: A method of micro-structuring a surface of a sample of ferroelectric material, the method comprising: (a) taking a sample of ferroelectric material having a −z face which is to be etched; (b) illuminating the −z face with ultraviolet light to define illuminated and unilluminated parts of the surface; and (c) immersing the −z face in an etchant to selectively remove the unilluminated parts of the −z face at a greater rate than the illuminated parts. The method can be carried out using pulsed ultraviolet light to etch lithium niobate crystals cut for etching on the −z face, and may further be combined with ablation to produce multi-level surface structures.

Abstract: An exemplary method of forming trench lines includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

Abstract: A method passivates a surface of a semiconductor structure. The method provides III-V semiconductor material having a surface to be passivated. Upon the surface of the III-V semiconductor material to be passivated an oxide layer is formed. Thereafter, the surface of the III-V semiconductor material having the oxide layer is passivated, without desorption of the oxide layer and in a vacuum of 2×10−6 Torr, with a material having the ability to intermix with the oxide layer so as to exchange oxygen, passivation layer material, and III-V semiconductor material therebetween to form graded layers of oxidized III-V and passivation material.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: Disclosed is a system for fabricating an integrated circuit capacitor (100). An electrode layer (102) is formed in the integrated circuit. An anti-reflective coating (108) is deposited over the electrode layer (102). An electrode top plate (104) is formed over the anti-reflective coating (108).

Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

Abstract: A method for pitch reduction is disclosed. The method can form a pattern with a pitch ⅓ the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processes, and conventional deposition processes. By choosing appropriate layers to be deposited and etched, the pattern can be an etching mask or it can be a device structure itself.

Abstract: A method of the invention comprises forming a partial absorber layer (PAL) over at least one integrated transistor device formed on a semiconductor substrate, and exposing the PAL to radiant energy. A first portion of the radiant energy passes through the PAL and is absorbed in the source and drain regions adjacent a gate region of the integrated transistor device and in the semiconductor substrate underneath the field isolation regions of the integrated device. A second portion of the radiant energy is absorbed by the PAL and is thermally conducted from the PAL to the source and drain regions. The first and second portions of the radiant energy are sufficient to melt the source and drain regions to anneal the junctions of the integrated device.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.

Abstract: Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.

Abstract: A method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects bottom anti-reflective coating process is performed, wherein the no hole defect bottom anti-reflective coating process is selected from the group consisting of dehydration baking, hydrophobic solvent treatment, and steady baking. Finally, a bottom anti-reflective coating is formed over the polysilicon layer.

Abstract: In the fabrication of integrated circuits containing multilevel structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers, superior adhesion between the FSG and aluminum-copper-TiN is achieved by subjecting the aluminum-copper-TiN layer to a plasma containing N2 and H2 or N2 and NH3 prior to deposition of the FSG layer. It is believed that the plasma treatment converts unreacted Ti within the TiN layer to TiN and, also, stuffs grain boundaries within the TiN layer with N2. The result is a void-free TiN layer which is impervious to F atoms residing in the FSG layer.

Abstract: A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

Abstract: A resist layer is deposited atop a substrate and is patterned to expose portions of a substrate. A hardmask layer is deposited atop the patterned resist layer and atop the exposed portions of the substrate. The patterned resist layer is removed so that only a portion of the hardmask layer that is atop the substrate remains.

Abstract: A method for etching and removing an anti-reflective coating from a substrate. The method comprises providing a substrate supporting a conductive layer (a tungsten-silicide layer) having an anti-reflective coating (e.g., a dielectric anti-reflective coating) disposed thereon. The anti-reflective coating is etched with an etchant gas consisting of NF3 and Cl2 to break through and to remove at least a portion of the anti-reflective coating to expose at least part of the conductive layer. The conductive layer is subsequently etched with the etchant gas to produce an anti-reflective coating gate structure which is used in semiconductor integrated circuits containing transistors.

Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

Abstract: Disclosed is a method for forming contact by using the ArF lithography technology using a low-k dielectric sacrifice layer. The method comprises forming a layer to be etched on the semiconductor substrate, successively forming a low-k dielectric sacrifice layer and a hard mask on the etched layer, forming an anti-reflective layer and a photoresist pattern on the hard mask by using ArF lithography technology, selectively etching the anti-reflective layer and the hard mask and simultaneously removing the photoresist pattern when etching the hard mask, forming a contact hole exposing a surface of the semiconductor substrate by etching the low-k dielectric sacrifice layer and the layer by using the hard mask as a mask and removing the hard mask and the low-k dielectric sacrifice layer.

Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

Abstract: A method for etching and removing an anti-reflective coating from a substrate. The method comprises providing a substrate supporting a conductive layer (a tungsten-silicide layer) having an anti-reflective coating (e.g., a dielectric anti-reflective coating) disposed thereon. The anti-reflective coating is etched with an etchant gas consisting of NF3 and Cl2 to break through and to remove at least a portion of the anti-reflective coating to expose at least part of the conductive layer. The conductive layer is subsequently etched with the etchant gas to produce an anti-reflective coating gate structure which is used in semiconductor integrated circuits containing transistors.

Abstract: A method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects bottom anti-reflective coating process is performed, wherein the no hole defect bottom anti-reflective coating process is selected from the group consisting of dehydration baking, hydrophobic solvent treatment, and steady baking. Finally, a bottom anti-reflective coating is formed over the polysilicon layer.

Abstract: After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (18) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20a to 20c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20a to 20c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20a to 20c) and patterns (18a to 18c) of the second antireflection coating film (18) as masks.

Abstract: The contour of a resist pattern is retreated at a site where a part of the place where a gate wiring is to be disposed, which part is located on an active region, and the place where the resist pattern made of a resist film is to be disposed are near to each other by a predetermined distance or less.

Abstract: A circuit device incorporating an anti-reflective coating and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes forming a film on the substrate and forming an anti-reflective coating on the film by first forming a silicon-rich nitride film on the film in a first plasma atmosphere and thereafter exposing the silicon-rich nitride film in-situ to a second plasma atmosphere containing oxygen to convert an upper portion of the silicon-rich nitride film to silicon oxynitride. Variability in the optical properties of the anti-reflective coating substantially reduced, resulting in improved UV lithographic patterning of etch masking.

Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defmed by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

Abstract: A method of forming an anti-reflective coating is described. A film is formed on a substrate. A first layer of an anti-reflective coating layer Is deposited on the film by chemical vapor deposition using a canrier gas, an organic halide gas and a hydrogen halide gas as gas sources. A second layer of the anti-reflective coating layer is formed on the first layer of the anti-reflective coating layer by chemical vapor deposition using a carrier gas and an organic halide gas as gas sources. A photoresist layer is formed on the second layer of the anti-reflective coating layer.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A germanium and silicon alloy is employed as an antireflective coating material for use in active area lithography and gate area lithography steps in the formation of a semiconductor integrated circuit. A layer composed of an alloy of germanium-silicon is deposited over an active area nitride layer or over a gate area nitride layer, and a photoresist layer is then formed on the germanium-silicon alloy layer. The photoresist layer is than exposed and developed. During exposure, the germanium-silicon alloy layer substantially reduces reflection from the underlying nitride layer, thereby relieving the dependency of exposure energy and resulting line width on the underlying nitride layer thickness.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: An anti-reflection film of an organic compound is formed on a substrate. The anti-reflection film is weakened by carrying out plasma processing on the anti-reflection film, and then, a resist film is formed on the weakened anti-reflection film. The resist film is subjected to pattern exposure and development so as to form a resist pattern from the resist film. The anti-reflection film is dry etched by using the resist pattern as a mask, so as to pattern the anti-reflection film.

Abstract: A method for forming a resist pattern includes the steps of: forming an underlayer transparent film on a semiconductor substrate; forming a resist film on the transparent film to a thickness set to be m·&lgr;/2n2, where &lgr; is an exposure wavelength, n2 is a refractive index of the resist film, and m is an integer from 5 to 30; applying a water-soluble antireflection film on the resist film to a thickness set to be &lgr;/4n1, where n1 is a refractive index of the antireflection film; and exposing the resist film from above the antireflection film by a beam having a wavelength &lgr; and developing the resist film as well as removing the antireflection film.

Abstract: The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process. The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack.

Abstract: A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.

Abstract: A method of manufacturing a semiconductor device by forming layers of materials on a semiconductor substrate and utilizing a series of etch chemistries to remove portions of the layers of materials to form a metal stack. A patterned layer of photoresist determines the portions of the layers that will be etched. An etch process etches a hardmask material, a breakthrough etch process etches an antireflection layer, a conventional main etch process etches approximately 80 percent of the metal film, a first overetch process for a first selected period of time and a second overetch process for a second selected period of time provides a metal film stack having straight profiles and smooth sidewalls.

Abstract: A silicon film is formed on a semiconductor substrate, and a silicon oxide film and a polycrystalline silicon film are formed thereon. Patterning is performed for the polycrystalline silicon film to form a capacitive upper electrode. Then, patterning is performed for the silicon oxide film to form a capacitive dielectric film below the capacitive upper electrode, the capacitive dielectric film having a shape larger than that of the capacitive upper electrode. Subsequently, an anti-reflection coating film (silicon nitride film which is silicon-rich) is formed on a full surface. Then, patterning is performed for the silicon film by means of photolithography to form a capacitive lower electrode and a gate electrode of a transistor.

Abstract: In a process and apparatus for coating the front and/or rear facets of semiconductor laser diodes with antireflection layers of minimal reflectivity, the coating material is deposited on the facets while at least one laser parameter is monitored, in-situ, for determining the coating thickness of the individual antireflection layers resulting in the minimum reflectivity of the coating and the respective coating procedure is terminated when the laser parameter indicates that such coating thickness has been reached.

Abstract: After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (16) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20a to 20c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20a to 20c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20a to 20c) and patterns (18a to 18c) of the second antireflection coating film (18) as masks.

Abstract: A process for the formation of a wiring pattern, which includes the steps of: exposing a resist through a photomask, the photomask having a pattern whose line width is equal to or less than a resolution limit; and developing the exposed resist to form a resist pattern having groove depressions on the surface thereof, the depressions not reaching the back of the resist pattern. The resist may be a positive resist in which case the resist pattern is formed on an underplate feed film; a plating metal is precipitated on the feed film in a region not covered by the resist pattern; the resist pattern is stripped after the precipitation; and the feed film is selectively removed in a region not covered by the plating metal. Alternatively, the resist may be a negative resist in which case the resist pattern is formed on a substrate; a metallic material is deposited on the resist pattern and the substrate; and the resist is stripped from the substrate to remove the overlying metallic material.

Abstract: Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in the same tool.

Abstract: Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber 34 is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber 40 is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber 38 is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of −50° C. to 150° C.

Abstract: In a process for fabricating a semiconductor device, an DLC (diamond like carbon) film is formed on a principal surface of a semiconductor substrate, and an ashing protecting film is formed on the DLC film for protecting the DLC film from an ashing. A hard mask film having a resisting property against an etching agent for the ashing protecting film and the DLC film, is formed on the ashing protecting film. The hard mask film is patterned using a patterned photo resist film as a mask, and then, the patterned photo resist film is removed by an oxygen ashing. The ashing protecting film and the DLC film is patterned using the patterned hard mask film as a mask, and a trench is formed in the principal surface of the semiconductor substrate using the patterned hard mask film, ashing protecting film and DLC film as a mask. An insulator film is deposited on the whole surface to completely fill up the trench.