Abstract: The method includes forming a gate oxide on a substrate. A stacked-amorphous-silicon (SAS) layer is then formed on the gate oxide. An anti-reflective coating (ARC) layer is formed on the SAS layer. Next, a gate structure is patterned by etching. A silicon oxynitride layer is formed on the substrate, and covered the gate structure. A BSG sidewall spacers are formed on the side walls of the gate structure. A selective epitaxial silicon is grown on the substrate by using ultra high vacuum chemical vapor deposition. Then, an ARC layer is removed to expose the top of the SAS layer. Then, a blanket ion implantation is carried out to implant p type dopant into the SAS layer, the epitaxial silicon and silicon substrate. A SALICIDE layer, a polycide layer are respectively formed on the SAS layer and the epitaxial silicon. Further, the extended source and drain are formed in the step. A thick oxide layer is formed over the substrate and gate structure for isolation. Then, contact holes are generated in the oxide layer.

Abstract: A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.

Abstract: A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

Abstract: Disclosed is an inventive multiple-chemistry etching method suited for etching through selected portions of layers in a layer stack in a plasma processing chamber. The layer stack preferably includes at least an anti-reflective layer and a metallization layer disposed below the anti-reflective layer. The method includes a first etching step where the anti-reflective layer of the layer stack is at least partially etched with a first chemistry, the first chemistry comprising an etchant chemical and a polymer-forming chemical. Once the first etching step is complete, the method proceeds to a second etching step where at least part of the metallization layer of the layer stack is etched with a second chemistry different from the first chemistry.

Abstract: According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having the same shape as that of the contact hole is formed by using a reflection prevention film containing nitrogen atoms, the etching stopper film and the reflection prevention film in a contact hole formation region which contain nitrogen atoms and have equal selectivity ratios under a predetermined condition are simultaneously removed by etching, so that a semiconductor device having stable performance and simple manufacturing steps can be obtained.

Abstract: In a method of manufacturing a semiconductor device, an operating layer and a light-shielding film are sequentially formed to form a recess step on a semiconductor substrate. A first photoresist film is formed on the light-shielding film. The light-shielding film is patterned using the photoresist film as a mask to form a gate electrode formation opening portion. A metal film is formed on the entire surface including the opening portion. The metal film is selectively etched using, as a mask, a second photoresist film formed on the metal film, thereby forming a gate electrode having a T shape in the longitudinal section. The second photoresist film is removed. The light-shielding film is removed.

Abstract: In a method of building up wiring with a protective insulator film as a mask, a precise and elaborate wiring pattern is formed. The method comprises a process of making up a conductive material film on the surface of a semiconductor substrate, a process of depositing a inorganic insulator film consisting of a semiconductor oxide film and a semiconductor nitride film in layers on the conductive material film, a process of making up an antireflection film for an irradiation light for sensitizing used in photo lithography which patterns photosensitivity resist film, a process of making up the photosensitivity resist film on the antireflection film to pattern in a predetermined shape, and a process of applying dry etching to the conductive material film and the antireflection film with the inorganic insulator film as a mask.

Abstract: The present invention relates to a method of a sequencial WSi/.alpha.-Si sputtering process, more particularly to a method of in-situ wafer cooling for a sequencial WSi/.alpha.-Si sputtering process. A sputtering process of WSi and a sputtering process of .alpha.-Si are finished in a multi-chamber sputtering apparatus according to the invention; meanwhile, a wafer is cooled down by bolwing of inert gas before a process of sputtering .alpha.-Si starts. Thus, compared to traditional art of finishing WSi/.alpha.-Si sputtering in two apparatus, partial time of vacuuming and venting required in a sputtering process is saved according to the invention, thereby, shortening the production cycle time, reducing the possibility of wafer contamination, and suppressing the fabricating cost.

Abstract: A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

Abstract: Germanium is employed as an antireflective coating material for use in active area lithography and gate area lithography steps in the formation of a semiconductor integrated circuit. A germanium layer is deposited over an active area nitride layer or over a gate area nitride layer, and a photoresist layer is then formed on the germanium layer. The photoresist layer is than exposed and developed. During exposure, the germanium layer substantially reduces reflection from the underlying nitride layer, thereby relieving the dependency of exposure energy and resulting line width on the underlying nitride layer thickness. Germanium-silicon may also be employed as the antireflective layer.

Abstract: A thick layer formed of aSi or aSi/aSiN is used as an antireflection layer (3) in the lithographic structuring of layers (2) on a semiconductor substrate (1). A reflection suppression is based on absorption in the aSi layer and on interference in the aSiN layer. An optical decoupling of the background is achieved, with the result that the antireflection layer can be used universally.

Abstract: According to this invention, an etching stopper film constituted by a silicon nitride film is stacked on an insulating film constituted by a silicon oxide film for protecting a wiring to prevent damage to the wiring caused by anisotropic dry etching for forming a contact hole. A resist pattern having the same shape as that of the contact hole is formed by using a reflection prevention film containing nitrogen atoms, the etching stopper film and the reflection prevention film in a contact hole formation region which contain nitrogen atoms and have equal selectivity ratios under a predetermined condition are simultaneously removed by etching, so that a semiconductor device having stable performance and simple manufacturing steps can be obtained.

Abstract: A process is provided for forming a hard mask over an aluminum-containing layer for patterning and etching the aluminum-containing layer to define interconnects. The process comprises depositing the material comprising the hard mask at a temperature that is within the range of about 100.degree. C. below the sputtering temperature of the aluminum-containing metal and the sputtering temperature of the aluminum-containing metal.

Abstract: A pattern forming method having a step of forming an amorphous carbon film on a patterning layer formed on a substrate, a step of forming a photoresist film on the amorphous carbon film, a step of selectively exposing and developing the photoresist film to form a photoresist pattern, and a step of successively dry-etching the amorphous carbon film and the patterning layer by using the photoresist film as an etching mask. Desired optical constants of an amorphous carbon film formed by sputtering can be obtained by controlling a substrate temperature and other parameters.