Utilizing Varying Dielectric Thickness Patents (Class 438/981)
  • Patent number: 9034709
    Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: May 19, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Shogo Katsuki, Toshiro Sakamoto
  • Patent number: 8697530
    Abstract: By modifying the dielectric liner for a spacer structure so as to exhibit an enhanced diffusion blocking characteristic, for instance by incorporating nitrogen, the out-diffusion of P-dopants, such as boron, into the dielectric material may be significantly reduced. Consequently, transistor performance, especially of P-type transistors, may be significantly enhanced while nevertheless a high degree of compatibility with conventional techniques may be maintained.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ekkehard Pruefer, Ralf Van Bentum, Klaus Hempel, Stephan Kruegel
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Patent number: 8685820
    Abstract: The present disclosure provides for multiple gate dielectric semiconductor structures and methods of forming such structures. In one embodiment, a method of forming a semiconductor structure includes providing a substrate including a pixel array region, an input/output (I/O) region, and a core region. The method further includes forming a first gate dielectric layer over the pixel array region, forming a second gate dielectric layer over the I/O region, and forming a third gate dielectric layer over the core region, wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer are each formed to be comprised of a different material and to have a different thickness.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Hui Tseng, Dun-Nian Yaung, Jen-Cheng Liu, Wen-I Hsu, Min-Feng Kao
  • Patent number: 8642374
    Abstract: An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 4, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jeong-Ho Lyu, Sohei Manabe, Howard Rhodes
  • Patent number: 8633118
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 21, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8609496
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongyean Oh, Woon-kyung Lee
  • Patent number: 8492851
    Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 23, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Pai-Hung Pan
  • Patent number: 8329525
    Abstract: At least three metal-oxide semiconductor transistors with different threshold voltages are formed in and above corresponding first, second and third parts of a semiconductor substrate. The second transistor has a lower threshold voltage than the second transistor, and the third transistor has a lower threshold voltage than the second transistor. The gate oxide layers for the three transistors are formed as follows: a first oxide layer having a first thickness is formed above the first, second and third parts. The first oxide layer above the second part is etched and a second oxide layer having a second thickness smaller than the first thickness is formed. The first oxide layer above the third part is etched and a third oxide layer having a third thickness smaller than the second thickness is formed. The second and the third oxide layers are then nitrided to form first and second oxy-nitride layers.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: December 11, 2012
    Assignee: STMicroelectronics, Inc.
    Inventor: Franck Arnaud
  • Patent number: 8232199
    Abstract: A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Song, Byung-Goo Jeon
  • Patent number: 8187961
    Abstract: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Eduard Albert Cartier, Vijay Narayanan, Vamsi Paruchuri
  • Patent number: 8187942
    Abstract: A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step of selectively removing a portion of the first insulation layer formed the second region of the semiconductor substrate. The removal of the portion of the first insulation layer is conducted using an etching solution comprising propylene glycol, HF and amine. The method also includes a step of forming a second insulation layer on the first insulation layer in the first region and on the semiconductor substrate in the second region.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Bang Lee
  • Patent number: 8143148
    Abstract: A method for forming a laser diode structure. The method includes providing a laser diode material having a surface region. A multilayer dielectric mask structure comprising alternating first and second dielectric layers is formed overlying the surface region. The method forms a laser diode structure using the multilayer dielectric mask structure as a mask. The method selectively removes a portion of the first dielectric layer to form one or more undercut regions between the second dielectric layers. A passivation layer overlies the multilayer dielectric mask structure and the undercut region remained intact. The dielectric mask structure is selectively removed, exposing a top surface region of the laser diode structure. A contact structure is formed overlying at least the exposed top surface region.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: March 27, 2012
    Assignee: Soraa, Inc.
    Inventors: James W. Raring, Daniel F. Feezell, Nick Pfister
  • Patent number: 8084328
    Abstract: A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: December 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Pi-Tsung Chen, Ying-Tsung Chen
  • Patent number: 8008150
    Abstract: A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending through the first conductive layer and the first insulating layer to define an active region in the memory cell region between the trench isolation regions, and selectively removing the first conductive layer and the first insulating layer from the memory cell region of the substrate to expose a surface of the active region between the trench isolation regions.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hoon Kim
  • Patent number: 7964917
    Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventor: Susumu Akamatsu
  • Patent number: 7879737
    Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: February 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
  • Patent number: 7863153
    Abstract: An efficient method is disclosed for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process). The method comprises (1) forming a first portion of the field oxide with a first field oxide profile (e.g., an abrupt bird's beak profile) during a field oxide oxidation process, and (2) forming a second portion of the field oxide with a second field oxide profile (e.g., a graded bird's beak profile) during the field oxide oxidation process. A graded bird's beak profile enables higher breakdown voltages. An abrupt bird's beak profile enables higher packing densities. The method gives an integrated circuit designer the flexibility to create an appropriate field oxide profile at a desired location.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: January 4, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Richard W. Foote, Jr.
  • Patent number: 7851304
    Abstract: Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woon-Kyung Lee, Jeong-Hyuk Choi
  • Patent number: 7834417
    Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) includes one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) is defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Robert W. Baird, Gordon P. Lee, Jiang-Kai Zuo
  • Patent number: 7834389
    Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: November 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Yi-Chen Huang, Jim Cy Huang, Weng Chang, Hun-Jan Tao
  • Patent number: 7799649
    Abstract: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: September 21, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Reima Tapani Laaksonen
  • Patent number: 7785966
    Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: August 31, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chang Liu, Wen-Ting Chu, Chi-Hsin Lo, Chia-Shiung Tsai
  • Patent number: 7781289
    Abstract: A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of the substrate associated with the control capacitor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, P-well, and N-well implantations). These portions of the substrate may have faster oxidation rates than other portions of the substrate, allowing a thicker front-end gate oxide to be formed over these portions of the substrate. In addition, a rapid thermal process anneal can be performed, which may reduce defects in the front-end gate oxide and increase its quality without having much impact on the oxide over the other portions of the substrate.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: August 24, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Thanas Budri, Jiankang Bu
  • Patent number: 7776761
    Abstract: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Sik Park
  • Patent number: 7772646
    Abstract: There is a method of manufacturing a semiconductor device with a semiconductor body comprising a semiconductor substrate and a semiconductor region which are separated from each other with an electrically insulating layer which includes a first and a second sub-layer which, viewed in projection, are adjacent to one another, wherein the first sub-layer has a smaller thickness than the second sub-layer, and wherein, in a first sub-region of the semiconductor region lying above the first sub-layer, at least one digital semiconductor element is formed and, in a second sub-region of the semiconductor region lying above the second sub-layer, at least one analog semiconductor element is formed. According to an example embodiment, the second sub-layer is formed in that the lower border thereof is recessed in the semiconductor body in relation to the lower border of the first sub-layer Fully depleted SOI devices are thus formed.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: August 10, 2010
    Assignee: NXP B.V.
    Inventors: Josine Johanna Gerarda Petra Loo, Vincent Charles Venezia, Youri Ponomarev
  • Patent number: 7767562
    Abstract: A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: August 3, 2010
    Assignee: Qimonda AG
    Inventors: Helmut Horst Tews, Jochen Beintner
  • Patent number: 7759238
    Abstract: The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Tai Chiang Chen, Xin Wang
  • Patent number: 7759263
    Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
  • Patent number: 7700417
    Abstract: A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60?), one (60) forming the reference current (RC) side (601) and the other (60?) forming the mirror current side (602) of the CCM (74). The gates (65, 65?) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66?, 66?) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601).
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Geoffrey W. Perkins, Jiang-Kai Zuo
  • Patent number: 7642146
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Mark Robert Visokay, Luigi Colombo
  • Patent number: 7605016
    Abstract: Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: October 20, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Dae Hong Min
  • Patent number: 7585736
    Abstract: A method of manufacturing a semiconductor device includes steps (a) to (d). The step (a) is a step of forming a first insulating film and a nitride film on a semiconductor substrate in this order. The step (b) is a step of removing said first insulating film and said nitride film in a first region while leaving said first insulating film and said nitride film in a second region. The step (c) is a step of forming a second insulating film on said semiconductor substrate in said first region. Here, a thickness of said second insulating film is different from that of said first insulating film. A third insulating film is formed on said nitride film in said second region along with the formation of said second insulating film. The step (d) is a step of removing said third insulating film and said nitride film in said second region.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: September 8, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Yoichi Fukushima
  • Patent number: 7563679
    Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 21, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Graham R. Wolstenholme, Mark A. Helm
  • Patent number: 7553704
    Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 30, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Robert W. Baird, Jiang-Kai Zuo, Gordon P. Lee
  • Patent number: 7550346
    Abstract: Disclosed is a method for forming a gate dielectric in a semiconductor device. The present method includes forming a first dielectric layer on a semiconductor substrate; removing a portion of the first dielectric layer to expose a portion of the substrate; forming a nitride layer on the exposed portion of the substrate and the first dielectric layer; forming a transition metal layer on the nitride layer; and oxidizing the transition metal layer to form a transition metal oxide layer.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: June 23, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jeong Ho Park
  • Patent number: 7550349
    Abstract: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 23, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 7537998
    Abstract: Forming salicide in a semiconductor device includes the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: May 26, 2009
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Joon Hyeon Lee, Woon Yong Kim
  • Patent number: 7531438
    Abstract: A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: May 12, 2009
    Assignee: ProMOS Technologies Inc.
    Inventors: Jih-Wen Chou, Chih-Hsun Chu, Hsiu-Chuan Shu
  • Patent number: 7528041
    Abstract: A method of manufacturing a semiconductor device, including including preparing a semiconductor substrate having first to fourth active regions and field oxides, the third and fourth active regions sandwiching the second active region, and the field oxides isolating the first to fourth active regions; forming a protective film having openings over the second active region and the field oxide which adjoins the second active region, over the semiconductor substrate; forming the first gate insulator on the second active region; removing the protective film; forming second gate insulators thinner than the first gate insulators on the first, third and fourth active regions, respectively; forming gate electrodes on the first gate insulator over the first active region and on the second gate insulator over the second active region; and forming a pair of first doped regions in the first active region and second doped regions in the third and fourth active regions.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: May 5, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Toshihiro Honma
  • Patent number: 7528015
    Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrice M. Parris, Weize Chen, John M. McKenna, Jennifer H. Morrison, Moaniss Zitouni, Richard J. De Souza
  • Patent number: 7524720
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined, forming a polysilicon on the gate oxide layer, selectively removing the polysilicon on the PMOS region, selectively removing the gate oxide layer on the PMOS region, forming a pure SiO2 layer on the semiconductor substrate of the PMOS region, removing a surface oxide layer on the remaining polysilicon generated when the pure SiO2 layer is formed, and forming a gate electrode polysilicon on the entire surface including the remaining polysilicon.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: April 28, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Young Seong Lee
  • Patent number: 7504291
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7504308
    Abstract: A method of dual bird's beak LOCOS may reduce a design rule for a more cost-effective logic device formation. The method may also form a LOCOS layer having a smooth bird's beak to fabricate a stable high-voltage device. The method includes steps of defining a low-voltage device area for a logic device and a high-voltage device area for a high-voltage device, forming a first pad layer in the low-voltage device area and a second pad layer in the high-voltage device area, the first pad layer being thinner than the second pad layer, and forming LOCOS type device isolation layers having bird's beaks differing in size in each of the low-voltage device area and the high-voltage device area, by oxidizing a portion of the semiconductor substrate exposed by a hard mask.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: March 17, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chang Nam Kim
  • Patent number: 7482623
    Abstract: An organic semiconductor device includes a substrate, a gate electrode formed directly on the substrate , gate insulating film formed directly on the gate electrode, a source electrode and a drain electrode formed directly on the gate insulating film, an organic semiconductor layer formed directly on the source electrode and the drain electrode, and a voltage control layer disposed directly between the gate insulating film and the organic semiconductor layer and directly contacting the source electrode and the drain electrode, wherein the voltage control layer gives an ambipolar characteristic to the organic semiconductor layer.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: January 27, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takao Nishikawa, Yoshihiro Iwasa, Shin-ichiro Kobayashi, Taishi Takenobu
  • Patent number: 7473625
    Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: January 6, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Mu-Yi Liu, Chia-Lun Hsu, Ichen Yang, Kuan-Po Chen, Tao-Cheng Lu
  • Patent number: 7468300
    Abstract: A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: December 23, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yong Keon Choi
  • Patent number: 7435651
    Abstract: The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160 over a substrate 115, subjecting the first gate dielectric layer 160 to a first nitridation process, forming a second gate dielectric layer 165 over the substrate 115 and having a thickness less than a thickness of the first gate dielectric layer 160, and subjecting the first and second gate dielectric layers 160,165 to a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics device 100 fabricated in accordance with the method.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: October 14, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Ajith Varghese, Reima T. Laaksonen, Terrence J. Riley
  • Patent number: 7429514
    Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: September 30, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Paul J. Rudeck, Don C. Powell
  • Patent number: RE44156
    Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as ?6V˜12V, ?12V˜6V, ?9V˜9V etc.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: April 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Rong-Ching Chen, Ching-Chun Huang, Jy-Hwang Lin