Utilizing Varying Dielectric Thickness Patents (Class 438/981)
  • Patent number: 6268251
    Abstract: A method of fabricating multiple thickness gate oxide layers, comprising the following steps. A silicon substrate having at least a first and second gate oxide region is provided. A first gate oxide layer is formed over the silicon substrate within the first gate oxide region. The first gate oxide layer having a first predetermined thickness. A first layer of polysilicon is deposited and planarized over the first gate oxide layer. The first planarized layer of polysilicon and the first gate oxide layer are masked and etched within the second gate oxide region, exposing the silicon substrate within the second gate oxide region. A second gate oxide layer is formed over the exposed silicon substrate within the second gate oxide region. The second gate oxide layer having a second predetermined thickness. A second layer of polysilicon is selectively deposited over the second gate oxide layer. The first and second layers of polysilicon are planarized to a uniform thickness.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: July 31, 2001
    Assignee: Chartered Semiconductor Manufacturing Inc.
    Inventors: Dong Zhong, Jia Zhen Zheng
  • Patent number: 6265267
    Abstract: A method of fabricating a semiconductor device with various thicknesses of the gate oxide layers is described, which method is applicable to a substrate having a first region and a second region, wherein the first region has a first conductive layer to isolate the first gate oxide layer from the substrate. Thereafter, a first oxide layer/nitride layer is formed on the first conductive layer, followed by forming a doped polysilicon layer on the first oxide layer/nitride layer, wherein the doped polysilicon layer is not formed in the second region. Subsequently, a second gate oxide layer is formed on the substrate of the second region, whereas a first oxide layer/nitride layer/second oxide layer is concurrently converted from the oxide layer/nitride layer/doped polysilicon layer. A defined second conductive layer is then formed on the first oxide layer/nitride layer/second oxide layer and the second gate oxide layer.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: July 24, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Chih-Jen Huang
  • Publication number: 20010008808
    Abstract: The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.
    Type: Application
    Filed: February 8, 2001
    Publication date: July 19, 2001
    Inventor: Fernando Gonzalez
  • Patent number: 6261978
    Abstract: A first dielectric layer (22) is formed over a semiconductor device substrate. A resist layer (32) is then patterned to expose portions of the first dielectric layer (22). Portions of the first dielectric layer (22) are removed to expose portions of the semiconductor device substrate (42). The resist layer (32) is then removed. The semiconductor device substrate is cleaned without using a fluorine-containing solution and a second dielectric layer (62) is formed overlying the semiconductor device substrate.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: July 17, 2001
    Assignee: Motorola, Inc.
    Inventors: Ping Chen, Navakanta Bhat, Paul G. Y. Tsui, Daniel T. K. Pham
  • Patent number: 6261972
    Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: July 17, 2001
    Assignees: Infineon Technologies AG, International Business Machines
    Inventors: Helmut Horst Tews, Mary Weybright, Stephan Kudelka, Oleg Gluschenkov, Suri Hegde
  • Patent number: 6258673
    Abstract: A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the stan
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Houlihan, Liang-Kai Han, Dale W. Martin
  • Patent number: 6248618
    Abstract: A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: June 19, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shyue Fong Quek, Ting Cheong Ang, Puay Ing Ong, Sang Yee Loong
  • Patent number: 6235585
    Abstract: Methods for fabricating a flash memory device which improves both charge retaining characteristics and characteristics of a gate insulating film are disclosed.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: May 22, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Sung Chul Lee, Jae Seung Choi
  • Patent number: 6232658
    Abstract: The invention comprises a process for forming a dielectric film having a compressive stress exhibited in the layers deposited onto an integrated circuit structure. This process includes depositing a first thin layer of dielectric material onto an integrated circuit structure, then exposing the integrated circuit structure to an elevated temperature. Then a second thin layer of dielectric material is deposited immediately overtop of the first thin layer of dielectric material, and then the integrated circuit structure is again exposed to an elevated temperature. The process is carried out to insure that the composite layer comprising the first and second deposited thin dielectric layers, after heat treatment, exhibits a residual stress which is compressive.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: May 15, 2001
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Joe W. Zhao
  • Patent number: 6232244
    Abstract: Dual gate oxide layer thicknesses are achieved by depositing a thin blocking layer on active regions of a semiconductor substrate, such as silicon nitride, oxynitride, or oxide. Selected active regions are nitridated through a patterned photoresist mask formed thereon. The blocking layer protects the substrate from the photoresist mask and enables nitriding, as by ion implantation, plasma exposure, or rapid thermal annealing.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: May 15, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Effiong E. Ibok
  • Patent number: 6228782
    Abstract: Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: May 8, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hao Fang, Massaki Higashitani, Narbeh Derhacobian
  • Patent number: 6228721
    Abstract: For fabricating a metal oxide structure on a semiconductor substrate, an active device area surrounded by at least one STI (shallow trench isolation) structure is formed in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal. An opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the layer of metal that is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area where the layer of metal is exposed.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: May 8, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Yu
  • Patent number: 6225661
    Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: May 1, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Judy Xilin An, Bin Yu, Ming-Ren Lin
  • Patent number: 6225163
    Abstract: A process for forming high quality gate silicon dioxide layers of multiple thicknesses. The process includes steps of first providing a semiconductor substrate (e.g., a silicon wafer) with at least a first active area, a second active area and an electrical isolation region separating the first and second active area, followed by the formation of a first gate silicon dioxide layer of a predetermined thickness (typically less than 100 angstroms) on the first and second active areas. A first silicon layer (e.g., a polysilicon or amorphous silicon layer) is then deposited on the first gate silicon dioxide layer and the electrical isolation region. Next, the first silicon layer is patterned using, for example, photolithographic and etching techniques, to form a patterned first silicon layer and to expose a portion of the first gate silicon dioxide layer that was grown on the second active area.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: May 1, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Albert Bergemont
  • Publication number: 20010000247
    Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are flown through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are flown through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the f
    Type: Application
    Filed: December 1, 2000
    Publication date: April 12, 2001
    Applicant: FUJITSU LIMITED, ADVANCED MICRO DEVICES, INC.
    Inventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
  • Patent number: 6207588
    Abstract: A method for forming a dual oxide layer on a silicon substrate provides that layer having varying thicknesses by using a damage layer formed on the silicon substrate, or a silicon nitride layer deposited on the silicon substrate. The damage layer is formed on the silicon substrate by dry etching a designated part of the silicon substrate, and the dual oxide layer is formed by using the properties of SiO2 by which the oxide layer growth speed on the damage layer is slower than that on the silicon substrate. A pattern of the damage layer is defined by photolithography, and the damage layer having a depth of about 20 to 5,000 Å is formed using CF4, CHF3, or Ar gas at a pressure of 900 m Torr or less, or using Cl2 or HBr. In the preoxidation cleaning step, a solution containing NH4F, HF, and H2O, a standard solution containing NH4OH, H2O2, and H2O, and/or HF are used.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: March 27, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Kook Choi, Kyung Hawn Cho, Won Sik An, Chung Hwan Kwon
  • Patent number: 6200857
    Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: March 13, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tommy C. Hsiao, Mark T. Ramsbey, Yu Sun
  • Patent number: 6200843
    Abstract: A method for forming a semiconductor device. A substrate is provided. A first electrically insulating layer is formed on the substrate. A second electrically insulating layer is formed on the first electrically insulating layer. Openings are formed through the second electrically insulating layer down to the level of the first electrically insulating layer. Spacers are formed on opposing sidewalls of the openings. The spacers on one of the opposing side walls of the openings are removed, thereby exposing portions of the first electrically insulating layer. Exposed portions of the first electrically insulating layer in the openings are removed, thereby exposing portions of the substrate. The spacers on another of the opposing sidewalls of the openings are removed, thereby exposing portions of the first electrically insulating layer. A third electrically insulating layer is formed in the openings over the exposed portions of the first electrically insulating layer and the exposed portions of the substrate.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: March 13, 2001
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, Edward J. Nowak, Minh H. Tong
  • Patent number: 6197638
    Abstract: A method of providing oxide layers at the surface of the semiconductor substrate suitable for use with the formation of programmable logic devices. The method comprises the steps of: depositing a layer of nitride on the surface of the semiconductor substrate; etching a first and second portions of the nitride layer; forming a first and second regions of a first oxide layer on the substrate in the first and second etched portions of the nitride layer; etching a the first region of the oxide; forming a second oxide layer on the substrate having a first portion in the first etched portion of the nitride and a second portion overlying the first portion of the second region of the first oxide layer; removing the nitride layer; and forming a third layer of oxide having a first portion on the surface of the substrate, a second and third portions on the first and second portions of the second oxide layer.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: March 6, 2001
    Assignee: Vantis Corporation
    Inventor: Sunil D. Mehta
  • Patent number: 6184093
    Abstract: Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (120) that is thin in some regions, such as the cell region, and thicker in other regions (155), such as the periphery region. The method provides the gate oxide layer with different thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor device.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: February 6, 2001
    Assignee: Mosel Vitelic, Inc.
    Inventor: Kuo-Tung Sung
  • Patent number: 6184050
    Abstract: A method for forming a photodiode is provided. A substrate having a well with a first electric type therein is provided. An insulating layer is formed on the substrate. The insulating layer is patterned to form an opening. The insulating layer still remains with a thin thickness below the bottom of the opening. A heavily doped region with a second electric type is formed in the well in the position below the opening. A junction is thus formed between the heavily doped region and the well.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: February 6, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Jen-Yao Hsu
  • Patent number: 6165918
    Abstract: Systems and methods are described for fabricating semiconductor gate oxides of different thicknesses. Two methods for forming gate oxides of different thicknesses in conjunction with local oxidation of silicon (LOCOS) are disclosed. Similarly, two methods for forming gate oxides of different thicknesses in conjunction with shallow trench isolation (STI) are disclosed. Techniques that use two poly-silicon sub-layers of substantially equal thickness and techniques that use two poly-silicon sub-layers of substantially unequal thickness are described for both LOCOS and STI. The systems and methods provide advantages because gate uniformity and quality are improved, the processes and resulting devices are cleaner, and there is less degradation of carrier mobility.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: December 26, 2000
    Assignee: Integrated Device Technology, Inc.
    Inventors: James Yingbo Jia, Jeong-Yeol Choi
  • Patent number: 6162683
    Abstract: A method of forming a floating gate memory device having a memory array region (11), a first periphery region (15), and a second periphery region (17) is provided that comprises forming a polysilicon gate (18) insulatively disposed outwardly from a substrate (10) in the memory array region (11). The polysilicon gate (18) is doped with nitrogen ions. A first oxide layer (20) is formed outwardly from the substrate (10) in the first and second periphery regions (15) and (17) and from the polysilicon gate (18) of the memory array region (11). The thickness of oxide formed outwardly from the substrate (10) is greater relative to the thickness of oxide formed outwardly from the polysilicon gate (18). The first oxide layer (20) in the second periphery region (17) is removed. A second oxide layer (22) is formed outwardly from the substrate (10) of the second periphery region (13), from the first oxide layer (20) in the first periphery region (15) and from the polysilicon gate (18) of the memory array region (11).
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: December 19, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Men-Chee Chen
  • Patent number: 6150220
    Abstract: A dual thickness gate insulation layer, for use with, e.g., a dual gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), is formed using a more simplified method and improves the reliability. An impurity layer is formed in the semiconductor substrate, and the impurity layer includes a first portion and a second portion. An insulation layer is grown in the semiconductor substrate, and the insulation layer includes a first layer and a second layer which are different from each other in thickness. The present invention simplifies the insulation layer fabricating steps and improves product reliability.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: November 21, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Yun-Jun Huh, Nam-Hoon Cho
  • Patent number: 6147008
    Abstract: A new method is provided for the creation of an oxide layer that contains three different thicknesses. A first layer of oxide is grown on the surface of a substrate; a first layer of photoresist is deposited and patterned thereby partially exposing the surface of the underlying first layer of oxide. A nitrogen implant is performed into the surface of the underlying substrate; the photoresist mask of the first layer of photoresist is removed. A second layer of photoresist is deposited and patterned, the first layer of oxide is removed from above and surrounding the implanted regions of the substrate. The second mask of resist is removed.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: November 14, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Siow Lee Chwa, Ying Jin, Yung-Tao Lin
  • Patent number: 6143624
    Abstract: An insulated trench isolation structure is formed by ion implanting impurities proximate the trench edges to enhance the silicon oxidation rate and, hence, increase the thickness of the resulting oxide at the trench edges. Embodiments include masking and etching a barrier nitride layer, forming protective spacers on portions of the substrate corresponding to subsequently formed trench edges, etching the trench, removing the protective spacers, ion implanting impurities into those portions of the substrate previously covered by the protective spacers, and then growing an oxide liner. The resulting oxide formed on the trench edges is thick due to the enhanced silicon oxidation rate, thereby avoiding overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: November 7, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
  • Patent number: 6140189
    Abstract: A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: October 31, 2000
    Assignees: Sharp Laboratories of America, Inc., Sharp Kabushiki Kaisha
    Inventors: Sheng Teng Hsu, Katsumasa Fujii, Hidechika Kawazoe, Jong Jan Lee
  • Patent number: 6136657
    Abstract: A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: October 24, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Suk Yang, Chang-Hyun Cho, Ki-Nam Kim
  • Patent number: 6133164
    Abstract: The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: October 17, 2000
    Assignee: Vantis Corporation
    Inventor: Hyeon-Seag Kim
  • Patent number: 6127248
    Abstract: A fabrication method for a semiconductor device capable of adjusting a thickness of each portion of gate insulating film at both sides of a gate, which includes the steps of: providing a semiconductor substrate having a first region and a second region; forming a gate insulating film on the substrate; forming a conductive layer on the gate insulating film and patterning the conductive layer, for thereby forming a first gate and a second gate on the first and second regions, respectively; forming impurity areas in the first region at both sides of the first gate in order to reduce the velocity of oxidation; applying a re-oxidation process to the gate insulating film, for thereby forming each portion of the gate insulating film at both sides of the first gate thinner than each portion of the gate insulating film at both sides of the second gate; and respectively forming a source/drain region at both sides of the first and second gates.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: October 3, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Young-Gwan Kim
  • Patent number: 6124153
    Abstract: A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a gate insulating layer through a post oxide process. A polysilicon layer is patterned to become an active layer and a chemical vapor deposition oxide film deposited. By thermal oxidation a thermal oxide film is formed under the chemical vapor deposition oxide film. A gate electrode made of polysilicon is formed on the gate insulating layer. Thermal oxidation is performed to make the end portions of the thermal oxide film thicker than the portion under the gate electrode of the thermal oxide film. With this process, the electric field near the drain junction region is reduced and thus the leakage currents of the TFT decrease. In addition, the method in this invention is very simple compared with the conventional methods of obtaining a LDD structure and on-current is not reduced.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: September 26, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-hyung Lee, Yong-suk Jin
  • Patent number: 6124171
    Abstract: Transistors are formed on the substrate having two different thickness' of gate oxides. A silicon nitride mask is used to protect one of the gate oxides while the other is grown. A nitride mask is formed from a hydrogen balanced nitride layer formed using direct plasma deposited nitride with an ammonia and silane chemistry. In one embodiment the nitride mask remains in place in the completed transistor.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: September 26, 2000
    Assignee: Intel Corporation
    Inventors: Reza Arghavani, Bruce Beattie, Robert S. Chau, Jack Kavalieros, Bob McFadden
  • Patent number: 6117736
    Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: September 12, 2000
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 6110780
    Abstract: A new method of using a NO or N.sub.2 O treatment on a first area on a wafer in order to form a thinner oxide film in the first area and a thicker oxide film in a second area on a wafer using a single oxidation step is achieved. A semiconductor substrate of a silicon wafer is provided wherein a first area is separated from a second area by an isolation region. The silicon substrate in the second area is treated with NO or N.sub.2 O whereby a high-nitrogen silicon oxide layer is formed on the surface of semiconductor substrate in the second area. A tunnel window is defined in the first area and the oxide layer within the tunnel window is removed. The silicon wafer is oxidized whereby a tunnel oxide layer forms within the tunnel window and whereby a gate oxide layer is formed overlying the high-nitrogen silicon oxide layer in the second area. The tunnel oxide layer has a greater thickness than the combined thickness of the gate oxide layer and the high-nitrogen silicon oxide layer.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: August 29, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Mo-Chiun Yu, Wen-Ting Chu, Syun-Min Jang
  • Patent number: 6110783
    Abstract: A method for making an asymmetric MOS device having a notched gate oxide wherein a region of the gate oxide adjacent to either the source or drain is thinner than the remainder of the gate oxide. The resulting MOS device includes a channel under the notched region of the gate oxide with a relatively high concentration of mobile charge carriers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: August 29, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: James B. Burr
  • Patent number: 6110842
    Abstract: A method for forming integrated circuits having multiple gate oxide thicknesses. A high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only. In one embodiment, a pattern (12) is formed over a substrate (10) and a high density plasma nitridation is used to form a thin nitride or oxynitride layer (18) on the surface of the substrate (10) . The pattern (12) is removed and oxidation takes place. The nitride (or oxynitride) layer (18) retards oxidation (20b), whereas, in the areas (20a) where the nitride (or oxynitride) layer (18) is not present, oxidation is not retarded. In another embodiment, a thermal oxide is grown. A pattern is then placed that exposes areas where a thinner effective gate oxide is desired. The high density plasma nitridation is performed converting a portion of the gate oxide to nitride or oxynitride. The effective thickness of the combined gate dielectric is reduced.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: August 29, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Yasutoshi Okuno, Sunil V. Hattangady
  • Patent number: 6100141
    Abstract: A method for forming a dual-thickness gate oxide layer starts with forming and patterning a pad oxide layer and a silicon nitride layer on a substrate. The substrate contains pre-determined regions for accommodating the internal circuit and the ESD protection circuit respectively. A field oxide layer for separating the active regions of the internal circuit and the ESD protection circuit is formed by performing an oxidation process. A thick gate oxide layer is formed on the active region of the ESD protection circuit by oxidation after the pad oxide and the silicon nitride thereover are removed. Similarly, a thin gate oxide layer is formed on the active region of the internal circuit by oxidation after the pad oxide and the silicon nitride thereover are removed. A patterned conducting layer is then formed on the substrate as gates. An implantation process is performed to form the source/drain regions within the region of the internal circuit. Next, spacers that surround the gates are formed on the substrate.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: August 8, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Chen-Chung Hsu
  • Patent number: 6096664
    Abstract: A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: August 1, 2000
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Thomas S. Rupp, Stephan Kudelka, Jeffrey Gambino, Mary Weybright
  • Patent number: 6091109
    Abstract: The present invention provides a structure comprising: a first oxide film having a first thickness and extending on a first region of a semiconductor substrate; and a second oxide film having a second thickness which is thicker than the first thickness of the first oxide film, the second oxide film extending on a second region of the semiconductor substrate, wherein the first oxide film contains a first substance which is capable of decreasing an oxidation rate of a thermal oxidation process, while the second oxide film contains a second substance which is capable of increasing the oxidation rate of the thermal oxidation process.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventor: Eiji Hasegawa
  • Patent number: 6087223
    Abstract: A semiconductor flash memory device comprises a subrate, a plurality of buried bit lines, an insulation film, a floating gate, an inter-layer insulation film, and a control gate formed on the inter-layer insulation film. The fabrication method comprises forming the patterned first insulation films on the substrate, forming the gate insulation film on the substrate and between the patterned first insulation films, depositing a first poly-silicon layer on the gate insulation film and the patterned first insulation film, forming a floating gate by etching the first poly-silicon layer, forming a second insulation film on each of the floating gate and the substrate having the buried bit lines therein, and forming a control gate on the second insulation film. The flash memory device realizes high yield rate due to the simplified fabrication steps and facilitated fabrication.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: July 11, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventor: Kyeong Man Ra
  • Patent number: 6087237
    Abstract: A thick oxide layer is formed over a drain region of an MOS transistor while a thin oxide layer is provided over the source and channel regions. As a result both improved current driving ability and reduced gate induced drain leakage current are achieved.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: July 11, 2000
    Assignee: L.G. Semicon Co., Ltd
    Inventor: Hyun Sang Hwang
  • Patent number: 6077749
    Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. The oxide having the greater thickness is formed adjacent a source or drain region of the device, and the oxide with the lesser thickness is formed adjacent the other one of the source or drain regions. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO.sub.2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO.sub.2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: June 20, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Charles E. May
  • Patent number: 6072216
    Abstract: A vertical DMOSFET includes a buried layer which is of the same conductivity type as the drain and which extends into the heavily doped substrate and approaches or extends to the surface of the epitaxial layer at a central location in the MOSFET cell that is defined by the body regions of the MOSFET. In some embodiments the upper boundary of the buried layer generally conforms to the shape of the body region, forming a dish shaped structure under the body region. A significant portion of the current flowing through the channel is drawn into the buried layer and since the buried layer represents a relatively low-resistance path, the total resistance of the MOSFET is lowered without any significant effect on the breakdown voltage. The conformal buried layer can be formed by implanting dopant into the epitaxial layer at a high energy (0.5 to 3 MeV). Before the implant, a thick oxide layer is formed in a central region of the MOSFET cell.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: June 6, 2000
    Assignee: Siliconix Incorporated
    Inventors: Richard K. Williams, Wayne Grabowski
  • Patent number: 6046086
    Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: April 4, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo
  • Patent number: 6030872
    Abstract: A method for fabricating a mixed-mode device. A first gate oxide layer and a second gate oxide layer are formed. The polysilicon layer is used as a mask to pattern the gate oxide layers. Additionally, a top electrode is formed during the first gate oxide layer is patterned. A bottom electrode is formed during the second gate oxide layer is patterned. The first gate oxide layer and the second gate oxide layer are formed by a single oxidation operation, thus thicknesses of the first gate oxide layer and the second oxide layer can be effectively controlled.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: February 29, 2000
    Assignee: United Integrated Circuits Corp.
    Inventors: Jau-Hone Lu, Shu-Ying Lu, Chang-Ming Lu, Ya-Ling Hung
  • Patent number: 6017785
    Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: January 25, 2000
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chung-Chyung Han, Jeong Yeol Choi, Cheun-Der Lien
  • Patent number: 5976936
    Abstract: A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: November 2, 1999
    Assignee: Denso Corporation
    Inventors: Takeshi Miyajima, Norihito Tokura, Kazukuni Hara, Hiroo Fuma
  • Patent number: 5976946
    Abstract: A thin film formation method includes the deposition step of forming a dielectric thin film consisting of many elements. In the deposition step, first- and second-layer thin films are deposited as lower and upper layers on an underlayer, and at least one of the thin films is crystallized to form the dielectric thin film. The first-layer thin film closer to the underlayer is deposited with a larger composition of at least one kind of constituent element of the thin film than stoichiometric composition to allow for diffusion outside the film.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: November 2, 1999
    Assignee: NEC Corporation
    Inventors: Takeo Matsuki, Yoshihiro Hayashi
  • Patent number: 5970345
    Abstract: The invention comprises an integrated circuit having both low voltage and high voltage MOS transistors and a method for making the integrated circuit. In accordance with the method of making the integrated circuit, a first oxide layer is formed outwardly from a semiconductor substrate comprising a low voltage region and a high voltage region. A sacrificial layer is formed outwardly from the first oxide layer. The part of the sacrificial layer disposed outwardly from the low voltage region is removed to form an intermediate structure. The intermediate structure is selectively etched to remove the part of the first oxide layer disposed outwardly from the low voltage region. A second oxide layer is then formed comprising a first area disposed outwardly from the low voltage region and second area disposed outwardly from the high voltage region. The formation of the second oxide layer in the second area consumes the sacrificial layer.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: October 19, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Sunil V. Hattangady, George R. Misium
  • Patent number: 5960274
    Abstract: A method of providing oxide layers at the surface of the semiconductor substrate suitable for use with the formation of programmable logic devices. The method comprises the steps of: depositing a layer of nitride on the surface of the semiconductor substrate; etching a first and second portions of the nitride layer; forming a first and second regions of a first oxide layer on the substrate in the first and second etched portions of the nitride layer; etching a the first region of the oxide; forming a second oxide layer on the substrate having a first portion in the first etched portion of the nitride and a second portion overlying the first portion of the second region of the first oxide layer; removing the nitride layer; and forming a third layer of oxide having a first portion on the surface of the substrate, a second and third portions on the first and second portions of the second oxide layer.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: September 28, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sunil D. Mehta