Utilizing Varying Dielectric Thickness Patents (Class 438/981)
  • Patent number: 6818514
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: November 16, 2004
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 6812158
    Abstract: Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 2, 2004
    Assignee: LSI Logic Corporation
    Inventors: Wen-Chin Yeh, Venkatesh Gopinath, Arvind Kamath
  • Patent number: 6803278
    Abstract: The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: October 12, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Publication number: 20040198000
    Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces comer loss of STI regions caused by HF etchant.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 7, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chia-Lin Chen, Chien-Hao Chen, Mo-Chiun Yu
  • Patent number: 6790727
    Abstract: Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: September 14, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert E. Jones, Jr., Bruce E. White, Jr.
  • Patent number: 6787421
    Abstract: A semiconductor device (10) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric (16) is formed in a region of the device for higher voltage requirements, e.g. an I/O region (24). A thinner second gate dielectric (20) is formed in a region of the device for lower voltage requirements, e.g. a core device region (22). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide (26) is deposited over both dielectrics, followed by deposition of a gate electrode material (28). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: September 7, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David C. Gilmer, Christopher C. Hobbs, Hsing-Huang Tseng
  • Patent number: 6784060
    Abstract: Disclosed are a transistor in the semiconductor device and method of fabricating the same. A gate oxide film is formed using a nitrification oxide film in a low voltage device region and a gate oxide film is formed to have a stack structure of a nitrification oxide film/oxide film/nitrification oxide film in a high voltage device region. An electrical thickness by an increased dielectric constant could be reduced even when a physical thickness of the gate oxide film is increased. The leakage current and diffusion and infiltration of a dopant into the gate oxide film or the channel region could be prevented. Furthermore, an electrical characteristic of the device could be improved by reducing the leakage current.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: August 31, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Doo Yeol Ryoo
  • Publication number: 20040166698
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Application
    Filed: February 26, 2003
    Publication date: August 26, 2004
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 6780717
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Publication number: 20040161897
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 19, 2004
    Applicant: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Patent number: 6773991
    Abstract: Heavily concentrated impurities are selectively introduced into an exposed region of an oxide film. The exposed region of the oxide film where the impurities are introduced is selectively etched so that a surface of the semiconductor substrate is exposed An oxidizing process is performed and a second oxide film is formed on the first oxide film and the exposed surface of the semiconductor substrate. A polysilicon layer is formed as the floating gate.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 10, 2004
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Toshiyuki Orita
  • Patent number: 6773999
    Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near the center of the gate insulating film in the thickness direction. The peak value of nitrogen concentration in the gate insulating film is equal to or greater than 10 atm % and less than or equal to 40 atm %.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenji Yoneda
  • Patent number: 6770550
    Abstract: After a channel layer (7) containing nitrogen is formed in a channel region (5) in the main surface of a semiconductor substrate (1), a gate insulating film (9) and insulating films (10) are formed as oxide film by a thermal oxidation on the main surface of the semiconductor substrate (1). The insulating films (10) are thicker than the gate insulating film (9) because the oxidation reaction is suppressed in the nitrogen-introduced region. Further, stresses caused by the oxidation are suppressed-around the connections between the gate insulating film (9) and the insulating films (10). Accordingly, reduction in leakage current and improvement of gate insulating film reliability are compatibly realized.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tatsuya Kunikiyo
  • Patent number: 6764959
    Abstract: Within a sequential and repetitive thermal oxidation and stripping method for forming a plurality of gate dielectric layers having a maximum numbered plurality of thicknesses upon a semiconductor substrate, there is provided a compensating thermal annealing when forming less than the maximum numbered plurality of thicknesses of the plurality of gate dielectric layers upon the semiconductor substrate. By employing the compensating thermal annealing, the semiconductor substrate is more readily manufacturable in conjunction with related microelectronic fabrications.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: July 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Mo-Chiun Yu, Shih-Chang Chen, Chen-Hua Yu
  • Patent number: 6756272
    Abstract: Memory cells 10, according to the present invention, are comprised of a semiconductor substrate 2, and device isolating/insulating films 3 on the semiconductor substrate 2. A source region 4 and drain regions 5 are formed on the surface of the semiconductor substrate 2 within the device fabricating region, which is enclosed with the device isolating/insulating films 3. Floating gate electrodes 24 are formed above the semiconductor substrate 2. Each channel/gate insulating film 14a is formed between each channel region 23 and its corresponding floating gate electrode 24. Wherein, each channel region 23 is located between the source region 4 and one of the drain regions 5. Each tunnel oxide film 15, which is thinner than each channel/gate insulating film 14a, is formed between part of each drain region 5 and its corresponding floating gate electrode 24. Wherein the part is located far away from the depletion layer, which exists between each drain region 5 and its adjacent channel region 23.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: June 29, 2004
    Assignee: NEC Corporation
    Inventor: Kenichiro Nakagawa
  • Patent number: 6756263
    Abstract: A semiconductor device includes a trench isolating elements, a memory cell transistor and a peripheral circuit Vcc transistor having a thermal oxide film of a first thickness, and a peripheral circuit Vpp transistor including a thermal oxide film and a thermal oxide film formed before trench formation, having a second thickness greater than the first thickness.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: June 29, 2004
    Assignee: Rensas Technology Corp.
    Inventor: Naoki Tsuji
  • Patent number: 6750512
    Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: June 15, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Schillaci, Paola Maria Ponzio
  • Patent number: 6750159
    Abstract: An object of the present invention is to provide a semiconductor apparatus and a method of manufacturing the same, in which dispersion of a threshold voltage Vth of a transistor at every transistor is reduced to remove generation of fixed charges in a gate insulation film and a surface level to stabilize the operation of the semiconductor apparatus. A semiconductor apparatus having a MIS transistor (1), wherein a gate electrode (4) of said MIS transistor (1), which mainly contributes to the operation of a circuit, is continuously formed to a position above a bypass film (8) made of an insulation film through which a leak current is able to easily flow as compared with a gate insulation film (7) of said MIS transistor (1) under the same voltage.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 15, 2004
    Assignee: Sony Corporation
    Inventor: Hideshi Abe
  • Patent number: 6743688
    Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: June 1, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. James Fulford, Charles E. May
  • Patent number: 6740944
    Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: May 25, 2004
    Assignee: Altera Corporation
    Inventors: Peter John McElheny, Yowjuang (Bill) Liu
  • Patent number: 6737335
    Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: May 18, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dal Choi, Kyu-Charn Park, Dong-Seog Eun
  • Patent number: 6737291
    Abstract: A method for fabricating an image sensor capable of preventing a salicide layer formation on a photodiode as simultaneously as of forming the salicide layer selectively on a gate electrode closely located to a transistor which includes the steps of: forming a gate electrode on a substrate; forming an insulating spacer at lateral sides of the gate electrode; forming a photodiode in the substrate exposed at an one edge of the gate electrode; forming a floating diffusion area in the substrate exposed at the other edge of the gate electrode; forming a salicide barrier layer on the photodiode, wherein the salicide barrier layer exposes a upper surface and corners of the gate electrode; and forming a salicide layer on the exposed upper surface and the upper corners of the gate.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 18, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Boo-Taek Lim
  • Patent number: 6734113
    Abstract: The present invention provides a method for forming multiple gate oxide layers with different thickness in one chip by using a simple process. Particularly, a series of processes such as the first oxidation, the nitridation, the wet dip-out and the second oxidation contribute to form the gate oxide layer having different thicknesses. As a result, it is possible to integrate those various devices having different driving voltages into one chip. It is further possible to manufacture diverse products with improvements on layout design and device and process margins.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: May 11, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung-Jae Cho, Kwan-Yong Lim
  • Patent number: 6735123
    Abstract: A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: May 11, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nicholas H. Tripsas, Mark T. Ramsbey, Wei Zheng, Effiong Ibok, Fred T K Cheung
  • Patent number: 6713333
    Abstract: The disclosed invention provides a method for fabricating a MOSFET comprising the steps of forming a first insulation layer over a semiconductor substrate; forming a trench which bottoms on the semiconductor substrate in the first insulation layer so that the semiconductor substrate is exposed at the bottom of the trench; injecting impurities selectively under at least one end of the exposed surface of the semiconductor substrate; forming a second insulation layer to cover the bottom surface of the trench by oxidizing the exposed surface of the semiconductor substrate; forming a gate electrode over the second insulation layer inside the trench; removing the first insulation layer; forming a drain region under the surface of the semiconductor substrate so that the drain region contacts with one end of the second insulation layer, the end under which the impurities were injected; and forming a source region under the surface of the semiconductor substrate so that the source region contacts with the other end of
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: March 30, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Satoru Mayuzumi
  • Publication number: 20040058558
    Abstract: To provide a manufacturing method for a semiconductor device, with which it is possible to prevent silicon oxynitride formed upon nitriding a first gate oxide film from inhibiting oxidation of a second gate oxide film to keep a high reliability of the second gate oxide film. When a first gate insulating film is removed for forming the second gate oxide film or when a silicon substrate is washed just before the formation of the second gate oxide film, treatment with an ammonia-hydrogen peroxide solution is added, whereby a silicon oxynitride film at a site where the second gate oxide film is formed can be removed prior to the formation of the second gate oxide film.
    Type: Application
    Filed: July 10, 2003
    Publication date: March 25, 2004
    Inventor: Hitomi Sakurai
  • Patent number: 6709931
    Abstract: Methods of fabricating a semiconductor device having low-voltage MOS transistors and high-voltage metal-oxide semiconductor (“MOS”) transistors are provided. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate. The device isolation layer defines first and second active regions in low and high-voltage MOS transistor regions, respectively. A capping layer pattern is formed to cover the low-voltage MOS transistor region. The capping layer pattern exposes the second active region in the high-voltage MOS transistor region. A first gate oxide layer is formed on an entire surface of the semiconductor substrate having the capping layer pattern. The first gate oxide layer is formed using a chemical vapor deposition (“CVD”) technique. The first gate oxide layer serves as a gate insulating layer of the high-voltage MOS transistor.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: March 23, 2004
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Sung-Hoan Kim
  • Patent number: 6703322
    Abstract: Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second region, with a mask layer formed on the surface of the sacrificial oxide layer. By defining and patterning the mask layer, a first opening and a second opening, having predetermined surface areas, are formed in portions of the first and second regions of the mask layer to expose portions of the. The sacrificial oxide layer has a surface area equal to the first predetermined surface area, and portions of the sacrificial oxide layer having a surface area equal to the second predetermined surface area. A linear nitrogen doping process is then performed to simultaneously implant nitrogen ions with a first and second predetermined concentration into the first and second region, through the first opening and the second opening, respectively.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: March 9, 2004
    Assignee: Macronix International Co. Ltd.
    Inventors: June-Min Yao, Cheng-Shun Chen, Shu-Ya Hsu
  • Patent number: 6686246
    Abstract: The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: February 3, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Fernando Gonzalez
  • Patent number: 6674105
    Abstract: In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the n-channel MOS field effect transistors forming the flip flop. Namely, the p-channel MOS field effect transistors serving as the driver gates have a larger gate length and a smaller gate oxide film thickness than the n-channel MOS field effect transistors forming the flip flop.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: January 6, 2004
    Assignee: NEC Corporation
    Inventor: Kiyotaka Iwai
  • Patent number: 6661061
    Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: December 9, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Fred N. Hause
  • Patent number: 6660594
    Abstract: An integrated circuit device, such as a merged device, is formed by forming a first gate oxide layer on a first region, such as a logic circuit region, of a substrate. A conductive layer is formed on the first gate oxide layer. A second gate oxide layer is formed on a second region, such as a cell array region, of the substrate. A first gate pattern is formed on the second gate oxide layer. The conductive layer and the first gate oxide layer are patterned to form a second gate pattern. A silicide layer is formed on the second gate pattern and in the substrate adjacent to the second gate pattern.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: December 9, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-hoon Han, Duck-hyung Lee, Dong-woo Kim
  • Patent number: 6653192
    Abstract: The present invention relates to a method of manufacturing a semiconductor device by which a high voltage device and a low voltage device are simultaneously formed. Nitrogen ions are implanted only into the semiconductor substrate in the low voltage device region. An oxidation process under N2O gas or NO gas ambient is then performed to form a first nitrification oxide film having a thick thickness in a high voltage device region and a second nitrification oxide film having a thin thickness and a high concentration of nitrogen ions in a low voltage device region. Next, the first and second nitrification oxide films are rapidly nitrified to form a dual gate insulating film consisting of third and fourth nitrification oxide films having a high dielectric constant. Therefore, reliability of a gate insulating film can be improved and increase in the leakage current can be also prevented.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: November 25, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventor: Doo Yeol Ryoo
  • Patent number: 6645817
    Abstract: Method of manufacturing a semiconductor device comprising MOS-transistors of a first type (A) having a gate oxide (3) of a first thickness and MOS-transistors of a second type (B) having a gate oxide (10) of a second, greater thickness. In this method, active regions (4) and field oxide regions (5) are formed in a silicon body (1). Then a layer of gate oxide (6) of said first thickness is formed on the active regions, on which a layer (7,8) of an electrode material is deposited. In the layer of electrode material, the gate electrodes (9) for the transistors of the second type are formed. Then an oxidation treatment is carried out, in which the thickness of the gate oxide under said gate-electrodes increases to the desired second thickness (10). During these processes, the electrode layer on the active regions of the MOS-transistors of the first type is not disturbed. The gate electrodes for the transistors of the first type are formed after the oxidation treatment.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 11, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Klaas Gerbrand Druijf, Hendrik Hubertus Van Der Meer
  • Publication number: 20030199140
    Abstract: A thin gate insulating film of a transistor in a core circuit region is formed with a three-layer structure having an oxide film formed by thermally oxidizing a main surface of a semiconductor substrate (silicon substrate), a CVD nitride film formed on the oxide film and oxynitride film formed by oxidizing the upper surface of the CVD oxide film. A thick gate insulating film of a transistor in an I/O circuit region is formed with a pure oxide film. As a result, such a semiconductor device is obtained in that NBTI of the transistor in the I/O circuit region can be reduced, reliability of the gate insulating film can be improved while a threshold voltage of the transistor in the core circuit region can be properly controlled, and NBTI of the transistor in the core circuit region can be reduced.
    Type: Application
    Filed: October 21, 2002
    Publication date: October 23, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Tamotsu Ogata
  • Patent number: 6617214
    Abstract: An integrated circuit is made with transistors having varying characteristics in the same well. One transistor, which is particularly useful as an I/O device, has a relatively deep source/drain with a relatively thick gate dielectric. The well doping is selected so that this transistor has low leakage. Another transistor type, which is particularly useful for low voltage analog purposes, has a relatively thin gate dielectric and the relatively deep source/drain. A third transistor type, which is particularly suited for high density and low power operation, has a relatively shallow source/drain, the relatively thin gate dielectric, and a high dose halo implant. A fourth transistor type, which may also be present for high-speed operations, has the relatively thin gate dielectric, the relatively shallow source/drain, and may have a halo implant. The halo implant will be of a lower dosage than the halo implant for the third transistor type.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: September 9, 2003
    Assignee: Motorola, Inc.
    Inventors: Choh-Fei Yeap, Srinivas Jallepalli, Alain C. Duvallet, Franklin D. Nkansah
  • Patent number: 6605511
    Abstract: A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: August 12, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tuan Duc Pham, Mark T. Ramsbey, Yu Sun, Chi Chang
  • Patent number: 6605501
    Abstract: A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: August 12, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew-Hoe Ang, Eng-Hua Lim, Cher-Liang Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou
  • Patent number: 6602751
    Abstract: A disclosed method for manufacturing semiconductor devices includes the steps of: implanting an ion in a region in which a medium thickness gate oxide film is to be formed, under such conditions that a range of fluorine may measure 15-150 nm in a P-type silicon substrate; removing a chemical oxide film on the surface or the region; and forming by oxidation processing the gate oxide film with the medium film thickness in the region.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: August 5, 2003
    Assignee: NEC Corporation
    Inventor: Takuo Oohashi
  • Patent number: 6586301
    Abstract: Heavily concentrated impurities are selectively introduced into a portion outside a polysilicon region of a region of a tunnel window area of an EEPROM memory cell, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in a tunnel window area by oxidizing residual polysilicon.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: July 1, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: Toshiyuki Orita
  • Patent number: 6583011
    Abstract: A method to grow layers of gate oxide or gate base materials of different thicknesses for dual gate structures. The process starts with a semiconductor surface in which STI regions have been formed and over the surface of which a layer of gate base material has been grown. A dielectric, such as nitride, is deposited, masked and etched over a first region where thin gate base material must be created thereby exposing the surface of the deposited layer of gate base material in that region. The gate base material is etched to the desired thickness, creating a first thin layer of gate base material. A thick first layer of gate electrode material, poly, is deposited over the dielectric thereby including the surface of the first thin layer of gate base material, and polished down to the surface of the dielectric leaving gate electrode material deposited in the opening above the first thin layer of gate base material.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: June 24, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Li Xia, Gao Feng, Yong Meng Lee
  • Patent number: 6576512
    Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: June 10, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Taniguchi, Shoji Shukuri, Kenichi Kuroda, Shuji Ikeda, Takashi Hashimoto
  • Publication number: 20030102504
    Abstract: A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 5, 2003
    Inventors: Geeng-Chuan Chern, Amitay Levi, Dana Lee
  • Patent number: 6555484
    Abstract: Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: April 29, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Krishnaswamy Ramkumar, Hanna Bamnolker
  • Patent number: 6555436
    Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 29, 2003
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David M. Rogers, Ravi Sunkavalli, Janet Wang, Narbeh Derhacobian, Yider Wu
  • Patent number: 6551879
    Abstract: A method for forming a semiconductor device that includes defining a substrate to include a peripheral section and a core section, masking the peripheral section of the substrate, growing a first dielectric layer over the core section of the substrate, depositing a first polysilicon layer over the first dielectric layer for forming at least one gate structure, growing a first oxide layer over the first polysilicon layer, depositing a nitride layer over the first oxide layer, implanting oxygen ions into the nitride layer, unmasking the peripheral section of the substrate, and growing a second oxide layer over the nitride layer, wherein the growth rate of the second oxide layer is increased due to the implantation of oxygen ions in the nitride layer.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: April 22, 2003
    Assignee: Macronix International Co., Inc.
    Inventor: Kent Kuohua Chang
  • Patent number: 6548340
    Abstract: The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: April 15, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Fernando Gonzalez
  • Patent number: 6534364
    Abstract: A tunnel diode construction 12 for an EEPROM device 10, and method for making it are shown. A tank 13 is provided at a surface of a semiconductor substrate 5 containing a doped diffused tunnel region 46. A layer of insulation 38 is provided over the surface of the substrate with a first thickness 48 to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness 39 elsewhere. A conducting floating gate 19 is provided above the doped diffused tunnel region 46 and at least part of the tank 13, on the layer of insulation 38. The floating gate 19 extends over the oxide 38 beyond the lateral boundaries of the doped diffused tunnel region 46 in every direction to terminate over the second thickness of oxide 39 over the tank 13.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: March 18, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: John P. Erdeljac, Louis N. Hutter
  • Publication number: 20030027391
    Abstract: Within a sequential and repetitive thermal oxidation and stripping method for forming a plurality of gate dielectric layers having a maximum numbered plurality of thicknesses upon a semiconductor substrate, there is provided a compensating thermal annealing when forming less than the maximum numbered plurality of thicknesses of the plurality of gate dielectric layers upon the semiconductor substrate. By employing the compensating thermal annealing, the semiconductor substrate is more readily manufacturable in conjunction with related microelectronic fabrications.
    Type: Application
    Filed: August 2, 2001
    Publication date: February 6, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mo-Chiun Yu, Shih-Chang Chen, Chen-Hua Yu
  • Publication number: 20030013323
    Abstract: A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.
    Type: Application
    Filed: June 14, 2002
    Publication date: January 16, 2003
    Inventors: Richard Hammond, Matthew Currie