Utilizing Varying Dielectric Thickness Patents (Class 438/981)
  • Patent number: 7405118
    Abstract: The present invention provides a semiconductor device fabrication method including the steps of: forming first gate insulating films in first to third active regions of a silicon substrate; wet-etching the first gate insulating film of the second active region through a first resist opening portion of a first resist pattern; forming a second gate insulating film in the second active region; forming on the silicon substrate a second resist pattern having a second resist portion larger than the first resist opening portion; wet-etching the first gate insulating film of the third active region through a second resist opening portion of the second resist pattern; and forming a third gate insulating film in the third active region.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: July 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Satoshi Nakai
  • Patent number: 7402480
    Abstract: The individual performance of various transistors is optimized by tailoring the thickness of the gate oxide layer to a particular operating voltage. Embodiments include forming transistors with different gate oxide thicknesses by initially depositing one or more gate oxide layers with intermediate etching to remove the deposited oxide from active regions wherein transistors with relatively thinner gate oxides are to be formed, and then implementing one or more thermal oxidation steps. Embodiments include forming semiconductor devices comprising transistors with two different gate oxide thicknesses by initially depositing an oxide film, selectively removing the deposited oxide film from active areas in which low voltage transistors having a relatively thin gate oxide are to be formed, and then implementing thermal oxidation.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: July 22, 2008
    Assignee: Linear Technology Corporation
    Inventors: François Hébert, Salman Ahsan
  • Patent number: 7388279
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 17, 2008
    Assignee: Interconnect Portfolio, LLC
    Inventors: Joseph C. Fjelstad, Kevin P. Grundy, Para K. Segaram, Gary Yasumura
  • Patent number: 7378311
    Abstract: The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: May 27, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 7378308
    Abstract: A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 27, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ju-Wang Hsu, Chih-Hsin Ko, Jyu-Horng Shieh, Baw-Ching Perng, Syun-Ming Jang
  • Patent number: 7374635
    Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: May 20, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Shigemi Murakawa, Toshikazu Kumai, Toshio Nakanishi
  • Publication number: 20080073722
    Abstract: A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate embodiment, circuit has a plurality of read ports. In an alternate embodiment, selecting the optimal gate oxide thickness for the transistors in circuit allows the trade-off between transistor switching speed and gate leakage current to be optimized to produce a circuit having a fast enough read access time and a low enough standby power.
    Type: Application
    Filed: September 25, 2006
    Publication date: March 27, 2008
    Inventor: Thomas W. Liston
  • Patent number: 7348247
    Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. A disclosed semiconductor device comprises a semiconductor substrate; a gate formed on the semiconductor substrate; a gate oxide layer interposed between the semiconductor substrate and the gate; and source and drain regions formed within the substrate at opposite sides of the gate. The gate oxide layer has a first region with a first thickness and a second region with a second thickness. The second thickness is thicker than the first thickness.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: March 25, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Geon-Ook Park
  • Patent number: 7321141
    Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: January 22, 2008
    Assignee: United Microelectronics Corp.
    Inventor: Jhy-Jyi Sze
  • Patent number: 7300847
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: November 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7291534
    Abstract: A method of manufacturing a semiconductor device has the steps of: preparing a semiconductor substrate having a structure in which first and second active regions are isolated by a field oxide; forming a first insulation film and a first film on the semiconductor substrate; exposing the first active region in the first active region; forming a second insulation film and a first conductive film over the first active region, the second insulation film being thicker than the first insulation film; processing the first conductive film and the second insulation film into a first gate electrode and a first gate insulation film; exposing the second active region in the second active region; forming a third insulation film and a second conductive film on the over the second active region, the third insulation film being thinner than the second insulation film; and processing the second conductive film and the third insulation film into a second gate electrode and a second gate insulation film.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: November 6, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noriko Tomita
  • Patent number: 7282426
    Abstract: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: October 16, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Venkat R. Kolagunta, David C. Sing
  • Patent number: 7276414
    Abstract: NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Michael Violette, Garo Derderian, Todd R. Abbott
  • Patent number: 7273787
    Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: September 25, 2007
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Wen-Ji Chen, Tung-Po Chen, Kai-An Hsueh, Sheng-Hone Zheng
  • Patent number: 7271065
    Abstract: Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do not increase the costs or complexity of the device fabrication process. The novel memory cell includes a source region and a drain region separated by a channel region in a horizontal substrate. A first vertical gate is separated from a first portion of the channel region by a first oxide thickness. A second vertical gate is separated from a second portion of the channel region by a second oxide thickness. The total capacitance of these memory devices is about the same as that for comparable source and drain spacings. However, the floating gate capacitance (CFG) is much smaller than the control gate capacitance (CCG) such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 7262103
    Abstract: Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: August 28, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Joon Hyeon Lee, Woon Yong Kim
  • Patent number: 7259071
    Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 21, 2007
    Assignee: SilTerra Malaysia Sdn.Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
  • Patent number: 7208378
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: April 24, 2007
    Assignee: Silterra
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Patent number: 7172942
    Abstract: The present invention provides a method for manufacturing a semiconductor elemental device wherein a first gate oxide film and a second gate oxide film thicker than the first gate oxide film are formed on a substrate provided with a device forming region comprised of silicon, comprising the steps of implanting an element for promoting a forming speed of each gate oxide film into a region for forming the second gate oxide film of the substrate; and simultaneously forming the first gate oxide film and the second gate oxide film by a thermal oxidation method, wherein in the element implanting step, the element is implanted in space of a depth equal to half the thickness of the second gate oxide film placed in predetermination of its formation from the surface of the substrate in such a manner that with the peak of a concentration distribution of the element as the center, a concentration distribution in which both sides of the peak is given twice as large as a standard deviation of the concentration distribution
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: February 6, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Koichi Kishiro
  • Patent number: 7169670
    Abstract: Provided is related to a method of forming a semiconductor device comprises steps of: providing a semiconductor substrate having a low voltage region and a high voltage region; forming a pad oxide layer and a pad nitride layer in sequence on the semiconductor substrate; removing the pad nitride layer and the pad oxide layer on the semiconductor substrate of the high voltage region, wherein a surface of the semiconductor substrate of the high voltage region is exposed and recessed; forming a sacrificial oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the sacrificial layer; forming a first gate oxide layer on the surface of the semiconductor substrate of the high voltage region; removing the pad oxide layer and the pad nitride layer left on the semiconductor substrate of the low voltage region, wherein a surface of the semiconductor substrate of the low voltage region is exposed and recessed; and forming a second gate oxide layer on the first gate oxide layer and t
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 30, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min Kyu Lee, Hee Hyun Chang, Jum Soo Kim, Jung Ryul Ahn
  • Patent number: 7166185
    Abstract: The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: January 23, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Shigemi Murakawa, Toshikazu Kumai, Toshio Nakanishi
  • Patent number: 7151031
    Abstract: Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: December 19, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Shin Kwon, Soon-Moon Jung
  • Patent number: 7118974
    Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: October 10, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chen, Chien-Hao Chen, Mo-Chiun Yu
  • Patent number: 7112486
    Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: September 26, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Heung-Jae Cho, Se-Aug Jang, Kwan-Yong Lim, Jae-Geun Oh, Hong-Seon Yang, Hyun-Chul Shon
  • Patent number: 7084035
    Abstract: A method for forming three kinds of MOS transistors on a single semiconductor substrate, each provided with gate oxides different in thickness from each other, without detracting from the device characteristics.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: August 1, 2006
    Assignee: Ricoh Company, Ltd.
    Inventor: Naohiro Ueda
  • Patent number: 7084453
    Abstract: A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: August 1, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Geeng-Chuan Chern, Amitay Levi, Dana Lee
  • Patent number: 7071038
    Abstract: A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: July 4, 2006
    Assignee: Freescale Semiconductor, Inc
    Inventors: Dina H. Triyoso, Olubunmi O. Adetutu, Randy W. Cotton
  • Patent number: 7060588
    Abstract: A semiconductor device adopting shallow trench isolation for reducing an internal stress of a semiconductor substrate. The semiconductor device is composed of a semiconductor substrate provided with a trench for isolation, and an insulating film formed to cover the trench for relaxing an internal stress of the semiconductor substrate. The insulating film includes a first portion disposed to be opposed to a bottom of the trench, and a second portion disposed to be opposed to a side of the trench. A first thickness of the first portion is different from a second thickness of the second portion.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: June 13, 2006
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiro Tamura
  • Patent number: 7056783
    Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: June 6, 2006
    Assignee: Agere Systems Inc.
    Inventors: Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Samir Chaudhry, Jack Qingsheng Zhao
  • Patent number: 7056791
    Abstract: A method of fabricating an embedded flash memory device. A substrate having a memory area is provided. A device is formed on the substrate in the memory area. A conductive layer is formed over the substrate to cover the device in the memory area. A conformal insulating layer is formed on the conductive layer and the substrate. The insulating layer is removed at an edge of the memory area. By anisotropic etching, the insulating layer and part of the conductive layer is removed to form a control gate on the sidewall of the device. Thus, polysilicon residue caused by the conventional control gate process does not occur.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: June 6, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Der-Shin Shyu, Hung-Cheng Sung, Chen-Ming Huang, Hsui Ouyang
  • Patent number: 7041562
    Abstract: Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: May 9, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sangwoo Lim, Yongjoo Jeon, Choh-Fei Yeap
  • Patent number: 7015111
    Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: March 21, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul J. Rudeck, Don C. Powell
  • Patent number: 6984593
    Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Arne W. Ballantine, Douglas D. Coolbaugh, Steve S. Williams
  • Patent number: 6979858
    Abstract: A semiconductor device having excellent characteristics is provided without deteriorated film quality. A first oxide film is divided into three regions A, B and C. Lengths I, II and III of the regions A, B and C in a plane direction of the silicon substrate are set equal to each other. In the first oxide film, a thermal treatment is carried out such that the film thicknesses of the regions A and C are increased. The thermal treating time, the thermal treating temperature and other parameters are adjusted such that sectional areas of the regions A and C become 1.5 times of a sectional area of the region B, while a film thickness of the region B is maintained.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: December 27, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yuki Saito, Yasutaka Kobayashi
  • Patent number: 6967147
    Abstract: Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: November 22, 2005
    Assignee: Infineon Technologies AG
    Inventors: Helmut Horst Tews, Jochen Beintner
  • Patent number: 6967130
    Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: November 22, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chun Chen, Tzu-Liang Lee, Shih-Chang Chen
  • Patent number: 6958278
    Abstract: Semiconductor devices having a dual gate and method for fabricating the same are disclosed. A disclosed example method comprises: forming dummy gates in a semiconductor substrate; sequentially forming a lightly doped drain (LDD) region, a spacer and a source/drain; depositing an insulation film above the semiconductor substrate; exposing the dummy gates by planarizing the insulation film; removing the dummy gates; selectively injecting impurities into a region associated with at least one of the removed dummy gates; forming gate oxide films having different thicknesses on the regions associated with the removed dummy gates; depositing a polysilicon layer above the gate oxide films; and then forming polysilicon gates by planarizing the polysilicon layer.
    Type: Grant
    Filed: December 26, 2003
    Date of Patent: October 25, 2005
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Ki-Min Lee
  • Patent number: 6955971
    Abstract: A semiconductor structure and methods for fabricating are disclosed. In an implementation, a method of fabricating a semiconductor structure includes forming a first semiconductor material substrate with a first dielectric area having a first thickness and a second dielectric area having a second thickness, bonding the first substrate to a second semiconductor substrate, and thinning at least one of the first and second substrates. The invention also pertains to a semiconductor structure. The structure includes a semiconductor substrate having a surface layer of semiconductor material, a first dielectric layer of a first dielectric material buried under the surface layer, and a second dielectric layer buried under the surface layer. In an embodiment, the thickness of the first dielectric layer is different than the thickness of the second dielectric layer.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 18, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Oliver Rayssac, Cécile Aulnette, Carlos Mazuré
  • Patent number: 6953727
    Abstract: A method of manufacturing a semiconductor device, having the steps of: (a) forming a first gate insulating film having a first thickness in a plurality of regions on a surface of a semiconductor substrate; (b) removing the first gate insulating film in a first region among the plurality of regions and allowing a native oxide film to be formed; (c) heating the semiconductor substrate in a reducing atmosphere and selectively reducing and removing the native oxide film formed in the step (b); and (d) after the step (c), forming a second gate insulating film having a second thickness thinner than the first thickness on the surface of the semiconductor substrate in the first region.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: October 11, 2005
    Assignee: Fujitsu Limited
    Inventor: Mitsuaki Hori
  • Patent number: 6946349
    Abstract: A method for integrating a SONOS device with an improved top oxide with SiO2 gate oxides of different thickness is described. In a first embodiment during ISSG oxidation to form the SiO2 gate oxides, a thin sacrificial silicon nitride layer is used over the top oxide of the ONO to minimize loss and to control the top oxide thickness. In a second embodiment the top oxide layer for the SONOS device is formed by depositing an NO stack. During ISSG oxidation to form the SiO2 gate oxides a portion of the Si3N4 in the NO stack is converted to SiO2 to form the top oxide with improved thickness control.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: September 20, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jae Gon Lee, Hwa Weng Koh, Elgin Quek, Dong Kyun Sohn
  • Patent number: 6936383
    Abstract: By using conventional spacer and etch techniques, microstructure elements, such as lines and contact openings of integrated circuits, may be formed with dimensions that are mainly determined by the layer thickness of the spacer layer. In a sacrificial layer, an opening is formed by means of standard lithography and etch techniques and, subsequently, a spacer layer is conformally deposited, wherein a thickness of the spacer layer at the sidewalls of the opening substantially determines the effective width of the microstructure element to be formed. By using standard 193 nm lithography and etch processes, gate electrodes of 50 nm and beyond can be obtained without significant changes in standard process recipes.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 30, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Martin Mazur, Carsten Hartig, Georg Sulzer
  • Patent number: 6908774
    Abstract: A method for adjusting the thickness of a thin semiconductor material layer. The method includes measuring the layer to establish a thickness profile, determining thickness adjustment specifications from the measured thickness profile, and adjusting the thickness of the layer in accordance with the specifications by sacrificial oxidation. An apparatus for adjusting the thickness of a thin layer of semiconductor material according to this method is also disclosed.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: June 21, 2005
    Assignee: S.O. I. Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud
  • Patent number: 6905956
    Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 14, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Chris W. Hill
  • Patent number: 6900097
    Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as ?6V˜12V, ?12V˜6V, ?9V˜9V etc.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: May 31, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Rong-Ching Chen, Ching-Chun Huang, Jy-Hwang Lin
  • Patent number: 6890822
    Abstract: A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: May 10, 2005
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ong Boon Teong, Oh Choong Young, Ng Chun Leng, Joung Joon Ho
  • Patent number: 6875656
    Abstract: A method for improving the thickness uniformity of a silicon-on-insulator (SOI) film on a semiconductor wafer. The preferred embodiments disclose using a selective epitaxial growth (SEG), sacrificial oxidation and an oxide removal process for improving SOI thickness uniformity. The SEG process is a leveling process that grows a materially identical layer of epitaxial silicon over the SOI layer, thus thickening the SOI layer and increasing its thickness uniformity. The sacrificial oxidation process oxidizes a portion of the newly thickened SOI layer, converting it into an oxide. An oxide removal process, commonly an etch process, removes the oxide produced by sacrificial oxidation while maintaining the thickness uniformity achieved by SEG leveling.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: April 5, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Gabriel G. Barna
  • Patent number: 6846714
    Abstract: An EEPROM device having voltage limiting charge pumping circuitry includes charge pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer. A process for fabricating the device is also provided.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: January 25, 2005
    Assignee: Lattice Semiconductor Corporation
    Inventors: Sunil D. Mehta, Kerry Ilgenstein
  • Patent number: 6841448
    Abstract: A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: January 11, 2005
    Assignee: Infineon Technologies AG
    Inventors: Oliver Gehring, Wolfram Langheinrich
  • Publication number: 20040259341
    Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.
    Type: Application
    Filed: June 20, 2003
    Publication date: December 23, 2004
    Applicant: Taiwan Semicondutor Manufacturing Co.
    Inventors: Chi-Chun Chen, Tzu-Liang Lee, Shih-Chang Chen
  • Patent number: 6821840
    Abstract: A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Gert Burbach, Thomas Feudel