Abstract: A method of providing oxide layers at the surface of the semiconductor substrate suitable for use with the formation of programmable logic devices. The method comprises the steps of: depositing a layer of nitride on the surface of the semiconductor substrate; etching a first and second portions of the nitride layer; forming a first and second regions of a first oxide layer on the substrate in the first and second etched portions of the nitride layer; etching a the first region of the oxide; forming a second oxide layer on the substrate having a first portion in the first etched portion of the nitride and a second portion overlying the first portion of the second region of the first oxide layer; removing the nitride layer; and forming a third layer of oxide having a first portion on the surface of the substrate, a second and third portions on the first and second portions of the second oxide layer.

Abstract: A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, the first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate. The increased oxide thickness adjacent to the discontinuities of the isolation trench reduces the electric field across the oxide.

Abstract: A method is provided for use in semiconductor fabrication processes for forming a plurality of gate oxide layers with various predefined thicknesses in mixed-mode or embedded circuits that are formed in a semiconductor substrate. In particular, the gate oxide layers of various predefined thicknesses are formed by means of separated growth, which allows all the gate oxide layers to be each formed in one single step, instead of combining two or more oxide layers as in conventional processes, so that the thicknesses can be more easily controllable to the desired levels. The quality of the thus-formed gate oxide layers can thus be better assured.

Abstract: Different thicknesses of gate oxide can be formed on a single chip in a single oxidation process by selectively implanting nitrogen into the surface of the chip in a pattern corresponding to the desired differences in gate oxide thickness. Implanting nitrogen to a silicon substrate reduces the rate at which oxide grows on the surface. Thus, by implanting different dosages of nitrogen into the surface of the substrate, thicker or thinner oxide layers can be provided. A processing chip with embedded DRAM can then be formed where the logic circuitry has a thin gate oxide and the DRAM circuitry has a thick gate oxide by implanting the higher dosage of nitrogen into the region of the chip where the logic circuits are to be formed. Different gate oxide thicknesses are then provided by exposing both the logic circuitry and the embedded DRAM section to a single thermal oxidation process.

Abstract: Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions.The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

Abstract: A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate. In a further aspect of the invention, the method comprises applying laser energy through a patterned, reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer may be applied to the surface of the semiconductor substrate. In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction.

Abstract: A first pair electrodes consisting of an anode to which a plurality of wiring lines to be anodized are connected and a cathode that is opposed to the anode, and a second pair electrodes for collecting impurities in a forming solution are immersed in a forming solution. A voltage is applied to the plurality of wiring lines in such a manner that at least one of the plurality of wiring lines receives the voltage for a different period than the other wiring lines.

Abstract: The invention relates to a method of forming a non-volatile memory device with a ramped tunnel dielectric layer, in which a floating gate material layer is being oxidized such that a tunnel dielectric layer is formed having a thickness at a drain region edge which is greater than a thickness at a source region edge.

Abstract: An electrostatic-discharge (ESD) protecting circuit of a semiconductor device prevents damage from an ESD applied to an internal circuit through an input or output pad. The thickness of respective gate insulating layers of respective active devices of the electrostatic-discharge protecting circuit and internal circuit, which are formed within a given radius in the range of about 350 .mu.m to about 1000 .mu.m from the electrostatic-discharge protecting circuit, is thicker than the thickness of gate insulating layers of active devices formed outside the radius.

Abstract: Disclosed herein is a stacked gate type non-volatile semiconductor memory cell including source/drain regions having a first portion covered with a tunnel oxide film and a second portion covered with an insulator film. The memory cell further includes a gate insulating film formed on a channel region, wherein the tunnel insulating film is thinner than the gate oxide film and the insulator film is thicker than the gate insulating film. A floating gate is formed on the respective insulating films and a control gate is formed over the floating gate with an intervention of a second gate insulating film.

Abstract: The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.

Abstract: A method for form an integrated circuit device begins by growing a tunnel oxide (22). The tunnel oxide is exposed to a nitrogen containing ambient whereby nitrogen is incorporated at atomic locations at the interface between the tunnel oxide (22) and a substrate (11). This tunnel oxide and nitrogen exposure is performed for all of a floating gate active area (12), a high voltage active area (14) and a logic gate active area (16). A floating gate electrode (24) and interpoly dielectric regions (26 through 30) are then formed in the floating gate region (12). The tunnel oxide (22) is etched from the active areas (14 and 16) whereby nitrogen contamination (32) may remain. An optional sacrificial oxidation and a low temperature 830.degree. C. wet oxidation process utilizing HCL, H2 and O2 is then used to grow a high voltage gate dielectric (34) which has been shown to improve charge to breakdown characteristics by a factor of 1,000.

Abstract: The present invention is a semiconductor device and a method of providing such a semiconductor device which allows a high junction breakdown voltage and a high field turn on voltage, while allowing the field oxide thickness to be limited and being independent of a misalignment of the mask. A method in accordance with the present invention for providing a semiconductor device including a field oxide, the field oxide including a field oxide boundary wherein the field oxide is located within the boundary, the method comprising the step of implanting a first implant area into the substrate, including areas proximate indistance to a junction area, the first area being implanted with a first implant concentration and implanting a second implant area distal to the junction area, the second implant area being implanted with a second implant concentration, wherein the depth of the implant is controlled by the energy level, wherein the implant of the second implant area is independent of a misalignment of a mask.

Abstract: The method for fabricating a charge coupled device disclosed includes the steps of forming a gate oxide film and forming a transfer electrode. The provisional oxide film is formed on a semiconductor substrate, and the provisional oxide film at a transfer electrode formation region is selectively etched away. The transfer electrode from a polycrystalline silicon film on the gate oxide film of the transfer electrode formation region is selectively formed, and the provisional oxide film between transfer electrodes is etched away. Since the oxide film which protects the silicon substrate surface (oxide film/silicon interface) of the second layer transfer electrode formation region during the patterning of the first layer polycrystalline film and the insulating oxide film which covers the first layer transfer electrode surface, is formed in the two-step oxidation process, it is possible to adjust the thicknesses of the two oxide films as desired.

Abstract: A semiconductor read-only memory (ROM) device is provided. The particular semiconductor structure of this ROM device can reduce the parasitic capacitance between the bit lines and the word lines, such that the resistance-capacitance time constant of the memory cells can be reduced to thereby speed up the access time to the memory cells. The binary data stored in each memory cell is dependent on whether a contact window is predefined to be formed in a thick insulating layer between the buried bit lines and the overlaying word lines. If the gate electrode of one memory cell is electrically connected to the associated word line via one contact window through the insulating layer, that memory cell is set to a permanently-ON state representing a first binary value; otherwise, that memory cell is set to a permanently-OFF state representing a second binary value. The threshold voltage of the permanently-ON memory cells is about in the range from 0.4 V to 0.7 V.

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract: A process including the steps of forming a gate oxide layer on a semiconductor substrate; masking the gate oxide layer with a nitride mask forming openings in the gate oxide layer using the nitride mask; and forming, at the openings, tunnel oxide regions of a thickness smaller than the thickness of the gate oxide layer. The nitride mask presents a thickness smaller than the width of the openings to improve etching of the gate oxide layer and subsequent washing. The mask also protects the covered layers when etching the gate oxide and growing the tunnel oxide regions, and is removed easily without damaging the exposed layers.

Abstract: The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relayout of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e.

Abstract: An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.

Abstract: A liquid crystal display comprises a lower substrate provided with a plurality of scanning signal lines, a plurality of image signal lines perpendicularly intersecting the scanning signal lines, a plurality of thin-film transistors formed at the intersection points of the scanning signal lines and the image signal lines, and a plurality of pixel electrodes connected respectively to the thin-film transistors; an upper substrate disposed opposite to the lower substrate and provided with a common electrode opposite to the pixel electrodes; and liquid crystal layer sealed in a space formed between the lower and the upper substrate. Each of the scanning signal lines is formed so as to form the gate electrode of a corresponding thin-film transistor, the scanning signal lines are formed by processing a metal film of columnar crystal grains, and the surface of the metal film is coated with a self-aligned oxide film.

Abstract: Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

Abstract: A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.

Abstract: The invention relates to a transistor having a ramped gate oxide thickness, a semiconductor device containing the same and a method for making a transistor.

Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a silicon dioxide layer and a silicon nitride layer are successively formed on the surface of a silicon substrate. These layers are patterned by etching to form a plurality of parallel barrier strips extending along a first direction on the surface of the substrate. Impurities are then implanted into the silicon substrate by using the barrier strips as masks, to form a plurality of buried bit lines in the areas between the barrier strips. Next, insulating sidewall spacers are formed on the sidewalls of the barrier strips. A metal silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process. A thick dielectric layer is then formed overlying the barrier strips, the insulating sidewall spacers, and the metal silicide layer.

Abstract: A SIMOX substrate 1 is processed through high temperature oxidation treatment after forming a mask-pattern 3 to shield specified electrodes from oxidation in order to increase partly a thickness of a buffed oxide layer 2 to form an area 4. Next, after an oxide film is removed from the surface of the substrate and LOCOS separation is practiced, MOSFET is produced by fabricating a source S and a drain D on the area 4 or the buffed oxide layer 2. Since the buried oxide layer corresponding to electrodes parts influenced by disadvantages of parasitic capacitance are thickened, an operation speed of an inverter is not much decreased and since mean thickness of the buried oxide layer can be thinner, a decrease of a drain electric current by negative electrical resistance can be suppressed. Furthermore, since the thickness of the buffed oxide layer can be controlled in response to each device, plural devices having different breakdown voltages are formed together on the same substrate.

Abstract: A method of forming a semiconductor device comprises the steps of forming a patterned pad oxide layer having a first nitrogen concentration over a semiconductor substrate assembly such as a semiconductor substrate. The substrate is oxidized to form field oxide which also forms an area of Kooi nitride at the interface of the field oxide and the active area. The Kooi nitride comprises a second nitrogen concentration which is less than the nitrogen concentration of the pad oxide. Next, the pad oxide and the Kooi nitride are oxidized thereby forming gate oxide over the pad oxide. The nitridized pad oxide oxidizes slower than the Kooi nitride, and therefore gate oxide thinning which is known to result from Kooi nitride is reduced or eliminated. Further, the need for the growth of a sacrificial oxide layer to remove the Kooi nitride, and a subsequent strip of the sacrificial oxide is eliminated thereby reducing thinning of the field oxide.

Abstract: The present invention aims to prevent the thickness of the element separation insulating film of the high voltage withstanding area from being thinned and reliability of the memory cell from being reduced. Element separation insulating films are formed on a surface of a silicon substrate. A silicon oxide film, serving as a gate insulating film of a high voltage withstanding area, is formed on the surface of the silicon substrate. A first polycrystalline silicon film is deposited on the oxide film and the element separation insulating films, and a first resist pattern is formed on the polycrystalline silicon film of the high voltage withstanding area and the low voltage withstanding area. The resist pattern is used as a mask to etch the polycrystalline silicon film. After separating the resist pattern, the silicon oxide film of the cell area is removed, and an oxide-nitride film, serving as a gate insulating film of the cell area is formed on the surface of the silicon substrate of the cell area.

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using a DPCC process. A first polysilicon layer is not removed from the circuit area, and the gate regions of a circuit transistors are formed by shorting first and second polysilicon layers. A thin tunnel oxide layer of the memory cells is formed using the same mask provided for implanting boron into the cell area of the substrate. Following implantation and without removing the mask, the gate oxide formed previously over the whole surface of the wafer is removed from the cell area; the boron implant mask is removed; and tunnel oxidation is performed to increase the thickness of the tunnel oxide by a desired amount, and to slightly increase the thickness of the oxide in the transistor area.

Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.

Abstract: A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: A semiconductor device with a trench element isolation structure having a trench element isolation film formed to have a small width at the boundary between an active region and a field region, thereby capable of obtaining an improved element isolation function while easily planarizing an insulating film formed in the trench. A thick oxide film is formed at the field region provided with no trench, thereby preventing formation of a parasitic capacitor between the semiconductor substrate and the gate electrode.

Abstract: In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.