Abstract: Aspects of a method and system for reducing the complexity of multi-frequency hypothesis testing using an iterative approach may include estimating a frequency offset of a received signal via a plurality of iterative frequency offset hypotheses tests. The iterative frequency offset hypotheses may be adjusted for each iteration. A correlation may be done between a primary synchronization signal (PSS), and one or more frequency offset versions of a received signal to control the adjustment of the iterative frequency offset hypotheses. A frequency of the received local oscillator signal may be adjusted based on the estimated frequency offset. One or more frequency offset version of the received signal may be generated via one or more multiplication, and the multiplication may be achieved via a multiplication signal corresponding to one or more frequency offsets. The frequency offset of the received signal may be estimated via the correlation.

Abstract: A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured to provide a signal representing a different phase offset based on the phase difference between the RE input signal and the RF reference signal; and a switch configured to receive an output of each of the plurality of phase detectors and configured to select the output representing the phase offset, that is closest to a phase of an output of an amplifier.

Abstract: A mobile wireless communications device includes a circuit board carried by a housing. A microprocessor, RF transceiver and circuitry are carried by the circuit board and operative with each other. Clock buffer circuitry is carried by the circuit board and connected to the RF transceiver and circuitry and microprocessor for isolating a clock signal from the noise of the microprocessor and allowing greater isolation for the RF transceiver from RF circuitry.

Abstract: A radar system has a phased-array antenna and plural local oscillators for controlling local transmit/receive units. The local oscillators are slaved to a master oscillator. The analog clock signal paths are subject to relative changes in electrical length. The electrical lengths of the signal paths are measured by phase-detecting forward- and reverse-direction clock signal flows. The phase-detected information for each signal path is a measure of the time delay. The radar command processor receives the measure of time delay and corrects the radar operation in response thereto.

Abstract: A differential clock pulse compensation is performed between the clock-pulse system (23) of a digital line-connected data interface and the asynchronous clock-pulse system (22) of a digital wireless data interface. A characteristic variable (20, 21) for the asynchronous differential clock pulse between the clock-pulse systems (22, 23) is monitored hereby. The data rate of the data (15, 16) transmitted over the line-connected data interface is adapted depending on the characteristic variable (20, 21).

Abstract: A method and apparatus for automatically correcting the frequency of a local oscillator of a receiver. A primary common pilot channel (CPICH) code sequence is generated by a CPICH code generator based on a reference cell identification signal and a frame start signal. The received despread CPICH code sequence is used to generate an estimated frequency error signal. A control voltage signal is generated by a control voltage generator based on the estimated frequency error signal. The CPICH code generator generates the CPICH code sequence based on signals received from a high speed downlink packet access (HSDPA) serving cell when HSDPA is active, or a timing reference cell when HSDPA is not active. The present invention achieves full maximum ratio combining gain when space time transmit diversity (STTD) is used, even without receiving a transmit diversity indication.

Abstract: An apparatus included a receiver for receiving an audio file signal, a decoder for demodulating the audio file signal; and a processor for polling the decoder for a loss of a phase lock in the demodulating of the audio file signal. The processor resets and reinitializes the decoder in response to the loss in the phase lock loop. The receiver includes 90 MHz radio frequency reception circuit. The decoder comprises an eight-to-four modulation EFM decoder. In the preferred embodiment, the decoder outputs a digital audio stream that conforms to a known I2S audio stream format.

Abstract: In one embodiment of the present invention, two crystal oscillator circuits are coupled in parallel to provide differing performance according to mode. Generally, a first circuit provides low phase noise and high accuracy while a second circuit provides greater phase noise within an acceptable tolerance while consuming significantly less power in a low power mode of operation. The second circuit includes an entirely separate amplifier for the low power operation that tolerates a relatively smaller input signal swing but that consumes even less power. The first circuit, which comprises selectable amplification elements, and the second circuit are coupled in parallel with selectable resistive elements and capacitive elements to provide varying amounts of amplification and filtering according to whether an operational mode is in a startup mode, a normal mode, or a low power mode of operation.

Abstract: The invention proposes an LNB using two transposition frequencies chosen on either side of the reception band so as to obtain a transposition of supradyne type and a transposition of infradyne type according to the frequency used. This choice of transposition frequencies makes it possible to have an overlap zone in the middle of the reception band which is transposed with the aid of the two oscillation frequencies but at different frequencies. This makes it possible to choose between the two transpositions in the case where the frequency transposed with the aid of an oscillator corresponds to a particularly noisy frequency.

Abstract: A multi-mode PLL frequency synthesizer of a wireless multi-mode transceiver is provided which includes a reference frequency source providing an oscillator signal with a constant reference frequency, a first frequency synthesizer subunit for converting the signal into carrier signals with frequencies in the range of a first frequency band, a second frequency synthesizer subunit for transforming the oscillator signal into carrier signals having frequencies in the range of a second frequency band, and a third frequency synthesizer subunit for converting the oscillator signal into an auxiliary signal with a fixed frequency. The auxiliary signal is used together with the carrier signals of the second frequency band to generate carrier signals with frequencies in the range of a third and fourth frequency band.

Abstract: A system and method for communicating between a base and a remote device in a security system. The base receives an audio signal from a telephone network via a panel and then frequency modulates the audio signal at a carrier frequency to generate an FM signal. The remote device receives the FM signal from the base, determines a phase error signal representing the phase error between the received FM signal and an output signal of a voltage controlled oscillator, determines a difference between the carrier frequency and a center frequency of the voltage controlled oscillator, and, if there is a difference, then changes the center frequency of the voltage controlled oscillator to match the carrier frequency of the FM signal.

Abstract: A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

Abstract: The proposed apparatus and is used for signal generation by multiplexing signals such that there appears no glitches in an output signal. The present apparatus utilizes the knowledge of phase difference between input oscillator signals being multiplexed in order to provide a glitchless output signal. The apparatus comprises a first selection circuit configured to synchronize its response to a first control signal to a next determined event of one of input oscillator signals and convey an input oscillator signal to its output in response to the first control signal. The apparatus comprises a similar selection circuit for each input oscillator signal being multiplexed. Outputs of the selection circuits may be connected to a combining circuit which combines the outputs, thus providing the glitchless output signal.

Abstract: A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.

Abstract: Techniques for generating reference signals for multiple communication systems are described. An apparatus comprises a reference oscillator, a frequency control unit, and a plurality of frequency synthesizers. The reference oscillator generates a main reference signal and may be a crystal oscillator or some other type of oscillator. The frequency control unit estimates the frequency error of the main reference signal and provides a frequency error estimate. The plurality of frequency synthesizers receive the main reference signal and generate a plurality of system reference signals for a plurality of systems. At least one (e.g., each) frequency synthesizer corrects the frequency error of the main reference signal based on the frequency error estimate from the frequency control unit. Each frequency synthesizer may include a sigma-delta modulator used to generate a divider control for a phase locked loop (PLL). The divider control corrects for the frequency error of the main reference signal.

Abstract: A receiver includes a first oscillator supplying a reference frequency signal; a reference signal generator producing a first frequency conversion signal and a local calibration signal from the reference frequency signal; a first frequency converter responsive to the first frequency conversion signal to down-convert the received signal during normal receive operation and to down-convert the local calibration signal during calibration processing; a second frequency converter responsive to a second frequency conversion signal from a second oscillator to further down-convert the received signal and the local calibration signal; a demodulator that demodulates the received signal at a demodulation frequency; and a frequency error processor that determines a frequency error from the local calibration signal at the demodulation frequency, wherein the reference signal generator adjusts a frequency of the first frequency conversion signal used during normal receive operation in response to the frequency error to compe

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: A dual path loop filter circuit for a phase lock loop is described. The filter circuit allows the filter to be integrated into a phase lock loop IC circuit without using active circuit components that may create additional noise and consume additional power. The filter circuit structure allows for a low capacitance capacitor to be used to filter out any undesired signals.

Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.

Abstract: An oscillation control device for controlling a frequency of an oscillator located at the remote site from a standard laboratory having a standard oscillator. The control device includes: a comparison section to compare a frequency of the frequency signal synchronized with a radio signal produced by a signal processing section with a frequency of a oscillation signal outputted from an oscillator to be controlled, an acquisition section to obtain, through a communication network, a comparison result which is obtained by a comparison of a frequency of the standard oscillator held by the standard laboratory and a frequency of the radio signal, a calculation section to calculate deviation between the frequency of the oscillator to be controlled and the frequency of the standard oscillator based on their comparison, and a control section to control the frequency of the oscillator to be controlled, based on the deviation calculated.

Abstract: A carrier recovery method and apparatus using multiple stages of carrier frequency recovery are disclosed. A receiver uses multiple frequency generation sources to generate carrier signals used to downconvert a received signal. An analog frequency reference having a wide frequency range and coarse frequency resolution is used in conjunction with a digital frequency reference having a narrow frequency range and fine frequency resolution. The multiple carrier signals are multiplied by a received signal to effect a multi-stage downconversion, resulting in a baseband signal. A frequency tracking module measures the residual frequency error present in the baseband signal. The measured residual frequency error is then used to adjust the frequencies of the carrier signals generated by the multiple frequency generation sources.

Abstract: A wireless transmit-only apparatus (20) has a controller (21) that responds to a user interface 25 by correlating specific user input with a corresponding characterizing transmission parameter(s) as is stored in a memory (35) and by selecting a corresponding resonant device (31 and 32). The latter devices serve to drive the PLL control input of a phase locked loop (23) to thereby influence the transmission carrier frequency of a wireless transmitter (22). In a preferred embodiment, at least one of the resonant devices comprises a mechanically resonant device such as a surface acoustic wave device, a crystal resonator, or a ceramic resonator.

Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.

Abstract: A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.

Abstract: An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LO 105 is thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filter 110 and complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL).

Abstract: Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock.

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract: A multi-band RF transceiver (100) includes a single dual band VCO (102) that is used in both transmit and receive modes of operation. The VCO's low band frequency output signal that is provided on output line (120) is multiplied by two by multiplier circuit (1302), when in the high band receive mode, as for example, when receiving a PCS or DCS signal. The VCO's high band frequency output signal provided on output line (120) is divided by two by divider circuit (130) when in the low band receive mode, as for example, when receiving a GSM signal. The single multi-band VCO (102) design provides for low susceptibility to both LO leakage and DC offset caused by radiation.

Abstract: A circuit for transmitting a signal has a first signal line and a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place. The circuit further comprises a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay. A second driver is configured for driving a second signal on the second signal line depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal. A method and computer program are also disclosed.

Abstract: The invention relates to a method for a particularly precise execution of a measurement or control action and to a corresponding controller (9). A temporally periodic synchronization signal (S, S?) generated by a receiver (9) based on a timing reference signal (Z) is divided by a switching frequency (F) generated by a timing generator (14) into a plurality of switching intervals (In). A switching command (Cn), which triggers a corresponding switching process of the action, is associated with each switching interval (In). Several measurement and control actions can be accurately synchronized by performing each action with the aforedescribed method using a common timing reference signal (Z).

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: An antenna-receiver communications system and method is provided to mechanize multibeam mobile antenna-receive subsystems. Digital beam forming for modern wideband mobile communications systems is provided. In an aspect, subsystems can simultaneously receive, acquire, track and output a multiplicity of signals from sources of different locations using a single antenna aperture from a mobile platform. The angle of arrival of a signal of interest is continuously determined. Individual phased array antenna output channels are phased aligned as required by the phased array equation and monopulse signal processing. Angle sensing and beamsteering are separated from antenna channel coherent summation. Thus, the angle sensing and beamsteering functions are not required to be computed at the data rate, but can instead be computed at a rate necessary for the beam acquisition and beam tracking function speed requirements. Signal processing computational load and system cost is reduced as compared to current systems.

Abstract: An offset determination arrangement includes a comparator device to compare an input signal with a reference value. A synchronization unit is provided to forward a comparison result of the comparator device as a function of a synchronization signal which can be generated by a synchronization clock generator. The synchronization signal includes clock pulses in which at least one clock period between adjacent clock pulses is shorter than a precedent clock period. The offset determination arrangement further includes an approximation unit to generate a compensation signal corresponding to an offset of the input signal as a function of the forwarded comparison result.

Abstract: A system, method, apparatus, means, and computer program code for improving accuracy of radio timing measurements. According to some embodiments, a wireless terminal or other wireless device can make adjustments to a measurement made from a radio transmission source by adjusting timing measurements using a weighted average and/or synchronizing its timing to the timing of this or some other radio transmission source. The adjusted measurements can be obtained for times other than when the original measurements are made. Measurements for multiple radio transmission sources can then be adjusted to a common time wherein adjustment errors due to unknown timing drift in the radio sources and wireless terminal and Doppler errors due to unknown relative velocities can be reduced or eliminated.

Abstract: A frequency synthesizer circuit generates an output clock signal having a desired frequency relationship with an input reference signal, and offers essentially arbitrary relational values and adjustment resolution within any applicable circuit limits. The frequency synthesizer includes a ring oscillator circuit that provides multiple phases of its output clock signal, a phase selection circuit to select a phase of the output clock signal for feedback to an oscillator control circuit at each cycle of the reference signal according to a phase selection sequence. The oscillator control circuit generates a control signal responsive to comparing the selected phases of the output clock signal with the reference signal, and the phase selection circuit may include a modulator to generate phase selection sequences having desired time-average values that enable arbitrary frequency adjustability.

Abstract: A reference frequency generator circuit for a radio frequency transmit and receive apparatus comprises: a first voltage controlled oscillator which is operable to produce a first reference frequency signal, a second voltage controlled oscillator which is operable to produce a second reference frequency signal, a switchable set of dividers, connected to receive the first and second reference frequency signals, and operable to produce a set of output reference frequency signals therefrom, a first subset of the set of output reference frequencies being derived from the first reference frequency, and a second subset of the set of output reference frequencies being derived from the second reference frequency, wherein the first and second reference frequency signals are not equal in frequency to the output reference frequency signals in the set of output reference frequency signals.

Abstract: A system and method for calibrating a local radio reference clock for a radio operating in a radio network having a network reference clock. The method comprises determining at the radio an offset between the local clock and the network clock, placing the local clock in a calibration mode, and calibrating the local clock using a radio link to reduce the offset.

Abstract: Local oscillator apparatus comprising communication signal terminals for a communication signal, especially in a receiver or a transmitter, and a controlled frequency oscillator for producing a local oscillator signal. The local oscillator also includes a reference frequency generator and a feedback loop for selecting and adjusting the frequency of the local oscillator signal relative to the frequency of said reference frequency signal. A first frequency divider divides the frequency of the local oscillator signal by a first division factor to produce a conversion signal, where the frequency of said conversion signal is at least approximately equal to the frequency of the communication signal, and conversion means responsive to the conversion signal converts between said communication signal and base-band signal.

Abstract: Time signals for controlling a radio clock are transmitted by a transmitter and received by a receiver as amplitude modulated time signals, formed of a multitude of time frames. Each time frame has a constant duration. These time signals are first automatically amplified. A so-called telegram of at least one received time signal is stored in a memory. At least one change of an amplitude of a time signal is determined in advance or predetermined and such amplitude change has a duration that is longer than a given or determined duration (?t). When a predetermined amplitude change begins the automatic amplification is locked-in. The present circuit arrangement for operating a radio-controlled clock is equipped with components for performing the foregoing operations.

Abstract: A variable resolution analog-to-digital converter includes a sample-and-hold circuit including a plurality of sample-and-hold units which are connected in parallel and selectively activated corresponding to a required resolution to sample and hold an analog input signal, a plurality of conversion stages connected in cascade to an output of the sample-and-hold circuit to convert an output signal of the sample-and-hold circuit to a plurality of bit signals, and a synthesis circuit to synthesize the bit signals, to generate a digital output signal.

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit forming part of the transmission PLL circuit is configured to be operable in a plurality of bands. A circuit for measuring the oscillating frequency of the oscillator circuit forming part of the transmission PLL circuit is also used for measuring the oscillating frequency of the oscillator circuit forming part of the reception PLL circuit or for measuring the oscillating frequency of the oscillator circuit for the intermediate frequency.

Abstract: A reference local oscillation signal transmission station 1 radiates a reference local oscillation signal to a service zone. A portion of the signal received by each radio slave station terminal 2 is branched and fed to an injection locked oscillator 6. As a result, a local oscillation signal which is synchronized with the reference local oscillation signal is obtained. In the slave station terminal 2, the thus-obtained local oscillation signal is fed to a transmission frequency converter (mixer) 7 and a reception frequency converter (mixer) 8. An IF band transmission modulated signal is fed to the mixer 7 for frequency conversion to a radio frequency band, and the thus-obtained radio-frequency modulated signal is transmitted. Meanwhile, a received radio-frequency modulated signal is fed to the mixer 8 for down conversion, and the thus-obtained signal is fed to an IF band demodulator 10 so as to restore an information signal.

Abstract: A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Abstract: The method of this invention for preparing a profile in W-CDMA which, using a timer value and norm value, helps a mobile unit to synchronize its signals with those of a base station, comprising providing a profile data preparing portion which cumulatively adds a new norm value to a previous cumulative value fetched from a profile memory to cause the result to be stored as a current cumulative value in a profile memory and repeat the same cumulative addition each time a new norm value is fed to said portion; furnishing the profile data preparing portion with an overflow detection ability to detect the overflow of the profile memory; and choosing, when the overflow of the profile memory is detected, a maximum writable value of the profile memory, and causing the profile memory to store said maximum writable value as a current cumulative value.

Abstract: A system and method are disclosed for dynamically selecting high-side injection or low-side injection of local oscillator mixing signals based upon an assessment of signal power within the input signal spectrum that could cause unwanted images in the processed signal. This image rejection assessment provides an advantageous basis upon which to make dynamic high-side versus low-side injection determinations.

Abstract: A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

Abstract: Systems and techniques are disclosed relating to wireless communications. These systems and techniques involve wireless communications wherein a device may be configured to recover an information signal from a carrier using a reference signal, detect a frequency error in the information signal; and periodically tune the reference signal to reduce the frequency error.

Abstract: A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

Abstract: A combination mobile phone and navigation satellite receiver comprises a circuit for correcting GPS receiver reference frequency drift by using VCO burst information periodically received by a PDC handset. A corrected GPS receiver reference frequency drift then enables faster initialization and stable operation of the position solutions made available to users. A GPS numeric controlled oscillator (NCO) receives a PDC handset VCO sample.

Abstract: A reference signal enhancement device for phase lock loop oscillator. In the reference signal enhancement device, a band pass filtering unit is coupled to a reference signal to filter high frequency noise, low frequency noise, and harmonic components of the reference signal or components with frequency exceeding a predetermined frequency in the reference signal. A signal amplification device including three amplifiers connected in series is coupled to the band pass filter to convert the filtered reference signal.