Abstract: A multi-clock-domain data input processing device preferably includes: a clock-signal-receiving synchronous circuit that generates an output clocking signal by phase-delaying a first clock signal; a data input part having a delay locked loop (DLL); and an input-processing part. The data input part preferably inputs data in response to the first clock signal and the input-processing part transfers data in response to a second clock signal having a timing different from that of the first clock signal. A clock-signal applying method for operating the multi-clock-domain data input-processing device preferably includes the steps of: applying a plurality of clock signals to a signal-receiving clock conversion part; and applying a delayed clocking signal outputted from the DLL to the remaining parts of the data input-processing device.

Abstract: A direct conversion receiving unit includes an oscillation circuit (50) whose oscillation frequency fvco is (N/(N+1))×fR, where fR is a receiving frequency. The output of the oscillation circuit (50) is divided into two parts, one of which is converted to the frequency of (1/(N+1))×fR by a divide-by-N circuit (52). Mixing the two frequencies (1/(N+1))×fR and fvco=(N/(N+1))×fR generates the frequency fR, which is supplied to conversion mixers (38 and 44) as a local input. The receiving unit requires only one oscillation circuit, and excludes all the circuits that handle a frequency higher than fR, enabling a small size and low current consumption configuration.

Abstract: When changeover switch (26) selects the output of L band filter (23), changeover switch (28) is turned off and mixer (29) is operated as an amplifier such that the oscillation frequency of local oscillator (31) is controlled based on data fed to data terminal (37) and a channel selection can be performed in mixer (32). When changeover switch (26) selects the output of V band filter (25), changeover switch (28) is turned on and a channel selection is performed based on data fed to data terminal (37) in mixer (29). With this arrangement, the need for a tuning filter is eliminated and a broadband tuner not requiring manpower for adjustments can be provided.

Abstract: An electronic tuner has an input terminal, a mixer receiving the signal fed into the input terminal, a matching circuit connected to an output of the mixer, a band-pass filter connected to an output of this matching circuit, an intermediate-frequency (IF) amplifier connected to an output of the band-pass filter, and an output terminal receiving output of the IF amplifier. These circuits are composed of balanced circuits and connected by balanced lines. The mixer has a high output impedance. For the matching circuit, the impedance of the matching circuit at the band-pass filter side is equal to the impedance of the band-pass filter at the matching circuit side. This structure can realize an electronic tuner having low power consumption.

Abstract: In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer frequency-relationship between the stepped-frequency signal (Ssf) and the tuning oscillator (LO). That is, if the stepped-frequency signal (Ssf) has a frequency Fsf, the tuning oscillator (LO) will operate at a frequency Flo=N·Fsf, N being an integer or an integer fraction.

Abstract: The present invention relates to a local oscillator balun using an inverting circuit. The local oscillator balun using an inverting circuit comprises a complementary output converting circuit for amplifying a weak signal as a single signal from a local oscillator to produce two signals; a differential amplification circuit for producing two signals having a given amplitude from the two signals of said complementary output converting circuit; and an inverting circuit for inverting the two signals of the differential amplification circuit. Thus, a complementary signal having the maximum amplification and small phase difference can be produced. Therefore, the present invention can implement the maximum gain and small local oscillating leakage of the frequency mixer in a Gilbert type high frequency double balance frequency mixer.

Abstract: A frequency generation circuit includes an oscillator (403), a comparator (413) coupled to the oscillator, a first divider (407) coupled to the comparator, a PLL (400) coupled to the first divider, a second divider (422) coupled to the PLL, a first multiplexor (409) coupled to the second divider, a third divider (408) coupled to the comparator and the first multiplexor, a second multiplexor (410) coupled to the comparator and the reference clock PLL, a fourth divider (411) coupled to the second multiplexor, a fifth divider (412) coupled to the comparator, and a seventh divider (450) coupled to the comparator. A method of operating a transceiver includes using the frequency generation circuit to provide a first clock signal, a second clock signal, a first reference frequency, and a second reference frequency for a first component, a second component, a third component, and a fourth component, respectively, of the transceiver.

Abstract: An optoelectronic phase locked loop for clock recovery in high-speed optical time division multiplexed systems. The optoelectronic phase locked loop includes a balanced photodetector through which the polarity ambiguity in error signal is resolved and the cancellation of laser noise enabling clock recovery with low timing jitter. The optoelectronic phase locked loop also includes an electroabsorption modulator as a phase detector, a lowpass filter, a variable controlled oscillator, a power divider and an amplifer.

Abstract: A frequency conversion circuit includes a first mixer for performing frequency conversion of a received signal having components disposed at first frequency intervals into a first intermediate frequency signal which has a frequency lower than that of the received signal and which has components disposed at predetermined frequency intervals, two second mixers for performing frequency conversion of the first intermediate frequency signal into a second intermediate frequency signal having a frequency lower than that of the first intermediate frequency signal. A first local oscillation signal changing at second frequency intervals different from the first frequency intervals is supplied to the firs mixer, and a second local oscillation signal having a frequency which is the reciprocal of an integer of the frequency of the first local oscillation signal is supplied to the second mixers.

Abstract: When a cellular phone terminal is powered on, it immediately receives a reference signal (non-modulated reference frequency signal for correcting a crystal oscillation circuit) for correcting the reception frequency of a radio signal transmitted from a base station at all times, and corrects the error of the reception frequency on the basis of the reference signal received. After the error of the reception frequency is corrected, the cellular phone terminal makes normal communications with the base station.

Abstract: A tuner comprises a frequency changer which converts an input signal to a predetermined fixed intermediate frequency. The frequency changer is followed by an IF filter having a filter parameter, such as center frequency, which is electronically adjustable. A controller adjusts the adjustable filter characteristic so as to achieve a predetermined desired filtering performance, such as ensuring that the filter center frequency corresponds to the desired intermediate frequency. The controller comprises a local oscillator having the same type of tuned circuit as the IF filter. A phase locked loop compares the local oscillator frequency with a reference frequency and controls the tuned circuits of the IF filter and the local oscillator.

Abstract: A receiver uses an adaptive algorithm to tune a low-cost crystal oscillator according to a temperature compensation profile so as to produce a precision master reference frequency despite temperature, initial tolerance, and aging effects. An automatic frequency control system also tunes the crystal oscillator. The adaptive algorithm adjusts the temperature compensation profile for the crystal oscillator according to the adjustments made by the automatic frequency control should a received signal's quality factor exceed that associated with the temperature compensation profile.

Abstract: A synchronization system within a dual antenna receiver employs two timing recovery loops each coupled to a different antenna input. The timing error computed within each timing recovery loop is differentiated by a high pass filter and compared to a predefined threshold indicating convergence. Both sampling rates are then synchronized utilizing the timing error from whichever loop converges first. If synchronization lock for the selected loop is lost, the other loop is selected to provide timing error to both loops.

Abstract: The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: A method and apparatus for defining and generating a digital waveform such as used for the local oscillator for a down converter in a receiver is disclosed. The method and apparatus is particularly useful where the digital waveform is not an integer submultiple of a reference signal. A plurality of different digital waveforms meeting the timing criteria but having different combinations of segments needed to meet the timing criteria are generated. Each of the digital waveforms so generated are tested in, for instance, a receiver to enable the selection of the best combination of segments.

Abstract: A phase detector having improved dynamic range, frequency range, multiplication factor range, and detector gain. The detector converts a reference signal into a square wave. The square wave signal causes a step recovery diode in a sampling phase detector to trigger on a leading edge to obtain a more consistent and more precise sampling of an oscillator signal. The phase detector includes a saturated amplifier to convert the reference signal to a square wave signal, a transformer to impedance match the amplifier with the sampling phase detector and to generate a balanced output of the square wave signal. The sampling phase detector generates a phase error signal indicative of the phase difference between the reference signal and the oscillator signal. The sampling phase detector includes balanced outputs having oppositely-phased phase error signals. A potentiometer is provided to reduce or eliminate any imbalances in the oppositely-phased phase error signals.

Abstract: The present invention provides a PLL circuit, which can make convergence at a high speed and convert an IF signal into an RF signal, and a wireless mobile station with that PLL circuit.

Abstract: A frequency tracking and locking system of a wireless microphone has a frequency selection unit selecting a predetermined frequency and outputting the predetermined frequency to the frequency data storage unit, a frequency data storage unit storing a predetermined frequency data and outputting the predetermined frequency data to the data encoding unit, the data encoding unit encoding the predetermined frequency data and outputting the predetermined frequency data to the infrared modulation transmitter, an infrared modulation transmitter transforming the predetermined frequency data to the infrared frequency data and transmitting the infrared frequency data to the data decoding unit, a data decoding unit decoding the infrared frequency data to a first radio frequency and outputting the first radio frequency to the frequency transformation unit, a frequency transformation unit transforming the first radio frequency to a second radio frequency and outputting the second radio frequency to the radio emission unit,

Abstract: An apparatus and method for detecting the presence of a signal component in an arbitrary signal, where the signal component has a desired frequency. The apparatus includes an error signal generator and a detector. The error signal generator has an input for receiving a reference signal having a reference frequency, a second input for receiving the arbitrary signal having the signal component and an output for generating a difference signal dependent upon a difference in frequency between the reference frequency and the desired frequency. The detector has an input for receiving the difference signal and an output for producing a detector signal when the magnitude of the difference signal is greater than a threshold magnitude. The detector signal indicates the presence of the signal component in the arbitrary signal.

Abstract: A multi-band RF transceiver (100) includes a single dual band VCO (102) that is used in both transmit and receive modes of operation. The VCO's low band frequency output signal that is provided on output line (120) is multiplied by two by multiplier circuit (1302), when in the high band receive mode, as for example, when receiving a PCS or DCS signal. The VCO's high band frequency output signal provided on output line (120) is divided by two by divider circuit (130) when in the low band receive mode, as for example, when receiving a GSM signal. The single multi-band VCO (102) design provides for low susceptibility to both LO leakage and DC offset caused by radiation.

Abstract: There is disclosed a frequency synthesizer having an HF synthesizer for generating a first reference frequency signal having a variable frequency in a high-frequency band as a unit synthesizer, an LF synthesizer for generating a second reference frequency signal in a low-frequency band as another unit synthesizer, and an arithmetic circuit including a mixer for receiving the first and second reference frequency signals, a divider for receiving the second reference frequency signal, a mixer for receiving the first reference frequency signal and an output signal from the divider, a divider for receiving an output signal from the mixer, a divider for receiving an output signal from the mixer and capable of switching a division ratio, and a switch for switching and outputting output signals from the dividers, wherein an output signal of the switch is outputted as a first local signal, and an output signal from the divider is outputted as a second local signal.

Abstract: Interference in a receiver caused by a beat frequency arising from mutual interference of local oscillation signals from other, proximately located receivers is prevented by changing over between an externally supplied clock signal and internal clock signal. The selected clock signal is used as the local oscillation signal of the receiver, thereby removing a difference between the mutually interfering local oscillation signals and preventing the beat interference from arising.

Abstract: A circuit configuration has a radio-frequency section with a receiving mixing stage, and has a signal processing circuit with an A/D converter, a digital filter and a frequency estimator. The frequency estimator continuously determines a first frequency correction control signal, which is representative of a frequency offset between the frequency of an IF received signal and a frequency which is characteristic of a pass band of the filter. The first frequency correction control signal is used for readjustment of the mixing frequency.

Abstract: A carrier reproducing apparatus and method enabling stable operation even at a low S/N, wherein, when phase signals are locked and exceed a predetermined value, a tracking circuit generates a signal and an oscillation frequency of a signal output from a numerical control oscillation circuit is controlled so that the phase signals do not exceed the predetermined value and wherein a down sampling circuit and an interpolation circuit convert signals having a frequency of more than twice the symbol rate to signals having a frequency of twice the symbol rate.

Abstract: The method includes deriving all receiver carrier frequencies and all transmitter carrier frequencies of the base station from a common reference frequency; comparing a transmitter carrier frequency of a subscriber station with a receiver carrier frequency in the base station to obtain an average frequency deviation; transmitting the average frequency deviation to the concerned subscriber station; adjusting the transmitter carrier frequency of the subscriber station so that the frequency deviation is minimized; when data is to be transmitted with other carrier frequencies, switching from the receiver channel and transmitter channel to other channels; and prior to switching deriving new transmitter and receiver carrier frequencies (TMTx2, TMRx2) of the subscriber station according to the following formulae: TMTx2={1/C}[BSRx2+ZFLOBS(m′−n·C)+RFLOBS(1−R)], TMRx2={1/C}[BSTx2+ZFLOBS(m−n′·C)+RFLOBS(1&mi

Abstract: A wireless communication system, which is provided with a PLL circuit having a plurality of oscillators and is capable of processing two or more transmit and receive signal different in frequency band from one another according to the switching between the oscillators, has a reset means which resets a voltage applied to each of filter capacitors lying within the PLL circuit to a predetermined voltage when the switching between the oscillators is performed.

Abstract: Methods and systems are provided for frequency generation suitable for use in wireless devices capable of operating at multiple frequencies. Such systems may change the loop gain of an automatic frequency control loop based on the operating frequency of the wireless device. Furthermore, such a frequency dependent loop gain may be carried out by the selection of subroutines with differing loop gains associated with the subroutines. Furthermore, the loop gain may also be temperature compensated based on the temperature of the wireless device and/or the operating frequency of the device.

Abstract: A method and apparatus for minimizing internal frequency errors in a crystal oscillator is disclosed. A microprocessor generates a voltage control signal in response to received inputs regarding the temperature of an associated voltage control temperature controlled crystal oscillator, a value from a default table at the detected temperature and a value from a compensation table at the detected temperature. This information is used to calculate the error for the presently applied voltage control signal. From this error, a new compensation value is calculated and entered into the compensation table at the detected temperature.

Abstract: In a circuit arrangement for demodulating an intermediate-frequency video signal generated while using a Nyquist edge, having a phase-locked loop (1) including a phase detector (3), a loop filter (4) and a voltage-controlled oscillator (5), and a video demodulator (2), the intermediate-frequency video signal being applied to the phase detector (3) and the output signal of the phase-locked loop (1) being applied to the video demodulator (2), which converts the intermediate-frequency video signal into a baseband video signal, phase fluctuations contained in the carrier of the intermediate-frequency video signal due to its generation while using a Nyquist edge are compensated in that the phase comparator (3) operates, by approximation, independently of modulation in the control range of the intermediate-frequency video signal, in that the baseband video signal is present in an inverted form with respect to the intermediate-frequency video signal, and in that a correction signal is derived from the baseband video

Abstract: An improved mixing circuit includes a MESFET having an LO signal coupled to its gate through a charging capacitor and an RF signal coupled to its drain through a first bandpass filter. Electrons are pumped onto the charging capacitor to bias the gate of the MESFET. The MESFET drain is coupled to a second bandpass filter which passes a signal at the mixed frequency.

Abstract: A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Abstract: The present invention relates to an improved demodulator for locking onto and tracking a carrier. Harmonic frequencies are occasionally generated by demodulation circuitry. When this occurs, the harmonic frequencies can interfere with the demodulator's locking and tracking functions, especially if the harmonic frequencies are near a down converted carrier's frequency. A system and method are disclosed which provides an offset to a frequency synthesizer whose output frequency is used to down convert the carrier. The offset alters the frequency of the down converted carrier so as to shift it away from the interfering harmonics. In this regard, the demodulator is enabled to lock onto and track a carrier when previously not possible.

Abstract: An improved local synchronization module which uses Frequency-phase adaptive double locked loop (FPADLL) to control a stable controllable oscillator is disclosed. A single physical feedback loop is implemented which can operate in either a phase locked loop mode or a frequency locked loop mode. The sync module includes a controller which determines in which mode the feedback loop operates. The controller also uses slipping information from a network reference recovery interface to reduce slipping. Also effects of ageing of the stable controllable oscillator are predicted and compensated for.

Abstract: A tuner circuit comprising a first frequency conversion means 14 for converting a high frequency input signal into a first intermediate frequency signal according to a first local oscillation signal, a second frequency conversion means 19 for converting the first intermediate frequency signal from the first frequency conversion means 14 into a second intermediate frequency signal according to a second local oscillation signal, a first PLL means 24 for controlling the first local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal having a fixed frequency, a second PLL means 31 for controlling the second local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal. In the first PLL means 24, a phase comparison frequency is set to a frequency higher than a specified value. In the second PLL means 31, a phase comparison frequency is set to a frequency lower than a specified value.

Abstract: A new architecture for such a type of synthesizer is proposed not having the drawbacks of such known synthesizers and having the same phase noise properties as ordinary integer divide by N synthesizers. The novel architecture has a main PLL with a first integer frequency divider in its feedback loop and further an auxiliary PLL having a second integer frequency divider in its feedback loop.

Abstract: In a receiving apparatus intermittently receiving modulated and transmitted information, a controller controls a supply of source voltage to a synchronization correcting signal generator and a PN code generator for accurately demodulating the intermittently received modulated information and to an information demodulator and an information decoder to be carried out at a timing independent of each other, by which the information demodulator and the information decoder can be driven once while the synchronization correcting signal generator and the PN code generator are driven N times in synchronizm with a timing for driving the synchronization correcting signal generator and the PN code generator.

Abstract: A radio device has an antenna for receiving a radio frequency signal, and a radio frequency mixer for down-converting the received radio frequency signal to an intermediate frequency signal. The radio device further has a frequency synthesizer for generating a local oscillator signal for the radio frequency mixer. The frequency synthesizer has a first local oscillator loop for producing a band selective local oscillator signal, a second local oscillator loop for producing a channel selective local oscillator signal, and a local oscillator signal mixer for mixing the band and channel selective local oscillator signals. The band selective local oscillator signal selects a band, and the channel selective local oscillator signal selects a channel within the band. The generated local oscillator signal is an output signal of the local oscillator signal mixer.

Abstract: A receiver is provided capable of receiving both RDS (Radio Data System) and DARC (DAta Radio Channel) system FM multiplex broadcasting. An RDS signal demodulating circuit is provided with a PLL circuit which comprising a first frequency divider for dividing an output of a crystal oscillator, a phase comparator for inputting an output of the first frequency divider, a low-pass filter connected with the phase comparator, a VCO connected with the low-pass filter, and a second frequency divider for dividing an output of the VOC and outputting the divided output signal to the phase comparator. An output of the VCO is transmitted as a reference clock RDSCL for demodulation of an RDS signal.

Abstract: A high frequency apparatus for receiving digital modulated high frequency signal which withstands vibration and is easy to adjust for tuning, yet presents clear oscillation signal. The invented apparatus has an input terminal(101), a mixer(104) which receives at one input the signals supplied to input terminal(101) and at the other input an output signal of local oscillator(103), and output terminals(107,108) to which the output signal of mixer(104) is delivered. A voltage controlled oscillator constituting said local oscillator(103) has an oscillating section and a tuning section; the tuning section has a movable conductive member(119) and a gluing agent(120) for maintaining a state after adjustment. Control loop has a high loop band width which is large enough so as the noise of local oscillator(103) is not dominated by noise of the above mentioned voltage controlled oscillator.

Abstract: A high frequency apparatus for receiving digitally modulated high frequency signals withstands vibration and has a simple tuning adjustment. The apparatus has an input terminal, a mixer which mixes the input signals and an output signal from a local oscillator, a voltage controlled oscillator which includes the local oscillator, an oscillating section, a movable conductive member and, a gluing agent for maintaining an adjusted state, and a control loop having a high loop band width which is large enough so that noise of the local oscillator is not dominated by noise of the voltage controlled oscillator.

Abstract: In a method for realizing carrier wave synchronization in the receptio of a multi-level, two-dimensional modulation signal, the received signal is demodulated by using at least one local oscillator (3) in order to generate the local oscillator frequency. In the method, the local oscillator (3) performs a frequency scanning within the frequency range of the reception; during the frequency scanning, a demodulated signal point system is formed of the received signal by using the frequency generated by the local oscillator (3). Furthermore, the demodulated signal point system in the method is examined in order to determine at which point of time the frequency of the local oscillator is synchronized to the carrier wave frequency of the received modulation signal.

Abstract: A receiver has an oscillator for generating an oscillating signal at an oscillating frequency in accordance with an oscillation control signal, and receives a radio signal at a tuning frequency corresponding to the oscillating signal to demodulate the received radio signal. The receiver further includes a first frequency control loop system for generating a first control signal indicative of the difference in phase between a comparison signal generated by dividing the oscillating signal on the basis of the information on a channel selection frequency and a reference signal, and a second frequency control loop system for generating a second control signal indicative of a frequency difference between the oscillating frequency of the oscillating signal and the channel selection frequency. Either the first control signal or the second control signal is selectively supplied to the oscillator as an oscillation control signal.

Abstract: A frequency synthesizer circuit comprises a controller, a synthesizer and a voltage controlled oscillator are used to generate an oscillating signal in response to external commands. The synthesizer provides a lock detect signal to the controller when the synthesizer detects that the oscillating signal has reached a desired frequency following application of a load signal. A first timer, a second timer, and a counter are adapted to receive the load signal and the lock detect signal. The first timer provides a first measurement corresponding to an amount of time between the load signal and a first receipt of the lock detect signal. The second timer provides a second measurement corresponding to an amount of time between the load signal and a final receipt of the lock detect signal. The counter provides a count value corresponding to a total number of times that the lock detect signal is received inclusive of the first receipt and the final receipt of the lock detect signal.

Abstract: A communication system is provided for increasing communication range between at least two radio communication devices without increasing the output power of transmitted radio signals from the devices, and without increasing the antenna gain of the received signals. Each radio device includes an oscillator for generating a carrier reference signal, and an SATPS receiver which receives at least one standard timing reference signal from at least one SATPS satellite. The received standard timing reference signal is used to continuously adjust the timing and synchronization of the oscillator to improve the accuracy of the carrier frequency signal. The improved accuracy in the carrier frequency signal may then be used to reduce the bandwidth of the modulated carrier frequency signals generated by the radio device to thereby increase the effective communication range and sensitivity of the device.

Abstract: A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.

Abstract: A carrier phase synchronizing circuit is disclosed, that comprises an AFC loop and a PLL, the AFC loop including an AFC complex multiplexing device, an LPF, a PLL complex multiplying device, a phase detector, a loop filter, an AFC filter, and a NCO, the PLL including a PLL multiplying device, a phase detector, a PLL filter, and a NCO. A loop range, a frequency control width, and a control time interval of each of the AFC filter and the PLL filter are controlled corresponding to a time change amount of the frequency error that is detected in the PLL.

Abstract: In a radio transmitter-receiver, a single frequency conversion method is used at a side of transmission and a double frequency conversion method is used at a side of reception. The frequency for transmission is identical with that of reception. A common oscillator of an oscillation frequency f1 is used for a local frequency for transmission/reception-first frequency conversion. A reception second local frequency signal and a transmitter intermediate frequency signal are generated by independent oscillators with oscillation frequencies 2f2 and 2f3 respectively. These oscillators generate two times the frequency of the conventional example thereof, thus providing the signals with frequency of 1/2 times the frequency-division by the frequency dividers for the reception side second frequency converter and transmission side intermediate frequency converters respectively.

Abstract: An automatic frequency control system for use in satellite communications is provided that is pre-programmed with an initial acquisition Doppler offset frequency. The system includes a search mode for accurately determining the satellite's initial frequency translation error before the initiation of data transmission and also for determining the Doppler rate of change. The system further includes a tracking mode, in which the frequency variation is continuously monitored. Depending on the frequency characteristics of the transmission, the system is capable of re-entering the search mode to determine a new frequency translation error, if necessary.

Abstract: A digital audio broadcasting (DAB) system includes a radio-frequency (RF) transmitter and a corresponding RF receiver. The RF transmitter transmits an RF DAB signal that includes a pilot signal at 250 Khz. An RF section of the RF receiver includes a phase-lock-loop (PLL) to compensate for any carrier frequency differences in the received RF DAB signal. This PLL tracks the phase of the received RF DAB signal when an amplitude of a recovered IF signal is above a predetermined threshold and upon detection of the pilot signal.

Abstract: Within a communication system, driving a numerically controlled oscillator with a frequency of a precision frequency oscillator and adjusting the frequency of the numerically controlled oscillator by a calculated number to be equal to that of a frequency signal derived from an external source. The calculated number utilized to adjust the numerically controlled oscillator is then transmitted to each of a number of subunits. Each subunit has another numerically controlled oscillator that is driven by a frequency derived from an internal communication link connecting the subunit to the communication system; and the other numerically controlled oscillator is controlled by the calculated number so that its frequency matches the frequency of the precision oscillator. The frequency of the internal communication link is controlled by the precision oscillator.