Abstract: A digital television receiver includes a tuner for down-converting an incoming signal to produce a down-converted signal according to a local oscillator signal corresponding to a selected channel. A filter is coupled to the tuner for filtering the down-converted signal to produce an intermediate frequency (IF) signal. A carrier recovery unit is coupled to the filter for locking to a carrier frequency of the IF signal, and a pre-shift unit is coupled to the tuner. By shifting the local oscillator signal in a first direction by a predetermined first frequency shift in a first phase of carrier recovery, and then by shifting the local oscillator signal in a second direction by a second frequency shift in a second phase of carrier recovery, the pre-shift unit ensures a pilot tone of a selected channel is not filtered from the down-converted signal by the filter.

Abstract: A method and apparatus for compensating for frequency drift in an LNB by storing the frequency offset of each LNB with respect to each channel. When a channel is selected, a particular LNB is activated and the table of offset values is consulted. The offset value for the LNB and channel is used to tune the LNB to a frequency that is appropriate for receiving the selected channel.

Abstract: A method for adjusting a phase difference between a received code modulated signal and a replica code sequence where, in order to enlarge the control range, it comprises a step of determining measurement values representing a phase difference between a received code modulated signal and a generated replica code sequence. The proposed method further comprises determining coefficients for a loop filter operation, which coefficients optimize a predetermined function specified for current properties of the received signal. Then, a loop filter operation is applied to the measurement values to obtain an indication of a required correction of a current frequency of the generated replica code sequence, which loop filter operation utilizes the determined coefficients. Finally, the frequency of the generated replica code sequence is adjusted based on the indication of a required correction. The invention relates equally to a corresponding unit and to a corresponding system.

Abstract: A method and system for estimating a frequency offset between a receiver and a transmitter, including the steps of, or means for: (a) receiving a first signal from said transmitter and demodulating the first signal; (b) performing a frequency shift on said first signal by a predetermined frequency factor to generate a second signal; (c) filtering each of said first and second signals; (d) determining the power of each of the filtered first and second signals; (e) determining an upper corner frequency value of the first signal using the power of the filtered first and second signals; (f) determining a lower corner frequency of the first signal using the determined power of the filtered first and second signals; and (g) determining a frequency offset value based on said upper corner frequency value and said lower corner frequency value.

Abstract: A direct conversion receiver includes a local oscillator for generating a sinusoid, a mixer for receiving an incoming signal and for mixing the incoming signal with the sinusoid, an analog-to-digital converter for converting the mixed analog signal into a digital signal, and a digital signal processor for outputting the digital signal so that an I-channel signal and a Q-channel signal are output separately and for transmitting to the local oscillator a phase control signal that determines the phase of a sinusoid to be generated by the local oscillator. The direct conversion receiver may further include a low noise amplifier for amplifying the incoming while preventing noise included in the input signal from being amplified, a baseband amplifier for amplifying the mixed analog signal in a baseband, and a baseband low pass filter for removing low frequency noise from a signal amplified by the baseband amplifier.

Abstract: A television tuner includes a surface acoustic wave filter that receives input of an intermediate-frequency signal; an integrated circuit for detecting the intermediate-frequency signal, the integrated circuit including a video detector and a voltage-controlled oscillator that supplies a local oscillation signal for synchronous detection to the video detector; and a tank circuit that is provided externally to the integrated circuit and that is connected to the voltage-controlled oscillator. The integrated circuit has balanced input terminals associated with a first edge, and two connecting terminals associated with a second edge opposite to the first edge. The balanced input terminals are connected to output terminals of the surface acoustic wave filter, and the connecting terminals are connected to the tank circuit.

Abstract: A frequency generator which can perform stable frequency oscillation unaffected by temperature variation. A frequency generator having a differential amplifier (1) having an LC resonance circuit (10) as a load and buffer circuits (21, 22) feeding back an output of the differential amplifier to its input, wherein a temperature coefficient converter (5) converting an output voltage of a reference voltage generator (4) and its temperature dependence to a voltage having a predetermined voltage and temperature coefficient and outputting it is provided to control bias currents IEF of emitter follower circuits to be in proportion to temperature variation. There are a characteristic in which delay time of the emitter follower circuits constructing the buffer circuits is in inverse proportion to a transconductance of transistors and a characteristic in which the transconductance is in inverse proportion to temperature and is in proportion to the bias currents IEF.

Abstract: A bimodal power data link transceiver device (33) is provided. The device comprises a transceiver integrated circuit (IC) (14); wherein the IC comprises an oscillator (150), a frequency reference port, and a RF output port. A VCO (12) is coupled to the oscillator and a direct digital synthesizer (15) is coupled to the frequency reference port. The combination allows the IC to operate below 200 MHz. In addition, an external power amplifier (19) is connected to the RF output port thus allowing for burst RF communications at a higher power than the quiescent receive mode.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: An impulse waveform generating apparatus comprises an oscillator for generating a reference signal having a center frequency in a frequency band of an impulse to generate, a timing matching circuit for shifting a phase of the reference signal by 90 degrees, a frequency demuultiplier for dividing a frequency of the phase shift signal and obtaining a timing signal having a frequency component having a frequency width of an impulse to generate, a memory storing a waveform shape table, a waveform forming section for forming a waveform in synchronism with the timing signal, according to information of a shape table having a predetermined waveform, a low-pass filter for obtaining an envelope signal from an output signal of the waveform forming section, and a waveform generating section for changing an amplitude of the reference signal according to a value of the envelope signal.

Abstract: A communication semiconductor integrated circuit device includes an RFVCO and a TXVCO and is formed over one semiconductor substrate, and has a first operation mode (idle mode) which does not perform transmission and reception, a second operation mode (warmup mode) which performs a preparation prior to the start of transmission or reception, and a third operation mode (transmission or reception mode) which performs transmission or reception. In the first operation mode, two oscillators are deactivated, and the operation of selecting a frequency band to be used in at least the TXVCO which generates a transmit signal, is performed in the second operation mode.

Abstract: A method and an arrangment for reducing phase jumps in a frame synchronization signal when switching between synchronization signal when switching between synchronization reference sources are disclosed. A new reference signal to which each of the two reference sources (signals) are phase locked, and has frequency n times the respective reference signal, is generated. A selection signal selects the new reference signal to be used, and the selected one is then divided back to its original frequency creating an input signal to a phase-locked loop generating the resulting frame synchronization signal. In this way, the maximum phase jumps are reduced from one period of the original reference signals to one period of the new reference signal. The invention is particularly applicable for reducing phase jumps on a master frame synchronization signal in a PDH system.

Abstract: A method and apparatus for synchronizing a local clock value in a wireless receiver receiving a data unit containing synchronization information. The method includes receiving a first data unit containing synchronization information, extracting the synchronization information from the received first data unit, copying a local free-running clock at a known reference point in time relative to the time the first data unit was received to generate a local timestamp; and calculating an offset to the free-running clock using the extracted synchronization information and the local timestamp, the calculating in non real-time, such that the sum of the calculated offset and the value of the free-running clock provides a local clock value that is approximately synchronized in time. The apparatus implementing the method is part of a node of a wireless station, and provides a time synchronization function, typically at the MAC layer.

Abstract: Disclosed is an oscillator circuit (10) for use in a local oscillator of an RF communications device (100) that communicates over an RF channel. The oscillator circuit includes an oscillator transistor coupled to a power supply voltage (Vcc) through a buffer transistor, and a biasing network having bias voltage outputs coupled to a control input of the oscillator transistor and to a control input of the buffer transistor. In one embodiment the bias voltage network is coupled to Vcc, while in another embodiment the bias voltage network is coupled to a separate voltage (Vbias). Circuitry is provided for setting a magnitude of Vcc and/or Vbias as a function of at least one of RF channel conditions, such as channels conditions determined from a calculation of the (SNR), or an operational mode of the RF communications device. The magnitude of Vcc (and Vbias) may be set between about zero volts (i.e., turned off) and some maximum value.

Abstract: The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained.

Abstract: Systems and methods for reducing interference in an enhanced radio receiver from a transmitter when both are located in the same aircraft are provided. The enhanced radio receiver detects and attenuates a signal from the transmitter, without attenuation or interference with other desired signals. An enhanced radio transmitter may inform the enhanced radio receiver of the frequency of transmission via a data communication path such that the enhanced radio receiver attenuates the transmitted frequency for the duration of transmission.

Abstract: An RF power oscillator for contactless card antennas shapes a carrier signal at the operating frequency utilizing a delay circuit having a number of taps for delaying the carrier signal by different lengths of time. The delayed signals are input into a buffer and output through impedance elements to a node coupled to the antenna. The resulting waveform for a square wave input signal, and equal-length delay taps, is a trapezoidal wave output. Any input wave form can be shaped in a variety of ways depending upon the combinations of delay taps used. Since the buffer drivers for each delayed wave switch state at slightly different times, the amplitude and bandwidth of emitted electromagnetic interference (EMI) is reduced for the transmission circuit.

Abstract: A carrier recovery method and apparatus using multiple stages of carrier frequency recovery are disclosed. A receiver uses multiple frequency generation sources to generate carrier signals used to downconvert a received signal. An analog frequency reference having a wide frequency range and coarse frequency resolution is used in conjunction with a digital frequency reference having a narrow frequency range and fine frequency resolution. The multiple carrier signals are multiplied by a received signal to effect a multi-stage downconversion, resulting in a baseband signal. A frequency tracking module measures the residual frequency error present in the baseband signal. The measured residual frequency error is then used to adjust the frequencies of the carrier signals generated by the multiple frequency generation sources.

Abstract: An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL). A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

Abstract: An arbitrary number of signaling beacons are synchronized simultaneously and automatically by a received modulated control signal in accordance with an arbitrary communication protocol over a communication link which may be separate from or superimposed upon a perceptible signal periodically provided from signaling beacons. The periodic perceptible signal may be stabilized using a crystal oscillator or an external transmitted signal such as a global positioning system (GPS) signal and synchronization thus maintained for extended periods of time even when the synchronization communication link is not available. Interference is substantially prevented by the communication protocol while supporting the provision of any desired beacon control functions.

Abstract: A mobile communication terminal includes (a) a first unit for calibrating a frequency, (b) a global positioning system (GPS) module, and (c) a processor which electrically connects the first unit and the global positioning system module to each other. The first unit counts the number of an intermediate frequency (IF) signal generated by converting a frequency of a signal transmitted from a base station, the processor coverts a count of the intermediate signal obtained while the first unit is in lock-up condition, into a real count offset, and the global positioning system module counts the number of a signal transmitted from a circuit which generates an operational frequency of the mobile communication terminal, and calibrates the number of the signal with the real count offset.

Abstract: DC offset is estimated in a wireless receiver during a period when receive energy is blocked from reaching a mixer within the receiver. The estimated DC offset value may then be used to reduce DC offset within the wireless receiver when a receive signal is subsequently being processed.

Abstract: A radio communication unit employs passive devices and a loop filter to receive a coded frequency modulated wakeup or synchronization signal that enables the receiving radio unit and initiates communications. The loop filter simultaneously tracks phase and frequency and provides smoothing to enable synchronization with weak signals (e.g., signals that typically do not enable a standard phase locked loop (PLL) to lock). In particular, when the communication unit is in a standby mode, the passive circuits of the present invention are receiving energy from a unit antenna and initially function as a phase locked loop (PLL) to lock onto an incoming signal. The wakeup or synchronization signal includes a series of tones at different frequencies, where the specific sequence is prearranged between the transmitting and receiving units. When each tone in the sequence has been detected by the receiving unit, the unit is enabled for communications.

Abstract: An electronic system for accurately controlling the RF output power from a power amplifier (21) is implemented using a multiplier (28) which multiplies the output power by itself to provide a DC component which is fed to a variable gain amplifier (29) which provides a controlling signal via a comparator (24) and an integrator (25) to the power amplifier. The transfer function between controlling signal and output power is substantially linear, even during dynamic variation of the controlling signal. The system is capable of a large dynamic range, and exhibits constant control loop bandwidth over this range. This is of particular use to TDMA applications with a large dynamic range of levelled output powers because a fixed filter function can be used to shape the transmitted burst.

Abstract: A control unit measures a phase error between a reference timing of a mobile station and a reception timing from a base station based on reception data from a reception unit and a count from a reference timing counter unit, determines a frequency deviation correction value calculation period corresponding to the measured phase error, and outputs it to a frequency deviation correction value calculation unit. The frequency deviation correction value calculation unit does not calculate a deviation at every reception time when intermittent reception is repeated, but calculates a deviation at intervals following the frequency deviation correction value calculation period given from the control unit.

Abstract: A radio communication apparatus includes a low-rate clock oscillator for generating a low-rate clock signal used for reception timing estimation; a frequency deviation measuring duration controller for determining a deviation measuring duration of measuring a frequency deviation of the low-rate clock signal in accordance with an intermittent time interval of the radio signal; a frequency deviation measuring section for measuring the frequency deviation of the low-rate clock signal over the deviation measuring duration; and a timing counter for correcting the frequency deviation of the low-rate clock signal, for measuring an intermittent span of the received signal in response to the low-rate clock signal after the correction, and for generating the estimated reception timing of the radio signal.

Abstract: A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

Abstract: A variable frequency oscillator comprising: an oscillatory circuit for generating a periodic output dependent on the capacitance between a first node and a second node of the circuit, and having a capacitative element connected between the first node and the second node; the capacitative element comprising: a variable capacitance unit, the capacitance of which is variable for varying the frequency of the output and a plurality of finite capacitances each being selectively connectable in parallel with the variable capacitance unit between the first node and the second node to trim the frequency of the output.

Abstract: An integrated demodulator tuning circuit (10, 60) receives differential currents at input terminals (12, 46) and provides an AFC signal at an output terminal (48). The AFC current characteristic has a dead band (72) in the output current generated when the integrated demodulator tuning circuit (10, 60) operates under the condition where the difference between the currents supplied at the input terminals (12 and 46) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (14, 16 and 20, 36, 38 and 40) that form the current mirrors connected to the input terminals (12, 46).

Abstract: A receiver has an adder for output intermediate-frequency signals of a plurality of receiving blocks, a demodulator for an added intermediate-frequency signal, adjustable reference-signal generator for supplying phase-shifted reference signals to the PLL circuits of the plurality of receiving blocks, and a plurality of switches. The switches are controlled when power is first supplied to the receiver such that the frequency-divided reference signals to the PLL circuits are in phase with one another. The adjustable reference-signal generator, upon tuning on power, is set in the phase-shift adjusted state stored immediately before previously turning off the power.

Abstract: Transmitter frequency locking across a full duplex communications link. An offset in one transmitter results in an offset at the corresponding receiver. That receiver offset shifts its transmitter in a corresponding manner, causing a correcting offset in the first receiver, which is used to correct the first transmitter. A first embodiment uses filtered received frequency information derived from a baseband demodulator to correct transmitter frequency. A second embodiment uses filtered frequency information from a frequency detector to correct transmitter frequency.

Abstract: The invention relates to a receiver arrangement for receiving frequency-modulated radio signals, having a demodulator circuit arrangement (18), which converts and intermediate-frequency signal into a voltage signal, which is applied to an input stage (22) of a signal-processing circuit arrangement (23), and having a clock-signal oscillator (26), which supplies a clock signal for generating a frequency signal for reducing the frequency of a received signal to the intermediate frequency, and relates to a method of adapting a receiving branch of the receiver arrangement to an input stage (22) of a signal-processing circuit arrangement (23) and a self-testing method. To allow the adaptation of the demodulator circuit arrangement to the downstream input stage of a signal-processing circuit arrangement to be carried out without external test signals, a test-signal generator stage (28) is provided, which forms a test signal with a known frequency from the clock signal supplied by the clock-signal oscillator (26).

Abstract: An oscillator 10 includes temperature compensation circuits 30 and 40, a frequency adjusting circuit 50, and an initial deviation correcting circuit 60. Switches SW 1 to 4 are controlled based on control data DC stored in a memory 90 so that a temperature compensation voltage V1, a temperature compensation voltage V2, a frequency adjusting voltage V3, and an initial deviation correcting voltage V4, output from the above circuits, are selectively added, supplying a sum to a voltage-controlled oscillation circuit 20 as a control voltage VA.

Abstract: A frequency plan for a signal analysis circuit includes operational parameters that are selected on the basis of first intermediate frequency (IF) filtering characteristics that are uniquely identified for the circuit. That is, rather than selecting a frequency plan based upon an original design of the circuit and circuit layout, actual IF filtering characteristics are considered. The center frequency of the passband of the first. IF filter may be measured and then used as an important factor, along with inhibiting spurious responses, in a devising the frequency plan for the specific circuit.

Abstract: A method and systems to evaluate the propagation delay within a semiconductor chip (305) that is embedded in an electronic system without requiring measurement apparatus and specific electrical contacts is disclosed. Since most of electronic systems use a microprocessor, the basic principle of the invention consists in using the microprocessor capabilities to measure the propagation delay of a chip embedded in such an electronic system. Thus, according to the invention, the microprocessor transmits an instruction to the semiconductor chip that performs propagation delay evaluation and then read the result in a dedicated memory register (415) of the chip. As a consequence, the chip does not require dedicated pins and measurement apparatus. In order to measure the propagation delay, the chip comprise a logic path (400) wherein propagation delay is created, then a rising edge detector (405) is used to analyze logic path signals, A counter (410) based on a system clock is used to measure propagation delay.

Abstract: The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: A receiver having a phase-locked loop (PLL) for synchronizing its oscillator with a carrier (CA). A calibration circuit (CAL) calibrates the phase-locked loop's oscillator (OSC) in the following manner. It measures (FMC) the frequency difference (dF) between a nominal frequency (Fnom) of the carrier (CA) and a frequency (Fosc) of the phase-locked loop's oscillator (OSC). Furthermore, it adjusts the frequency (Fosc) of the PLL oscillator in accordance with the measured frequency difference (dF). As a result, the phase-locked loop's oscillator will be substantially tuned to the nominal frequency of the carrier. The actual frequency of the carrier may differ from the nominal frequency. In general, such a difference will be sufficiently small for the phase-locked loop (PLL) to capture the carrier (CA).

Abstract: A wireless telephone system comprises a base unit having a base transceiver, and one or more wireless handsets, each handset comprising a handset transceiver. Each handset establishing a time-division multiple access (TDMA) link over a shared RF channel with the base unit via the base transceiver in accordance with a TDMA epoch, which allocates exclusive data and audio packet time slots to each handset. Each handset powers on its transceiver during its respective data and audio packet time slots as necessary to synchronize with the base unit using synchronization data transmitted with a data packet, to detect incoming call data transmitted with a data packet, or to transmit and receive audio information over the TDMA link. The handset powers off its transceiver otherwise during the epoch to minimize handset power use.

Abstract: Fast switching and fast settling is achieved in a phase locked loop (“PLL”) containing a bandwidth switched active loop filter (8) by feeding the phase error signal of the phase detector (1) of the PLL to the non-inverting input of the amplifier (7) within the loop filter and having the electronic switch (17) control the loop filter bandwidth through changing the resistance (9, 11) to ground at the inverting input of the amplifier between a high and low value associated respectively with broad bandwidth and narrow bandwidth to the loop filter. Switching is possible in as little as one microsecond, and is accompanied by fast settling of the loop with minimal generation of phase/frequency perturbation. The foregoing PLL is of particular benefit in fast switching frequency synthesizers, such as used in frequency hopping frequency synthesizers of frequency and time division multiplexing systems.

Abstract: A synchronization system within a dual antenna receiver employs two timing recovery loops each coupled to a different antenna input. Segment sync lock (detection of a segment sync in the data stream) by one timing recovery loop prompts selection of the timing error from the corresponding timing recovery loop for timing recovery within both loops. Both timing recovery loops are then synchronized utilizing the selected timing error. If sync lock for the selected loop is lost, the other loop is selected to provide timing error to both loops.

Abstract: Techniques for inner/outer loop tracking that is stable and provides desirable loop convergence characteristics are disclosed. In one aspect, the contribution from any one inner loop to the tracking function of the outer loop is limited, to prohibit any one received signal component from dominating the outer loop. In another aspect, the rate of outer loop tracking variation is controlled to provide inner and outer loop stability. Various other aspects are also presented. These aspects have the benefit of providing stable inner and outer loop control, as well as efficient convergence and tracking by the various loops, resulting in reduced frequency error and improved communication performance.

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: A method and apparatus to perform a real-time drift correction of a local oscillator in a wireless device such as a cordless telephone, and/or to perform software-based frequency tracking of the local oscillator. With respect to the real-time drift correction, the remote handset periodically wakes from a sleep mode and goes into a normal link verification mode. Once in the link verification mode, the remote handset enters a time division duplexing (TDD) mode and attempts to establish a link with a base unit based on the timing of the TDD data frame. After the remote handset establishes a link with the base unit, the remote handset requests a security word from the base unit. Upon receiving the requested security word, the remote handset determines if the requested security word matches a security word of the remote handset. The remote handset implements a software frequency adjustment of its local oscillator.

Abstract: In order to improve the performance of a feed back comprising a loop filter in terms of loop selectivity, stability and robustness the loop filter is being provided with a slew rate limiter.

Abstract: A device and a method for contactless transmission of data or power include an impedance which is connected into an LC resonant circuit only in a phasewise manner, in order to match a resonant frequency of the resonant circuit to an excitation frequency. This is realized by measuring a difference between the resonant frequency and the excitation frequency and connecting the impedance into the resonant circuit as a function thereof in a manner controlled by a charging current. In this case the charging current is phase-gating-controlled, and consequently only an effective component of the impedance is connected into the resonant circuit.

Abstract: A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame.

Abstract: The present invention provides methods and apparatus for integrating the operation of a plurality of radio networks. The plurality of radio networks may utilize a common frequency spectrum. The radio center frequencies are adjusted so that frequency drift in relation to each radio network is reduced. Also, system information about the plurality of radio networks may be sent on a radio channel that is associated with one of the radio networks. An oscillator synchronizer synchronizes a first reference oscillator that is associated with a first radio network and a second reference oscillator that is associated with a second radio network in order to adjust radio center frequencies. With a variation of the embodiment, a reference oscillator of one of the radio network adjusts center frequencies for radios that are associated with the other radio network.

Abstract: A frequency tracking circuit and method comprising a master crystal oscillator circuit is used for frequency tracking between a handset and a base station comprising a calibration subsystem for taking a temperature measurement, a reference control circuit for determining a numerical value needed to align a handset frequency with a base station frequency, an adder for adding the numerical value to a previous numerical value determined by the reference control circuit, a latch for latching the output of the adder, and a low precision master crystal oscillator for clocking the frequency of the latch. The most significant bit from the latch is input into a phase/frequency detector for forcing a voltage controlled oscillator to track a desired frequency.

Abstract: A frequency hopping receiver capable of real time demodulation, and a method thereof are provided. The frequency hopping receiver includes first and second frequency generators, a switch, a controller and a demodulator. The first frequency generator receives a first frequency control signal according to a predetermined control and generates a predetermined frequency first carrier wave used to generate a synthesized carrier wave for demodulating the received signal. The second frequency generator receives a second frequency control signal according to a predetermined control and generates a predetermined frequency second carrier wave used to generate the synthesized carrier wave for demodulating the received signal. The switch switches between the first and second carrier waves in response to a signal for selecting a carrier wave, to generate a continuous synthesized carrier wave.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.