Abstract: A noise test measurement system configured to measure a noise component of a transmitted RF signal is described. The noise test measurement system may include an antenna, a low-noise amplifier, a local oscillator, a first coupler, a first variable phase-shifter, a first mixer, and a processor.

Abstract: A direct conversion method is disclosed. The method comprises: amplifying the input signal to generate an amplified signal; down-converting the amplified signal into two intermediate signals using a first set of ternary signals and a second set of ternary signals, respectively; filtering the first intermediate signal to generate a third intermediate signal; filtering the second intermediate signal to generate a fourth intermediate signal; digitizing the third intermediate signal into a first output signal in accordance with a first clock; digitizing the fourth intermediate signal into a second output signal in accordance with the first clock; and generating the first set of ternary signals and the second set of ternary signals based on a second clock.

Abstract: In a direct conversion receiver, to cancel a DC offset generated in the baseband processing block, negative feedback arrangements comprising a gain control amplifier and a low-pass filter are respectively attached to the I and Q signal branches of the baseband block following mixer outputs. The gain control amplifier in each negative feedback circuit is gain adjusted so that the product G·B of the gain G of a primary gain control amplifier and its own gain B will be constant and thereby the DC offset is cancelled. This DC offset cancellation can be applied in a continuous receiving system with no intermittent time during a receiving operation. Capacitance elements located off-chip can be reduced to those to be used only in the low-pass filters in the negative feedback circuits, whereas many off-chip capacitance elements have been required to be inserted between each stage of gain control amplifiers in conventional baseband chains.

Abstract: A multiple frequency band hybrid receiver includes a plurality of input terminals to which different frequency band signals are respectively inputted; a plurality of mixers connected to the plurality of input terminals sequentially, receiving the different frequency band signals respectively, and down-converting frequencies of the received frequency band signals to predetermined frequencies; an output terminal outputting baseband signals. Each mixer receives a signal from an input terminal connected thereto or another mixer. One of the plurality of mixers receives the lowest frequency band signal, converts a frequency of the received signal to a baseband frequency, and provides a signal having the baseband frequency to the output terminal. The other mixers each down-convert a frequency of a received signal to a frequency band of a signal which is inputted into another mixer.

Abstract: System and method for processing signals are disclosed. The method may include converting, in an RF receiver, one or more analog samples, which are selected from one of a plurality of output paths of the RF receiver, to one or more digital samples. A digital feedback value may be generated based on an average of the one or more converted digital samples. A scaled version of the generated digital feedback value may be converted to an analog value. The converted analog value may be fed back to one or more of a plurality of input paths of the RF receiver. The one or more analog samples may be selected from among a plurality of output analog samples from the plurality of output paths of the RF receiver.

Abstract: According to one exemplary embodiment, a method for producing frequency conversion of a communication signal comprises performing a logarithmic transformation of the communication signal to form a logarithmically transformed communication signal, adding the logarithmically transformed communication signal to a logarithmic local oscillator signal, to form a sum signal, and performing an anti-logarithmic transformation of the sum signal. In one embodiment, the method may be used to down-convert a reception signal to baseband. In one embodiment, a log-antilog mixer circuit for producing frequency conversion of a communication signal comprises a signal log block configured to receive the communication signal as an input and to provide a logarithmically transformed communication signal as an output, and an antilog block configured to receive a sum signal of the logarithmically transformed communication signal and a logarithmic local oscillator signal.

Abstract: An RF receiver and an RF receiving method are provided using a baseband signal in which a DC offset is removed. In the RF receiver, a noise phase removing unit generates a phase controlled local signal PLOQ in which a phase of a Q signal of a local signal LOQ is controlled, by synthesizing a received RF signal RXIN and the Q signal of the local signal LOQ. A down converter generates a signal in which a DC offset from noise introduced into the received RF signal RXIN is removed, when synthesizing the received RF signal RXIN and the phase controlled local signal PLOQ for frequency-down conversion.

Abstract: The invention proposes an LNB using two transposition frequencies chosen on either side of the reception band so as to obtain a transposition of supradyne type and a transposition of infradyne type according to the frequency used. This choice of transposition frequencies makes it possible to have an overlap zone in the middle of the reception band which is transposed with the aid of the two oscillation frequencies but at different frequencies. This makes it possible to choose between the two transpositions in the case where the frequency transposed with the aid of an oscillator corresponds to a particularly noisy frequency.

Abstract: A radio-frequency IC (3) for a mobile radio transmitter (1) has an analogue/digital converter unit (5) for digitizing baseband signals (AB), a recovery unit (6, 7, 8, 9, 10) for recovering determined data information (Rot, TxSymbPhase) on which the baseband signals (AB) are based, a digital/analogue converter unit (11) and a frequency converter unit for producing transmitted signals on the basis of the signals produced by the digital/analogue converter unit (11).

Abstract: A method according to one embodiment includes using a quadrature set of local oscillator signals having duty cycles of substantially less than fifty percent to perform a mixing operation on a radio-frequency current signal. Other embodiments include using a quadrature set of local oscillator signals having duty cycles of less than twenty-five percent.

Abstract: Systems and methods for DC offset correction in analog and digital direct conversion RF receivers. A time derivate and subsequent integration of in-phase and quadrature phase signal path components is performed to effectively remove DC offset from the resultant down converted baseband signal.

Abstract: A wireless receiver (100) for receiving and demodulating a frequency modulated RF (radio frequency) signal by a direct conversion procedure, including channels (110, 112) for producing in-phase and quadrature components of a received RF signal, and a processor (123, 133) for periodically estimating an error in at least one of the in-phase and quadrature phase components and for producing a signal for adjustment of at least one of the in-phase and quadrature components to compensate for the detected error, wherein the processor is operable to apply alternatively each of a plurality of different procedures to estimate the error, the procedures including a first procedure which is applied when a signal quality value of the received RF signal is above a threshold value and a second procedure which is applied when a signal quality value of the RF received signal is not above the threshold value.

Abstract: Provided is a sub-harmonic frequency mixer having a structure in which two terminals of transistors receiving a Radio Frequency (RF) signal and a Local Oscillation (LO) signal are coupled. The frequency mixer is composed of a single-level structure of transistors and thus can be driven at a lower supply voltage compared to a common frequency mixer. A direct-conversion receiver employing such a frequency mixer needs an RF signal and an LO signal sources of single-phase. Therefore, the direct-conversion receiver has an architecture that simplifies a whole RF transceiver circuit and thus can be advantageously applied in implementing SoC (System-on-Chip) for a low power, high integration, low price and subminiature wireless transceiver circuit.

Abstract: A multiple band direct conversion radio frequency (RF) transceiver integrated circuit (IC) includes a multiple band direct conversion transmitter section, a multiple band direct conversion receiver section, and a local oscillation module. The multiple band direct conversion transmitter section includes a transmit baseband module and a multiple frequency band transmission module. The multiple band direct conversion receiver section includes a multiple frequency band reception module and a receiver baseband module. The local oscillation generation module is operably coupled to generate a first frequency band local oscillation when the multiple band direct conversion RF transceiver IC is in the first mode and operably coupled to generate a second frequency band local oscillation when the multiple band direct conversion RF transceiver IC is in the second mode.

Abstract: A method is for reducing a DC component of an input signal transposed into baseband and being generated by a first frequency transposition stage starting from an initial signal and from a transposition signal. The method includes amplifying the transposed input signal in a first amplifier. The first amplifier receives at a DC offset compensation input, a compensation signal extracted from an output signal of a second amplifier subjected to a compensation of a offset DC voltage of the second amplifier. The method also included alternating between receiving at an input of the second amplifier, a first auxiliary signal from an auto-transposition of a transposition signal in a second frequency transposition stage and a second auxiliary signal from a transposition of the initial signal in the second frequency transposition stage with the transposition signal.

Abstract: The present invention is a quadrature VLIF receiver, including calibration circuitry, and methods to closely match signal processing of an in-phase signal path and a quadrature-phase signal path to optimize VLIF image rejection. The calibration circuitry includes a variable gain variable-phase calibration signal generator, a variable gain amplifier for each signal path, phase adjustment circuitry for each signal path, and switching circuitry to support calibration steps. The calibration signal generator supplies a calibration signal at the same frequency as mixer local oscillator signals; therefore, during calibration, all signals downstream of the VLIF mixer are at DC, which simplifies calibration measurements, thereby minimizing calibration times.

Abstract: An RFID reader analog front end architecture employs multiplexed use of a single analog to digital converter in order to digitize the inphase and quadrature components of the incoming signal from the reader's receiving antenna. The Type 1 architecture includes an analog I/Q switch that controls which of the baseband signals will be digitized by a single Analog to Digital Converter. In the Type 2 architecture, the I/Q switch is moved so that it is directly adjacent to the receive mixers, requiring only one antialiasing filter block and gain block. In the Type 3 architecture, one mixer and its associated filtering chain are eliminated. The Type 4 architecture provides for selection of transmitter phase basis by means of an I/Q switch operating under control of the DSP that phase-shifts the transmitter with respect to the receiver.

Abstract: A frequency converter according to one embodiment includes a quadrature pair of passive mixers whose input terminals are coupled to a differential radio-frequency input via the channel regions of transistors that are arranged to operate in the saturation region.

Abstract: In a system and method for simultaneously receiving or switching between dual frequency carrier signals in a GPS receiver, the GPS receiver is adapted to utilize different harmonics of a sub-harmonic frequency generator, which may include a lower frequency voltage controlled oscillator (VCO) to detect the L1 and L2 GPS carriers. A sub-harmonic mixer may be used to simultaneously down convert the L1 and L2 signals to a lower intermediate frequency (IF). A second mixer may be an image reject (IR) mixer used to separate the downconverted L1 and L2 signals. This mixer may be configured to simultaneously monitor the L1 and L2 signals, or to switch between the L1 and L2 signals. High frequency switching is not required of the radio frequency (RF) input or local oscillator signals, and simultaneous L1 and L2 reception is enabled without and 3 dB image noise degradation.

Abstract: A frequency mixer device is provided with a mixer circuit having an input cell that amplifies an input signal and a switching cell that mixes the amplified input signal with a switching signal and outputs a multiplied signal, and a DC offset compensator that detects the input level of the input signal and outputs a compensation signal based on that detection signal, the compensation signal being supplied to the mixer circuit so as to compensate a DC offset included in the multiplied signal. The compensation signal that the DC offset compensator outputs is added to the output signal of the input cell so as to compensate the DC offset. Low frequency noise included in the compensation signal is converted to a frequency near that of the switching signal, and does not range over the desired waveband of the mixer output.

Abstract: A communications system is provided that includes a detector that has I/Q mismatch, a calibration circuit that estimating a phase and/or an amplitude mismatch of the detector, and a compensation circuit that uses the estimated phase and/or amplitude mismatch to mitigate the effects of the amplitude and/or phase mismatch. An IQ-modulated signal produced by the I/Q-modulator can be communicated over a loop back connection to the detector of the communication system. The calibration circuit can estimate the I/Q mismatch for the IQ-modulator and can provide the estimated values to a pre-compensation circuit. In one aspect, I/Q mismatch in the IQ-modulator of a communication system can be determined using a spectrum analyzer. Power measurements can be used to compute the amplitude mismatch and the phase mismatch of an IQ-modulator.

Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a wireless communication transmitter employs a control process to implement numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. By monitoring a plurality of parameters associated with the analog radio, such as temperature, bias current or the like, enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters may be implemented.

Abstract: A method and circuit for receiving a radio frequency signal by receiving and amplifying the radio frequency signal to produce a received signal and generating first and second clock signals corresponding to first and second channel signals, respectively, of the received signal and multiplying the received signal with the clock signals to obtain the channel signals. Pre-selectivity filtering of the received signal is performed by filtering the first channel using a first impedance, filtering the second channel using a second impedance, and converting the first and second impedances with respect to one another through a first gyrator. Amplitude limiting of the first and second channels is performed to obtain first and second amplitude limited channels. Poly-phase selectivity filtering of the first and second amplitude limited channels is performed to obtain first and second selectivity filtered channels. The selectivity filtered channels are demodulated to obtain a data signal.

Abstract: A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives a set of IR samples from the memory, forms a turbo code word from the set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching on the set of IR samples, performs error detection operations, and extracts information from a MAC packet that it produces.

Abstract: A system and method is shown for automatic frequency correction in a receiver, where the number of clock cycles in a baseband data signal, such as an I or Q channel of the receiver or an XOR of the I and Q channels, for a “1” state and a “0” state of a received data signal are each determined and the difference between the two is used to calculate a subsequent frequency offset correction value. The subsequent frequency offset correction value is added to a current offset correction value to obtain an actual offset correction value. The actual offset correction value is then used to adjust the frequency of the receiver clock.

Abstract: A multipath wideband communications receiver (100) having a plurality of RF signal paths (116, 136) covering different but overlapping frequency bands and a plurality of baseband signal paths (140, 150, 160, 170, 180, 190), the paths being re-configurable for sharing of the first and second paths in different ways in order to facilitate processing of received signals in different modes. Also, a rake receiver (800) employs a sigma-delta modulator arrangement (810) and programmable delays to provide fine delay adjustment. The sigma-delta modulator (810) may use sigma-delta circuitry from a sigma-delta A/D converters in a baseband paths of the receiver (100), that this may be achieved with no loss of functionality if in a particular reception configuration that sigma-delta A/D converter is not being utilized.

Abstract: A non-coherent synchronous direct-conversion receiving apparatus is provided. The apparatus includes a RF receiving unit, an I/Q ADC unit, and a digital signal processing unit for analyzing the digital signal received from the I/Q ADC unit to adjust a bandwidth of a variable receiving filtering unit according to the analyzing result, compensating a frequency offset to be correspondent with a symbol transmitting rate by extracting frequency offset information from the digital signal, compensating a frequency offset using the analyzing result, and applying a voltage corresponding to a sum of compensating values to the RF receiving unit. Therefore, the apparatus can compensate a frequency offset regardless of the magnitude of a frequency offset and performs a stable AFC operation through varying the bandwidth of a receiving filter by estimating the frequency offset with only data information, and adjusting a reference frequency twice through an interface signal.

Abstract: A programmable attenuator includes a resistor ladder having a plurality of taps to provide a coarse gain control. Coupled to each tap is a plurality of switches. Control logic activates or deactivates individual switches in the plurality of switches to provide a fine gain control. More specifically, a set of activated switches provides fine gain control by determining an overall attenuation level interpolated between an adjacent pair of taps.

Abstract: A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

Abstract: A method for performing handover between multiple modes for a mobile station is provided. The method includes operating the mobile station in a first mode. A handover from the first mode to a second mode is performed using a single wireless receiver. The mobile station operates in the second mode after performing the handover.

Abstract: A transmitter circuit has two mixers that modulate a carrier wave according to an input signal, outputs a signal having information in a phase and an amplitude, detects a DC offset in each of the mixers, and adds a DC voltage that corrects the detected DC offset to the input signal of the mixers. The mixer is a double balanced mixer having two load resistors, and the transmitter circuit has a resistor that is connected between a node of two load resistors and a power supply, a limiter amplifier that amplifies a signal, and a control unit that changes first and second potentials using a signal that is outputted by the limiter amplifier. The first and second potentials become a potential of the DC voltage that corrects the DC offset.

Abstract: A system and method is disclosed for enhancing a reception rate for a mobile communication system. A system is provided comprising a demodulator for separating a received signal into an I signal and a Q signal, an amplifier for amplifying the I signal and Q signal from the demodulator, and an offset adjusting unit. The offset adjusting unit is provided for amplifying an amplified I signal and an amplified Q signal, comparing a difference signal determined between the amplified I signal and the amplified Q signal with a target value, and outputting an amplification control signal associated with the difference signal and an amplification offset value.

Abstract: A direct current (DC) offset correction system for a direct conversion receiver and corresponding receiver and methods facilitate reduction of DC offsets in such receivers. One method includes calibrating a DC offset correction system in a closed loop configuration over each of a plurality of gain settings to provide a plurality of offset data for an operating mode of the direct conversion receiver; selecting one of the plurality of offset data based on a current gain setting of the direct conversion receiver as supplied, e.g., by an AGC system; and operating the DC offset correction system in an open loop configuration using the one of the plurality of offset data to correct for a DC offset in the direct conversion receiver.

Abstract: Aspects for measuring receiver mixer IQ mismatch in a transceiver are described. The measuring includes providing a training signal for a receiver mixer, the training signal having periodic, uncorrelated I and Q signals. A phase mismatch in the receiver mixer is determined from IQ correlation over a unit period. A gain mismatch in the receiver mixer is determined from a power estimate of both I and Q signal for the unit period.

Abstract: Aspects of compensating for DC offset in an RF receiver may comprise sampling data from at least one of a plurality of output paths, selecting a sampled data and generating at least one feedback signal based on the selected sampled data. The generated feedback signal may be fed back to at least one of a plurality of input paths, and at least one of the feedback signals may be of an opposite polarity to the selected sampled data. The selected sampled data may be converted to a digital sample, a plurality of the digital samples accumulated, and an average of the plurality of the digital samples calculated. A digital feedback value may be generated based on the average. A phase of the digital feedback value may be adjusted via a derotator, which may utilize the coordinate rotation digital computer (CORDIC) algorithm.

Abstract: In a radio apparatus, the band of a loop filter of a synthesizer in a blank channel searching state is narrower than the band in a communicating state. In addition, a radio wave environment is measured. A characteristic necessary for the radio apparatus is determined corresponding to the measured-radio wave environment. The power is controlled corresponding to the performance of the radio apparatus. Thus, the power consumption is decreased. In addition, the efficiency of the output power is improved. In the radio apparatus, the current consumption of a power amplifier PA is measured. A matching circuit (LNA or MIX) of the antenna is adjusted with the measured result so as to decrease an antenna loss. In the radio apparatus, a DC offset is removed from the transmitted power and the reflected wave. When the DC offset is removed using an AC coupling capacitor, the deterioration of the frequency characteristic of the receiving portion is compensated with a capacitor in a digital signal process.

Abstract: For the purpose of efficient transmission based on the UWB system, first and second baseband waveforms are generated at a cycle equivalent to an integral multiple of a carrier to have a specified phase difference from each other. The first baseband waveform is multiplied by the carrier and a first transmission data sequence to acquire a first transmission waveform. The second baseband waveform is multiplied by a phase shifted carrier and a second transmission data sequence to acquire a second transmission waveform. The first transmission waveform is mixed with the second transmission waveform to acquire a transmission signal. The transmission signal is transmitted as a ?/2 shift BPSK signal to transmit a UWB signal. Selecting the baseband waveforms and the carrier makes it possible to configure the transmission band and easily provide division multiplexing transmission.

Abstract: The present invention relates to an I/Q modulator using a current-mixing method used for a direct conversion wireless communication transmitter. In accordance with the present invention, an EVM of a wireless communication system, a linearity and a power consumption are improved by converting a D/A converted signal to a current level and then performing a frequency modulation.

Abstract: A sub-harmonic mixer and a down converter with the sub-harmonic mixer are provided. The sub-harmonic mixer includes a differential amplifying unit, a current buffer unit, and a switching unit. The differential amplifying unit is used to amplify a radio frequency (RF) signal and employs a first resonance circuit to force a leakage signal to flow to a first voltage. The current buffer unit is used to amplify the gain of an output signal of the differential amplifying unit and employs a second resonance circuit to force the leakage signal to flow to a second voltage. Finally, the switching unit switches an output signal of the current buffer unit into a base band signal.

Abstract: A digital mixer system and method is disclosed. In an embodiment, a digital mixer can receive a modulated signal having a sample rate approximately equal to a clock rate divided by an integer factor. The digital mixer can include a first mixing stage having a first plurality of Coordinate Rotation Digital Computer (CORDIC) elements to serially perform a predetermined number of consecutive CORDIC iterations per clock cycle. The first mixing stage can further have logic to selectively process data received from an output of the first mixing stage. The digital mixer can also include a second mixing stage having a second plurality of CORDIC elements to serially perform a number of consecutive CORDIC iterations per clock cycle. The second mixing stage can also have logic to selectively process data received from an output of the first mixing stage and from an output of the second mixing stage.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning a local oscillation frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset. The circuitry further includes a multi-stage mixer that produces current signal outputs from each mixing stage to a subsequent stage thereby avoiding a need for intermediate transconductance and output stages to convert between current signals and voltage signals.

Abstract: An apparatus and method for internally calibrating a direct conversion receiver (DCR) through feeding a calibration signal via ESD protection circuitry is disclosed. The apparatus includes an internal signal generator for generating a calibration signal, a front-end input stage for receiving an RF signal at an input node, an ESD protection unit for protecting against electrostatic discharge, and a switch unit coupled to the ESD protection unit, for selectively passing a calibration signal to the front-end input stage, whereby the connection of the switch unit and the ESD protection unit means that when the DCR is operating in normal mode, the switch unit will not affect the noise performance and matching of the receiver.

Abstract: In a signal receiving circuit of a direct conversion system applied with a semiconductor integrated circuit for radio communication having a PLL requiring a clock signal, an LNA requiring low-noise receiving characteristics, and others, a variable coupling line is provided between clock signal buffers and at an input stage of the PLL, so that coupling between the variable coupling line and an input terminal of the LNA and coupling between the variable coupling line and a GND terminal of the LNA are made equal to each other at frequencies of higher harmonic waves of a clock signal. When the input terminal and the GND terminal of the LNA are excited at the same phase, since no output occurs at an output terminal of the LNA, an output of the LNA does not contain any higher harmonic wave of a clock signal.

Abstract: A programmable transmitter generates a frame preamble to train a receiver with respect to a communication link format that corresponds to a transmission mode wherein the transmission mode may comprise transmitting the communication link over one or more antennas. Generally, the invention includes generating a preamble with an arrangement that depends upon whether a Greenfield (high data rate) or mixed mode transmission is to occur and that depends upon a number of spatial streams that are to be generated. One format for high data rate transmission includes a short training sequence, a long training sequence and a signal field. The mixed mode transmission further includes a legacy prefix.

Abstract: A harmonic filter for filtering a plurality of frequency components from an input signal comprises a phase shifter for generating an in-phase signal and a quadrature-phase signal according to the input signal; and a plurality of polyphase filter networks coupled in series. The first polyphase filter network in the series is coupled to the phase shifter for receiving the in-phase and quadrature-phase signals. Each polyphase filter network is for filtering a corresponding one of the frequency components from the input signal.

Abstract: An architecture for a receiver component in a wireless communications system is disclosed—one that supports both zero intermediate frequency (ZIF) and near-zero intermediate frequency (NZIF) operation. The architecture provides a down-conversion segment, and a local oscillator segment operatively associated with the down-conversion segment. An analog-to-digital conversion (ADC) segment is adapted to receive signals from the down-conversion segment and introduce the signals into a digital intermediate frequency (DIF) construct. The DIF construct performs a DC offset compensation or DC residue filtering on NZIF-based signals, and droop or mismatch compensation. Image removal is performed on NZIF-based signals, and DC offset compensation is performed on ZIF-based signals. Compensated signals are amplified to some nominal or desired level, and interpolation filtering of the amplified signals is performed prior to transmission thereof.

Abstract: Systems and methods for DC offset correction in analog and digital direct conversion RF receivers. A time derivate and subsequent integration of in-phase and quadrature phase signal path components is performed to effectively remove DC offset from the resultant down converted baseband signal.

Abstract: The embodiments of the present invention provide a configurable homodyne/heterodyne RF receiver including first and second mixers. The configurable homodyne/heterodyne RF receiver functions as a homodyne receiver when the first and second mixers are configured to operate in parallel, and as a heterodyne receiver when the first and second mixers are configured to operate in series. The embodiments of the present invention further provides an RFID reader employing the configurable homodyne/heterodyne RF receiver to facilitate a listen-before-talk function.

Abstract: A direct sampling tuner includes a low noise amplifier and an optional dynamically configurable band pass filter coupled to the low noise amplifier. The optional filter is configured to pass a selected band of channels. The tuner further includes a relatively high accuracy, multi-bit analog-to-digital converter (“ADC”) coupled to the LNA or to the optional dynamically configurable band pass filter. The ADC operates at greater than about twice a frequency of a sampled signal. The ADC directly samples the spectrum of the selected channels at the Nyquist frequency, thus avoiding image problems presented by conventional tuners.

Abstract: Provided are a direct current (DC) offset compensation apparatus and a method thereof. A DC offset compensation apparatus comprises an offset detection block detecting a DC offset, an offset compensation block operating according to an output signal of the offset detection block, and an offset compensation amplifying block controlled according to an output signal of the offset compensation block. Particularly, the offset compensation block comprises a counter that counts polarities of DC offsets for a predetermined period, a controller that comprises first to fourth mode units respectively operating fast down-compensation, regular down-compensation, fast up-compensation, and regular up-compensation modes, and a control device that controls the execution of one selected among the first to fourth mode units based on a value counted by the counter, and a register storing data to control the offset compensation amplifying block based on the one mode unit determined by the controller.