Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

Abstract: A system is provided for measurement data management in a distributed environment. The system comprises at least one storage system adapted to obtain raw measurement data or intermediate results from at least one measurement site via a network. In addition, the system further comprises a database, operatively connected to the said storage system, adapted to be accessed remotely by the measurement site via the network. The storage system or the measurement site is further adapted to perform successive processing steps on the raw measurement data along a process chain in order to generate measurement results, whereby associating metadata with the raw measurement data and with the measurement results. In this context, the metadata associated with each measurement result of the successive processing steps is provided with a new reference as well as a reference to the reference of the measurement result from the preceding processing step.

Abstract: Methods, systems, and devices for a fail compare procedure are described. An apparatus may include a host device coupled with a memory device. An application specific integrated circuit (ASIC) associated with the host device (e.g., included in, coupled with) may include a set of comparators that output first bit information that includes respective states of at least two bits of data read from the memory device. The host device may compare (e.g., at the ASIC) the first bit information to second bit information that includes respective expected states of the at least two bits. Based on the comparison, the host device may determine whether a state of at least one bit of the first bit information is different than a state of a corresponding bit of the second bit information, and may output one or more signals including indications of a fail to a counter of the ASIC.

Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

Abstract: Methods, systems, and devices for pattern generation for multi-channel memory array are described. A device may include a memory array and a circuit for testing the memory array. The memory array may include a first set of memory cells and a second set of memory cells, the first set of memory cells coupled with a first channel and the second set of memory cells coupled with a second channel. The circuit may be coupled with the memory array and may include a pattern generator and an output response analyzer. The pattern generator may be configured to selectively output a single pattern when operating in a single-pattern mode or a plurality of patterns when operating in a multi-pattern mode. The output response analyzer configured to determine whether the memory array includes one or more errors based at least in part on a pattern output by the pattern generator.

Abstract: Methods, systems, and computer-storage media are provided for validating the configuration of one or more applications to be used by one or more users in a healthcare management system. Requests are received to perform a configuration validation for at least one application at a first location. Configuration file data comprising one or more requirements and configuration data for the at least one application is obtained. The configuration validation is performed by conducting a comparative analysis on the configuration file data and the configuration data. If the data is identical, then the requirements are met, and the correct version of the application is installed. If the data is not identical, then the system identifies the correct version that needs to be installed. A message is generated for the first user comprising the configuration validation outcome.

Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

Abstract: Test case data is received for individual test cases. The test case data includes sets of test case specific elements. A test case base object is generated to represent a generic test case. The test case base object includes a set of test case specific properties. The test case base object is expanded into individual test case specific objects that represent the individual test cases. Each individual test case specific object is generated by setting the set of test case specific properties to a respective set of test case specific values as indicated in the sets of test case specific elements. The individual test case objects are used to execute the individual test cases against one or more systems under test.

Abstract: According to various embodiments, there is provided a method for testing a device driver software of a processor, the method including: configuring an identity field of a testing device based on a device emulation command received through a first testing device interface, wherein the identity field is accessible by the device driver software for recognising the testing device; running an emulation program on the testing device, the emulation program including an emulation of a human input device in accordance with the configured identity field; receiving an input instruction in the testing device via the first testing device interface, the input instruction indicative of an input performable on the emulated human input device; the emulation program, emulating an output signal generatable by the emulated human input device in response to the input being performed on the emulated human input device; outputting the emulated output signal via a second testing device interface to the device driver software of the

Abstract: A display panel test circuit that includes a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs); a first signal line electrically connected to gates of the MOSFETs; a second signal line electrically connected to sources of a part of the MOSFETs; and a third signal line electrically connected to sources of other part of the MOSFETs; wherein sources of any two adjacent MOSFETs of the plurality of MOSFETs are electrically connected to the second signal line and the third signal line, respectively. The display panel test circuit can detect a short circuit problem of a green data signal during a phase of lighting test, and thereby monitor and increase yields of AMOLED display panels.

Abstract: Methods and apparatus are provided for testing computing devices. A host computing device is provided for testing devices under test (DUTs) using a test suite that includes first and second tests. The DUTs can include a first group of DUTs with a first DUT and a second group of DUTs with a second DUT. The first and second groups of DUTs can share a common design. The host computing device can determine that the DUTs execute the first test before the second test. The host computing device can receive failing first test results for the first DUT. The host computing device can determine, based on the first test results and that the first and second DUT groups share a common design, to execute the second test before the first test and can subsequently instruct the second DUT to execute the second test before the first test.

Abstract: A device and computer-executable method is provided for adaptively determining a sampling scheme to be applied at a first sensor from among a plurality of sensors for sampling sensor data values corresponding to a signal. A sparsifying transform for a subsequent sampling time window of the first sensor is predicted, wherein the sparsifying transform is determined based on a predictive model of the sparsity of the signal. Moreover, a subsampling parameter for the subsequent sampling time window is determined. The subsampling parameter corresponds to a number of sensor data values to be acquired within the sampling time window. This subsampling parameter is determined based on the predicted sparsifying transform. Further determined is a compressive sampling scheme for the subsequent sampling time window of the first sensor. The compressive sampling scheme is determined based on the predicted sparsifying transform.

Abstract: An apparatus receives environmental data indicative of environmental parameters in a vicinity of a smart tray bearing a product thereon. The apparatus receives from the smart tray, network data being transmitted to the product via a network port in the smart tray. At least one outlier in the environmental data or the network data is identified. An action to be executed at the smart tray is determined in response to identifying the outlier.

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.

Abstract: A computer based method for a reusable functional failure test for a specific technical system, e.g., a traffic light system is provided. The method avoids inconsistencies in the functional failure test and reuses items of the respective data structures. Furthermore, the embodiment can identify components or electronic devices that do exceed assumed failure rates and that might be repaired or replaced to keep implementations of the specific technical in the desired failure rate limitations of the analysis, which can be done during the operation of the specific technical system.

Abstract: An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.

Abstract: One embodiment relates to a method of controlling supply voltage regulation within an integrated circuit. An external interrupt is sent from an external interaction processing layer to a processor in the integrated circuit. Off-die instructions are generated by the external interaction processing layer and sent to the processor. The off-die instructions are executed by the processor to test and adjust supply voltage regulation within the integrated circuit on a sector-by-sector basis. Another embodiment relates to a method of controlling a supply voltage regulator for a sector of an integrated circuit. Commands are sent by a processor and translated by a sector manager to bits. The bits are loaded into registers so as to set the regulator control circuit to the testing mode send a supply voltage to an analog-to-digital converter. Other embodiments and features are also disclosed.

Abstract: A sensor device comprises a sensor connected to a first signal and responsive to an external field to produce a sensor signal, a test device connected to a second signal and electrically connected in series with the sensor by an electrical test connection providing a test signal, and a monitor circuit electrically connected to the first, second and test signals. The monitor circuit comprises a processing circuit and a determination circuit. The processing circuit is responsive to the test signal and a predetermined processing value to form a processing output signal. The determination circuit is responsive to the processing output signal to determine a diagnostic signal. A sensor circuit responsive to the sensor signal provides a sensor device signal responsive to the external field.

Abstract: The invention provides a technology for promptly determining bacterial identification or an antimicrobial susceptibility testing. In the invention, first, a state where the bacteria are divided is monitored by performing microscopic observation with respect to the shape or the number of bacteria in each of wells of a culture plate for bacterial identification culture or the antimicrobial susceptibility testing. In addition, the shape, the number or the area of the bacteria are interpreted from the image obtained by the microscopic observation whether or not the bacteria proliferate at a stage from an induction phase to a logarithmic phase, and the time-dependent changes thereof are made into a graph. From the graph, it is determined whether or not the bacteria proliferate for each measurement, the determination results are displayed on the screen, and accordingly, the result of the antimicrobial susceptibility is provided every time when the measurement is performed (FIG. 12).

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip.

Abstract: It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.

Abstract: Determining instruction execution history in a debugger, including: retrieving, from an instruction cache, cache data that includes an age value for each cache line in the instruction cache; sorting, by the age value for each cache line, entries in the instruction cache; retrieving, using an address contained in each cache line, one or more instructions associated with the address contained in each cache line; and displaying the one or more instructions.

Abstract: Methods, systems, and devices for operating a memory device are described. A sense amplifier may be used to precharge an access line to increase the reliability of the sensing operation. The access line may then charge share with the memory cell and a capacitor, which may be a reference capacitor, which may result in high-level states and low-level states on the access line. By precharging the access line with the sense amplifier and implementing charge sharing between the access line and a capacitor, the resulting high-level state and the low-level states on the access line may account for any offset voltage associated with the sense amplifier.

Abstract: A mechanism is described for facilitating smart filtering and local/remote processing of data according to one embodiment. A method of embodiments, as described herein, includes detecting data collected via one or more sensing components, and evaluating the collected data to identify one or more portions of the collected data having privacy relevance, where evaluating further includes classifying the one or more portions as private data and other portions of the collected as non-private data. The method may further include filtering out the private data from the non-private data of the collected data, and processing the private data, where the non-private data is transmitted to a remote computing device over a network.

Abstract: Several embodiments perform battery backup unit (BBU) degradation testing. For example, a BBU testing system can be coupled to or part of a BBU. The BBU testing system can discharge the BBU by engaging a variable load to the BBU. The BBU testing system can monitor a discharge energy consumption over time as the BBU discharges until the discharge energy consumption reaches a specified amount of energy. The BBU testing system can determine a discharge time for the discharge energy consumption to reach the specified amount of energy. The BBU testing system can then compute a degradation state of the BBU based on the discharge time.

Abstract: Embodiments of the present invention disclose a heartbeat period setting method, including: setting a heartbeat period of a tested application to T2 and performing a first heartbeat test; setting heartbeat periods of multiple applications to T1 if the first heartbeat test is not passed, and performing heartbeat services; or setting the heartbeat period of the tested application to T3 if the first heartbeat test is passed, and performing a second heartbeat test; and setting the heartbeat periods of the multiple applications to T2 if the second heartbeat test is not passed, and performing heartbeat services; or setting the heartbeat period of the tested application to T4 if the second heartbeat test is passed, and performing a third heartbeat test, where T1<T2<T3<T4. The embodiments of the present invention further disclose a corresponding mobile terminal.

Abstract: A measuring and analyzing device is described which comprises a housing, a spectrum analyzer unit for analyzing a spectrum of a signal received, and a multimeter unit for measuring currents, voltages, resistances and/or connectivities. Said housing encompasses said spectrum analyzer unit and said multimeter unit. Said device is a handheld and portable measuring and analyzing device. Further, a method for measuring and analyzing signals is described.

Abstract: A monitoring system can receive sensor measurements from a select sensor of a group of sensors. The sensor measurements are compared to group alert condition or an individual alert condition. Based on the comparison, an alert state can be identified and a user notified of the alert state. The system can automatically determine the individual alert condition, which can be uniquely associated with the select sensor and can be associated with a domain of time.

Abstract: The present application relates to set top boxes and relates to the inclusion of a diagnostic function in the set top box which may be activated remotely or respond internally to the detection of faults or changes in status. The diagnostic function may emulate key presses from an infrared remote control to perform a test.

Abstract: Configurable input/output unit and configurable modular card provided therewith. The configurable input/output unit comprises a plurality of configurable inputs and outputs. The plurality of configurable inputs and outputs comprises a predefined output for sending a broadcast message and a predefined input for receiving a broadcast response message. The card comprises a board, at least one processor mounted on the board, at least one memory mounted on the board and in electronic communication with the processor, the configurable input/output unit comprising the plurality of configurable inputs and outputs, and a bus for providing electronic data exchange there between. The processor configures the plurality of inputs and outputs of the configurable input/output unit based on the broadcast response message. The processor may generate testing signals to the plurality of inputs and outputs of the configurable input/output unit.

Abstract: A system and method for monitoring and correcting device operating states during steady-state operations may be automated. The operating states for devices operating in a steady-state environment may be monitored. Any operating device that is set to operate in an unexpected operating state may be automatically changed to its expected operating state. The operator may then be warned of any incorrect state assignment through a console message that cannot be ignored by the operator.

Abstract: An improved self-testing method is described which is incorporated into a defibrillator (20). The method performs a self-testing protocol which operates on a first frequency until a threshold condition is reached. When the threshold condition is reached, the self-testing protocol switches to a second frequency. Such a method enables quicker identification of a failure mode in a population of defibrillators, while maintaining acceptable battery life in the device.

Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract: A method includes determining at least one value for at least one instance of data; determining at least one privacy policy, at least one security policy, or a combination thereof based, at least in part, on the at least one value; and causing, at least in part, an application of the at least one privacy policy, the at least one security policy, or a combination thereof with respect to the at least one instance of data.

Abstract: A technique is disclosed for facilitating editing of editable code in an interface device or similar apparatus. Properties of device elements are enumerated by a general purpose engine resident on the interface device. The general purpose engine enumerates the properties in response to a query in a design-time environment. The device element includes a specific property type and editable code consistent with the property type. A server module on the device serves the editable code and an editing environment from the interface device to a configuration station. The code can be edited on the configuration station in the editing environment and restored to the interface device. The technique alleviates the need for separate editing software or storage of the editable code in any location other than on the interface device itself.

Abstract: A method for analyzing test results. The method includes selecting a first subset of tests from a plurality of tests. Test results are gathered from the plurality of tests in real-time. A first statistical analysis is performed on test results from the first subset of tests. At least one process control rule is initiated as determined by results of the first statistical analysis performed on the test results from the first subset of tests.

Abstract: An alarm notification apparatus includes an event detector for monitoring vital information of a body, such as a blood pressure and electrocardiogram, to check whether an anomalous event has occurred to the body. A reliability evaluator evaluates reliability of a result of detection of the anomalous event in the event detector. A notifier selects at least one addressee according to the reliability among plural predetermined addressees, and notifies the selected addressee of occurrence of the anomalous event. Preferably, a storage area is used for storing error log data expressing a false detection of an anomalous event in spite of non-occurrence of an anomalous event. Assuming that the event detector detects the anomalous event, the reliability evaluator obtains the reliability according to the error log data. Thus, it is possible to reduce influence of the false detection due to measurement artifact.

Abstract: A device includes an OLED pixel and a control circuit controlled at a refresh rate thereof. The device includes first and second dummy control circuits having similar operating characteristics to the control circuit. A controller and logic circuit switch on the first and second dummy control circuits and apply an input voltage so the first and second dummy control circuits output first and second output voltages. At a first time, the controller and logic circuit switch off the second dummy control circuit so a leakage current flows through the second dummy control circuit to ground, causing the second output voltage to reduce. Comparison circuitry determines a second time at which, due to the reduction of the second output voltage, a difference between the first and second output voltages is greater than a threshold. Determination circuitry determines the refresh frequency based upon elapsed time between the first and second times.

Abstract: Various aspects of the disclosed technology relate to techniques of determining an across-chip distribution of temperature generated by on-chip devices. Effective thermal conductance and effective thermal capacity for each region of a plurality of regions of a layout design are first extracted. The effective thermal conductance for a region in a metal layer is determined based at least on density information of metal interconnect lines within the region and has components associated with directions of the metal interconnect lines. A thermal circuit is then constructed based on the effective thermal conductance, the effective thermal capacity and heat information of thermal nodes. The heat information of thermal nodes is determined based on an electrical simulation on the integrated circuit associated with the layout design. A thermal simulation is then performed on the thermal circuit to determine temperature information of the thermal nodes.

Abstract: A method, system, and computer program product for controlling power supplied to a processor is disclosed. A voltage regulator is set to a first voltage regulator set point, wherein the first voltage regulator set point provides a first load line for operation of the processor. A change in an operation of the processor from a first operating condition along the first load line to a second operating condition along the first load line is determined. The voltage regulator is the set to a second voltage regulator set point and the processor is operated at a third operating condition on a second load line corresponding to the second voltage regulator set point.

Abstract: Method and sensor observation system (200), for reporting observations to data users (204) based on sensor data collected (2:1) from a network of sensors (202). A first observation report that originates from a sensor in the network, is provided (2:4) to a first data user and a rating with respect to quality of the first observation report is received (2:5) from the first data user. Rating information is then created (2:8) based on the received rating, and a second observation report originating from the same sensor and comprising said rating information is provided (2:10) to a second data user. The comprised rating information thus indicates reliability of the second observation report. Thereby, the second data user is enabled to estimate and use the second observation report depending on its reliability as indicated by the rating information.

Abstract: A system for testing a base station apparatus includes a circuit board frame including a plurality of interfaces for a plurality of testing modules, and a central processing circuitry. The plurality of testing modules is detachably attachable to the interfaces, and each testing module comprises hardware that is configured to connect a determined interface of the base station apparatus and a reprogrammable processing circuitry. The central processing circuitry is configured to detect testing modules attached to the circuit board frame, determine a testing program to execute, and to program reprogrammable processing circuitries of the detected testing modules to execute testing functions of the testing program.

Abstract: A system is provided for powering an optical network terminal, including a power adapter connected to the optical network terminal and configured to power the optical network terminal; and a battery tray, connected to the power adapter, configured to supply auxiliary power to the optical network terminal through the power adapter from one or more batteries contained within the battery tray, wherein the battery tray is configured to allow removal and replacement, at the customer premise, of the one or more batteries.

Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

Abstract: Systems and methods are operable to test a plurality of devices under test (DUTs) communicatively coupled to one of a plurality of switching elements of a DUT controller. An exemplary embodiment identifies a first DUT and a second DUT from among the plurality of DUTs as members of a test group, wherein the first DUT and the second DUT are identified based upon a test schedule defining a plurality of test groupings of members of the plurality of DUTs for concurrent testing; and communicates control instructions to a first switching element coupled to the first DUT and to a second switching element communicatively coupled to the second DUT, wherein the control instructions are configured to actuate the first switching element and the second switching element to communicatively couple the first DUT and the second DUT.

Abstract: A procedure for obtaining noise temperatures of a field effect transistor (FET) embedded on a wafer through an analytical procedure which processes measured noise figure data over transistor's size Pd within a frequency range at constant voltage and current density. The parasitic elements associated with an electrical model of the embedding structures are determined. Then, for each of n=1, 2, . . . N FETs, the scattering parameters and noise figure Fmeas,n are measured, the components of the core model, normalized to the periphery Pd are determined, and the noise contributions of the parasitic components are de-embedded from Fmeas,n. The noise temperatures tgs, tds, and tgd are found by solving the equation 4 ? N i ? G s ? ( F meas , n - 1 ) - y s + ? C T A ? y s - y s + ? T B , n ? T A ? C T C ? T A + ? T B , n + ? y s P d n = A n ? t ds + B n ? t gs + C n ? t gd using at least three values of Fmeas,n and Pd,n.

Abstract: A method of testing a device. The method comprises determining a computational window. The computational window is a time period of device testing activity below an activity threshold. The at least one computational window occurs during the device testing activity. The method further comprises creating and executing a decision tree during the computational window. The decision tree comprises a scheduled test analysis of test results and a selection of test control actions scheduled to execute in response to the test analysis.