Abstract: A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.

Abstract: A detected data processing apparatus includes a selecting unit that calculates mutual correlation between a plurality of groups of detected data acquired from a detecting unit that detects an operational state of a circuit board, and then selects as analysis data the detected data of a group whose value indicating correlation with other groups is smaller than a threshold value set up in advance; and a first calculating unit that calculates a first Mahalanobis distance on a basis of a first Mahalanobis space generated by using the analysis data selected by the selecting unit from the detected data obtained when a normal circuit board is operated and on a basis of the detected data obtained when a circuit board of diagnosis target is operated.

Abstract: A communications system and method for testing components of an aircraft via Ethernet. The communications system may comprise one or more Ethernet links having software and hardware controls for timing, buffering, and messaging, and a dedicated Ethernet line. The Ethernet links may be configured to communicably link sections of a central communication system of the aircraft, each section being part of a separate aircraft component. The Ethernet links may also communicably link the sections with various databases over the Ethernet line. The databases may comprise loadable software, archived testing data, configuration data, and/or diagnostic data. Any of the central communication system sections and the databases may be located at geographically distant locations from each other, such as at separate production sites. The communications system may allow the aircraft components to test each other, or essentially for the aircraft to test itself prior to its components being physically joined together.

Abstract: A continuity testing apparatus includes open/short detection circuits provided for to-be-tested terminals, respectively and configured to determine the presence or absence of at least any one of an open-circuit failure and a short-circuit failure in to-be-tested terminals. Then, the continuity testing apparatus generates detected results of the open/short detection circuits based on the condition of continuity of the to-be-tested terminals having connections to the open/short detection circuits and the detected results from the open/short detection circuits in the preceding stages, and outputs the generated detected results to the open/short detection circuits in the succeeding stages. Further, the continuity testing apparatus determines the condition of continuity based on the output from the open/short detection circuit in the last stage.

Abstract: An integrated circuit with a single-channel input/output (I/O) interface and a multi-channel I/O interface includes functional circuits that operate in different clock domains and a test circuit. For a single-channel I/O interface, the test circuit simulates read/write operations by bypassing the functional circuits and performs electrical characterization of the single-channel I/O interface. For a multi-channel I/O interface, the test circuit configures a plurality of channels of the multi-channel interface in a half-duplex mode and performs electrical characterization using data loop back by bypassing the functional circuits.

Abstract: A system and method uses a measurement control device and a measurement machine to measure pin voltages of electronic components installed in an electronic device. The measurement control device controls a mechanical arm of the measurement machine to move to the pins of the electronic components according to coordinates of the pins. A voltage probe installed on the end of the mechanical arm can measure voltages of the pins automatically.

Abstract: An Analog/mixed signal automatic test system includes a software architecture that creates a virtual composite instruments through novel software dynamic allocation of low level resources. These virtual composite instruments provide backwards and forwards compatibility to a variety of automatic test equipment, known or available on the market. The virtual composite instruments are free from the normal constraints imposed by hardware implementations. Creation of the virtual composite instruments allows a single piece of automatic test equipment system to emulate many implementations of automatic test equipment, providing higher utilization, and therefore a lower cost test solution for device manufacturers. The test instruments are preferably object controls and are preferably instantiated and controlled by the test system server. This allows multiple users to control the tester simultaneously across, for example, the Internet.

Abstract: A platform specific test for computing hardware and method using same, wherein the method supplies a plurality of test procedures, and provides a computing device to be evaluated, where the computing device comprises (M) physical objects. The method identifies, for each value of (i), an (i)th physical object disposed in the computing device. The method then determines, for each value of (i), if the plurality of test procedures comprises one or more test procedures associated with the (i)th physical object. If, for each value of (i), the plurality of test procedures comprises one or more (i)th test procedures associated with the (i)th physical object, then the method adds, as one or more (i)th test procedures, the one or more test procedures associated with the (i)th physical object to a test algorithm, and saves that test algorithm.

Abstract: A method for testing electronic devices that are correspondingly connected to test units includes generating control signals for the electronic devices that are connected to one or more test units selected from the test units. A control unit adds ID codes corresponding to the selected test units to the control signals, and wirelessly transmits the control signals with the ID codes to all of the test units. Each of the test units compares the ID codes added to the control signals with its own stored ID code. When the ID code added to a control signal is in accordance with the ID code stored in one of the test units, the test unit controls the electronic device connected thereto to be turned on and off according to the control signal.

Abstract: Techniques for data gathering in large-scale wireless sensor networks are described. A data collection device receives aggregate data from at least one sensor node of a group of N sensor nodes. The aggregate data includes M weighted sums. Each of the M weighted sums includes a respective sum of N products each of which being a product of a respective coefficient and a sensor reading from a respective one of the N sensor nodes. M and N are positive integers and M is less than N. Computation is performed on the aggregate data to recover sensor readings from the N sensor nodes.

Abstract: A method of developing a statistical model for integrated circuits includes providing a set of test patterns; collecting a set of intra-die data from the set of test patterns; collecting a set of inter-die data from the set of test patterns; generating a total variation sigma (sigma_total) from the set of intra-die data and the set of inter-die data; appointing one of a global variation sigma (sigma_global) and a local variation sigma (sigma_local) as a first sigma, and a remaining one as a second sigma; generating the first sigma from one of the set of intra-data and the set of inter-data; generating the second sigma by removing the first sigma from the sigma_total; generating a corner model for global variations based on sigma_global and the set of inter-die data; and generating a corner model for local variations based on sigma_local and the set of intra-die data.

Abstract: A test system includes a main selector, a first and a second switching connectors, a first and a second sub-selectors, and a processor. The main selector includes a number of first switches, a number of first contacts, and a number of second contacts. Each sub-selector includes a second switch, a third contact, and a fourth contact. The processor sends a first instruction and a second instruction to correspondingly control the main selector and a selected sub-selector.

Abstract: A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.

Abstract: The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam.

Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.

Abstract: An automatic power supply testing system records a preset test order of first and second power supplies with a recording module. The automatic power supply testing system controls a first control unit to connect a first connector connected to the first power supply to a simulation load to test the first power supply according to the preset test order by a determination control module and obtains a first test result. The automatic power supply testing system controls a second control unit to connect a second connector connected to the second power supply to the simulation load to test the second power supply after determining that the first test result is displayed and obtain a second test result. A display module displays the electrical stability of the first and second power supplies.

Abstract: An Arbitrary Waveform Generator has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files. The controller generates this series of test waveforms by direct synthesis to cause each waveform to contain a respective different predetermined amount of Rj, Sj and ISI jitter components. In this way, the Arbitrary Waveform Generator produces a sequence of waveforms incorporating varying amounts of ISI to sweep the ISI jitter components from an initial amount of ISI, for example, zero ISI, and continually increment the amount of ISI to a full unit interval of ISI in predetermined increments, for example, 0.1 UI steps.

Abstract: A test management system is provided that performs tests on integrated circuit test structures. A server may be used to distribute a test recipe to multiple test cells. Each test cell may have multiple test instruments and associated instrument drivers. When performing a test, a test type module may run on a given test cell. The test type module may perform tests by using the instrument drivers to control the test instruments available in the test cell. Users may make test option selections using graphical interface screens such as a test recipe setup screen and a platform engine control screen. A user can select test sites for testing based on which process parameters where used to fabricate the test structures associated with the test sites or other criteria.

Abstract: A semiconductor memory device having a test mode circuit is presented which includes: a mode setting unit, in response to an external command and a first address signal for a mode set, providing a mode register set signal corresponding to predetermined mode setting; and a test mode circuit, in response to the mode register set signal and a second address signal for test enable control in an initial operation, performing test mode enable; the test mode circuit, in response to the mode register set signal and a third address signal for test item selection in the test mode enable state, outputting a test mode item signal; and the test mode circuit, in a subsequent operation, receiving the fed-back test mode item signal to maintain the test mode enable state.

Abstract: According to exemplary methods and systems of the present principles, the location of defective field repairable units (FRUS) of a circuit that have varying sizes or varying numbers of scan cells may be identified by employing tiles including scan cells from different FRUS. A set of test patterns may be scanned through the scan cells such that cells belonging to FRUs within a tile may be concealed while analyzing the response of scan cells in the tile contributed by a different FRU. Further, defective tiles are discoverable at any tile location and in any quantity within a maximal capacity using a compressed signature. In addition, signature registers that process data at a rate that is faster than the scan shift rate of the circuit may be employed during compression to multiply a circuit response by a plurality of components of a compression matrix during one scan shift cycle.

Abstract: Methods of monitoring one or more electronic displays are disclosed. A method may include performing at least one diagnostic operation on at least one electronic display having at least one camera, a display element, and a display server. Further, the method may include transmitting data relating to the at least one diagnostic operation to a network remote from the at least one electronic display. Additionally, the method may include displaying the data within the remote network.

Abstract: A multi-chip package test apparatus is for testing a plurality of semiconductor packages including a plurality of flash memories and an application specific integrated circuit (ASIC) stacked on a single substrate. The multi-chip package test apparatus includes a plurality of test sockets configured to receive the plurality of semiconductor packages, respectively, a plurality of central processing units (CPUs) mounted on a test board and each configured to execute a package test of a respective one of the semiconductor packages received by the plurality of sockets, and a plurality of multiple access dynamic random access memory (DRAM) device operatively interposed between the CPUs and test sockets, respectively, each of the multiple access DRAM devices configured with separate memory areas for access by a respective CPU and a respective ASIC of the semiconductor packages.

Abstract: A reference point-designating section 18b designates two reference points on a measurement object. A reference curve-calculating section 18c calculates a reference curve calculated by approximating an outline of the measurement object based on the reference points. A loss-composing point-calculating section 18d calculates loss-composing points constituting a loss outline formed on the measurement object based on the reference points and the reference curve. A loss size-calculating section 18f measures loss size based on the loss-composing points. Designating two reference points enables loss size measurement, thereby reducing complex operation and improving operability.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.

Abstract: A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.

Abstract: A system, method, and computer program product are provided for testing and re-testing integrated circuits. In use, a group of integrated circuits is tested. In use, before finishing the test, at least one of the integrated circuits of the group is re-tested.

Abstract: Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a predicting section that calculates a predicted value for each test vector by simulating an operation of the device under test, the predicted value indicating a prescribed characteristic value of the device under test to be measured while the device under test is supplied with a test signal corresponding to the test vector; a measuring section that obtains a measured value for each test vector by measuring the prescribed characteristic value of the device under test each time the device under test is supplied with a test vector; and a judging section that judges whether the device under test is defective based on a ratio between the predicted value and the measured value corresponding to each test vector.

Abstract: The testing method of the present invention for testing a plurality of devices under test connected to a test module includes (a) determining combinations of devices under test that can theoretically be measured simultaneously from among the combinations of the plurality of devices under test based on at least the connection relationship between the test module and the plurality of devices under test. The testing method further includes (b) testing the plurality of devices under test by sequentially selecting the combinations of devices under test to be actually measured simultaneously from the combinations determined in (a).

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: The invention concerns a method for determining a calibration value indicating the extent of loss of calibration of a group of three or more sensors in a sensor network, the method involving receiving a plurality of data values captured over a period of time by each of the sensors, determining by a processing unit (404) at least one correlation value associated with each sensor, each correlation value corresponding to the correlation between the data values captured by the associated sensor and the data values captured by at least one other sensor; extracting by a high pass filter (410) a noise component of the correlation values and outputting the calibration value determined based on the difference between the noise component and a reference noise value.

Abstract: An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: A testing system for a portable electronic device includes a sequential control card, a plurality of test devices, and a plurality of switches. The sequential control card provides and outputs command signals according to a predetermined test sequence. The test devices test the portable electronic devices according to the test sequence. The switches are connected between the sequential control card and the corresponding test devices, and are switched on, in order, under the control of the command signal from the sequential control card according to the test sequence to activate the corresponding test devices. The test devices test the portable electronic device according to the predetermined test sequence.

Abstract: A CPU voltage testing system and method uses a parameter storing unit to store a number of VID codes and a plurality of allowable voltage ranges. A number of VID code control signals corresponding to the number of the VID codes are sent to a VID code coding unit to control a voltage converting module to output corresponding voltage signals to a CPU. A voltage collecting unit collects CPU core voltages of the CPU and outputs the collected CPU core voltages to a data processing unit. The data processing unit can determine whether the collected CPU core voltages are within the plurality of allowable voltage ranges via comparing with a number of testing parameters stored in the parameter storing unit.

Abstract: Detecting an anomaly is disclosed. An indication that a computer system monitoring instrument is desired to provide as output a subset of the output data that it would produce if it were to remain on throughout a relevant period with no limit being placed on its output at any point during the relevant period is received. The instrument is configured to provide as output only the desired subset.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract: The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.

Abstract: An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy.

Abstract: Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.

Abstract: A semiconductor apparatus includes a functional block to observe a state of a signal line in the apparatus. The functional block includes a signal transfer section to receive, transmit and output the state of the signal line, and an observation flip-flop to store a state of an input terminal or an output terminal of the signal transfer section.

Abstract: Methods and systems for managing virtual working pages are disclosed. One method includes storing a first set of parameters in a working page within the tested system, where the first set of parameters is used for calibration of the tested system. The method also includes storing a second set of parameters in a virtual working page within an observation system having a plurality of virtual working pages. The method further includes transferring the second set of parameters from the observation system to the tested system. The method also includes storing one or more parameters of the second set of parameters in the working page. A related user interface is also disclosed.

Abstract: A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at least one process component associated with the fabrication of the die and at least one performance component associated with an electrical performance characteristic of the die. At least one of the die is tested. A protocol of the testing is determined based on the associated die health metric.

Abstract: A system for synchronizing multiple measurements across multiple sensors is provided. The system implements an algorithm in combination with highly flexible hardware architecture that generally comprises of multiple sensor inputs correspondingly from multiple sensors, and multiple analog signal conditioning circuits, and an array of switches situated between the sensor inputs and the analog signal conditioning circuits that enable the multiple sensor inputs to be routed to any one of the analog signal conditioning circuits or to any combination of analog signal conditioning circuits simultaneously. The algorithm looks at all configured measurements for all configured sensors to determine which measurements should be performed in parallel. Any measurements that are in common among enabled sensors are performed simultaneously while other measurements consume analog signal conditioning paths as they are available.

Abstract: Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Abstract: An automated processing system that includes providing an intelligent module with a composite connection for transmitting information and configuring the intelligent module within the automated processing system for automatic recognition.

Abstract: Embodiments of the invention provide a data storage device test method and data storage device manufacture method which allow a tester to perform an operation test of plural data storage devices connected thereto in a shorter period of time. In one embodiment, an operation test of each of plural HDDs 81-84 connected to a tester is performed by making plural HDDs 81-84 execute commands received from the tester, wherein, during a waiting period when exchange stops between the tester and, for example, HDD 81 of which operation test is being executed, the tester executes the operation test of another HDD. Such a waiting period occurs, for example, before HDD 81 becomes ready to receive a command, before a data transfer is completed and before HDD 81 becomes ready to receive the subsequent command. By using this waiting period, the tester issues a command to, for example, HDD 82 if the HDD is ready to receive a command or transfers data to the HDD if data transfer is possible.

Abstract: A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.