Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: A device that estimates a positional relationship between loads individually connected through sensors to electric power-supply ends provided in a power distribution network includes a communication unit configured to change a resistance value located between each of electric power-supply ends and a ground terminal of each of sensors and measure a voltage value produced between each of the electric power-supply ends and the ground terminal; and a determination unit configured to acquire voltage values from the two selected sensors from among the sensors after a resistance value of one of the two sensors that has a higher acquired voltage value is changed, calculate a ratio between voltage values acquired before and after the resistance value is changed, and determine that the two sensors are connected to a branch circuit in a same system in the power distribution network, when each ratio about the two sensors is within a specified range.

Abstract: Provided is a distributed test system and method for electrical devices that features bifurcated testing and analysis of test results for electrical devices by aggregating test results from multiple testing systems to a centralized server where analysis of test data is undertaken. The system includes a plurality of testing systems, each of which is configured to operate test software to provide electrical stimuli to devices under test (DUTs) and obtain measured metrics indicative of actual operational characteristics (AOCs) of the DUTs. A decision support system (DSS) is selectively placed in data communication with the plurality of testing systems to receive the measured metrics from each of the plurality of testing systems. The DSS is configured to operate on software and compare desired metrics, indicative of desired operational characteristics (DOCs) of each of the DUTs, with the measured metrics and provide a plurality of operational characteristic determinations (OCDs).

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.

Abstract: The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal associated with each device under test (DUT) is maintained at an integer multiple of the tester timing signal. Additionally, in other embodiments, the timing signal associated with various DUTs is used as a timing reference for other devices.

Abstract: A method, system and computer program product for filtering systematic differences from wafer evaluation parameters provides an efficient visual display and numerical map technique for observing wafer-level process variation. Measurement data is gathered from electronic circuits at multiple positions within multiple regions on one or more wafers and parameters are computed from the measurement data, which may be the measurement data values themselves. The set of parameters is filtered for expected systematic variation by computing a set of normalization values from the set of parameters and normalizing the data according to the normalization values. The normalized parameter set is then either presented in a visual display, e.g., by color mapping, or arranged in a numerical map of parameter value by location.

Abstract: A test apparatus for testing a device under test includes a test module that exchanges signals with the device under test to test the device under test, a test controller that includes a processor and a memory, where the test controller controls the test module, and a network that transfers communication packets between the test module and the test controller. Here, the test controller includes a receiving section that receives an interrupt packet requesting an interrupt to the test controller, from the test module via the network, a memory writing section that writes interrupt information included in the interrupt packet into the memory, and an interrupt notifying section that notifies the processor of the interrupt to cause the processor to reference the interrupt information written into the memory.

Abstract: The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam.

Abstract: A method and system for automatically verifying the quality of multimedia rendering are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of directing a command intended for a first driver to both the first driver and a second driver in parallel as the multimedia application issues the command and in response to a condition indicative of having available data to compare, comparing a first output generated by a first processing unit associated with the first driver and a second output generated by a second processing unit associated with the second driver.

Abstract: A system can test network performance of an electronic device via transmitting a testing file with a first designated name to a number of computers connected to the electronic device, obtaining comparison files from the number of computers after running the testing file, and replacing the names of the comparison files with standard names. The network performance of the electronic device can be confirmed via contents of the comparison files.

Abstract: A connection test apparatus includes a controlling section, controlling each connection test device to switch the operation mode between the first and the second modes such that a first connection test device among the connection test devices is in the first mode and the remaining connection devices are in the second mode, and controlling a signal generating circuit to output the connection test signal; and a judging section judging, on the basis of the response signal that the first connection test device outputs in response to the connection test signal, a state of connection of a first connector connected to the first connection test device and a first net including the first connector among the nets.

Abstract: A method for monitoring an insulation fault in an electric network with at least one electric power system supplying electric power to one or more electric loads, and at least one insulation resistance monitor is provided, wherein the at least one electric power system includes at least one electrical power source, and wherein the at least one insulation resistance monitor monitors an insulation resistance between terminal leads of the at least one electric power source and at least one reference potential. The steps are performed of disconnecting the at least one electric power source from the one or more loads by opening each terminal lead; measuring the insulation resistance between the electric circuit of at least one electrical power source and the reference potential; measuring the insulation resistance for the total electric network; closing the second terminal lead with the first terminal lead open; and measuring the insulation resistance for the total electric network.

Abstract: An integrated circuit is provided, which includes at least one external input, a power supply and a plurality of elementary components, each having at least one internal input and at least one internal output. The circuit further includes at least one test unit having an AND gate, each input of which is connected to an internal output of one of the elementary components and an output of which is connected to the power supply via a resistor.

Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Abstract: A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.

Abstract: A method for testing VLSI circuits comprises a two-pass diagnostic method for testing a circuit wherein a first pass comprises a conventional test flow wherein an ATPG tool generates a set of test patterns and identifies possible faulty nets within the circuit. A second pass focuses on a designated critical subset of the circuit extracted using a method for extracting a subset for failure diagnosis of the tested circuit. A second pass utilizes an extraction algorithm which extracts one or more critical subsets of the circuit in order to obtain more accurate failure diagnosis.

Abstract: Consistent with an example embodiment, there is a signal processing circuit. Linking multiplexing (L-MUX) circuits, link respective pairs of stream processing circuits. Each L-MUX circuit is individually switchable to a normal mode and a replacement mode; in normal mode, it passes a first stream of samples values between the stream processing circuits in the respective pair of the L-MUX circuits; in replacement mode, it supplies successive sample values from a second stream from the communication structure to a receiving one of the stream processing circuits in the respective pair. A control circuit keeps a selectable one of the multiplexing circuits in the replacement mode so the selectable one of the L-MUX circuits passes a stream of successive samples from the second stream to the receiving one of the processing circuits in the respective pair of L-MUX circuits, while keeping at least part of the other L-MUX circuits in the normal mode.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.

Abstract: A multi-function, intelligent, distributed analysis test tool (MFDAT) suitable for performing maintenance on complex, sophisticated electronic systems. MFDAT replaces ordinary test instruments such as spectrum analyzers, oscilloscopes, power meters, frequency counters and digital multimeters with modular virtual test instruments that perform the identical functions but use a single display and human interface. Setup information stored internally allows automatic selection and set up the instruments for a particular test. MFDAT provides a “virtual” system to the technician whereby when a second system under test is unavailable, a previous good reading stored by MFDAT is available for comparison. MFDAT provides three operating modes that allow the operator to develop, modify, or refine test procedures, use the embedded test instruments as they would use standard instruments, or to step through predefined test procedures.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

Abstract: Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Abstract: A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

Abstract: A safety control system includes a plurality of safety control stations connected to a control bus to communicate with each other and with a distributed control system including a plurality of control stations connected to the control bus, wherein each of the plurality of safety control stations has an interface through which each of the plurality of safety control stations is connected to the control bus for transmitting own data of each of the plurality of safety control stations to all other safety control stations by broadcasting at a fixed cycle via the control bus and for receiving by each safety control station transmitted data from all other safety control stations, and wherein the interface implements a safety layer used to generate and diagnose safety information.

Abstract: A system and method for determining the true electrical characteristics of a device. A codec is configured to measure at least one electrical characteristic of a device connected to a jack and to identify the device based on the measured electrical characteristics. An updateable database is populated with application circuit information and a software routine is responsive to the measured electrical characteristic and configured to adjust the electrical characteristics measured by the codec based on the application circuit information in the database.

Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.

Abstract: A method includes receiving measured values for a plurality of electrical test parameters associated with integrated circuit devices on at least one wafer measured prior to completion of the wafer. Values of the electrical test parameters are predicted. The measured values are compared to the predicted values to generate residual values associated with the electrical test parameters. At least one performance metric associated with the devices is generated based on the residual values.

Abstract: Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

Abstract: There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.

Abstract: An identification system and method for recognizing a device as one of a plurality of different types of devices connected to at least one terminal of an information handling system includes supplying a test signal to a device in a test mode; measuring an electrical characteristic of the device in response to the test signal being applied to the device in the test mode; and matching a representation of the electrical characteristic of the device with representations of the electrical characteristics of the plurality of devices for recognizing the device connected to the terminal as one of the plurality of different devices.

Abstract: A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.

Abstract: System and method for carrying out a process on an integrated circuit. The method includes reading a data key including subkeys, determining a process parameter set using a parameter directory in a manner dependent on the data key read in, and setting the parameters required for the process in accordance with the process parameter set determined. The parameter directory includes rule keys each having subkeys, which are each assigned predeterminable values from a plurality of values, and at least one subkey is assigned a wildcard, and a plurality of process parameter sets each respectively assigned at least one rule key. The step of determining a parameter set includes comparing the data key read in with the rule keys stored in the parameter directory, determining the rule key(s) whose subkeys match those of the data key read in, and outputting the process parameter set(s) assigned to the rule key(s) determined.

Abstract: This invention relates to safety instrumented systems (“SIS”) for monitoring and controlling chemical and other industrial process field devices, and that are responsive to signals for the emergency shutdown of the process or system. The patent will significantly improve the reliability of communications within an emergency shutdown system, reduce unwanted trips, and adapt to process conditions by failing to a safe mode in dynamic conditions that are not considered by prior art logic solvers.

Abstract: A method and system for measuring the input (loading) impedance of measurement systems using a test fixture. This is done by first measuring the characteristics of an unloaded test fixture to obtain scattering parameters of the test fixture and using a splitting algorithm to calculate the scattering parameters of each transmission line leg of the test fixture. The test fixture is then measured with a measurement system attached. The test fixture effects defined by the scattering parameters are then removed from the measurement to yield the scattering parameters of the measurement system alone (measurement system effects).

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the lines of wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals. The connection section may include a performance board to which the device under test is mounted, where the lines of wiring are connected with each other on the performance board.

Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a second reference integrated circuit device that provides flexibility in testing, allowing only the input to a first reference integrated circuit device of an application system to be tapped and not necessarily both input to and output from the first reference integrated circuit device to be tapped. In some embodiments, the input to the first reference integrated circuit device may be subsequently modified by a controller.

Abstract: Methods for monitoring process drift using plasma characteristics are provided. In one embodiment, a method for monitoring process drift using plasma characteristics includes obtaining metrics of current and voltage information of a first waveform coupled to a plasma during a plasma process formed on a substrate, obtaining metrics of current and voltage information of a second waveform coupled to the plasma during the plasma process formed on the substrate, the first and second waveforms having different frequencies, determining at least one characteristic of the plasma using the metrics obtained from each different frequency waveform, and adjusting the plasma process in response to the determined at least one characteristic of the plasma.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A system, method, and computer program product are provided for testing and re-testing integrated circuits. In use, a group of integrated circuits is tested. In use, before finishing the test, at least one of the integrated circuits of the group is re-tested.

Abstract: The invention provides an apparatus for testing an integrated circuits on devices including a plurality of electrical subassemblies including a plurality of pattern generator, driver, and power boards divided into physical zones with each physical zone including one pattern generator board, at least one driver board, and at least one power board connected to one another; and a configuration file having information representing flow of current through the electrical subassemblies connected to one another in an interconnection scheme, wherein the electrical subassemblies are organized into at least one logical zone, and wherein the logical zone comprises a plurality of pattern generators.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A method includes defining a hierarchy of test routines in a test program for testing integrated circuit devices. A first device is tested at a first screening level in the hierarchy. The first device is tested at a second detailed level in the hierarchy responsive to the first device failing the testing at the first screening level.

Abstract: In the present invention, substrates in a plurality of lots are successively processed in a coating and developing treatment system, and line width measurement is performed for some of substrates of the substrate which have been through processing in each lot. The line width measurement of two successive lots is performed such that the last line width measurement in the previous lot of the two successive lots has been completed at the time of completion of processing of a substrate which is first subjected to the line width measurement in the subsequent lot. According to the present invention, the measurement of product substrates can be performed without decreasing the throughput of the product substrates.

Abstract: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of generalized commands that conform to a command protocol. The BIST controller is configured to send the set of generalized commands to a sequencer.

Abstract: A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the “LUT delay chain”), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

Abstract: A novel method for testing a communications circuit is disclosed. The method includes the following steps: (a) connecting an internal balanced circuit to a well-balanced resistor network; (b) measuring a first plurality of real and imaginary components of the voltages with the internal balanced circuit connected to the well-balanced resistor network; (c) calculating an error for the internal balanced circuit based on the first plurality of voltages; (d) connecting the internal balanced circuit to the communications circuit; (e) measuring a second plurality of real and imaginary components of the voltages with the internal balanced circuit connected to the communications circuit; and (f) calculating a corrected balance for the communications circuit based on the second plurality of voltages and the error for the internal balanced resistor network. A novel device and software program that incorporates this novel method are also disclosed.

Abstract: A testing apparatus includes one or more trace banks. Each trace bank includes (1) an input switch operable to couple an input port to one of multiple output ports, (2) an output switch operable to couple one of multiple input ports to one output port, and (3) transmission lines of different lengths coupled between the output ports of the input switch and the input ports of the output switch. The trace banks can be cascaded using cables to connect their output and input ports. The input and output switches in the trace banks are controlled to provide a transmission path of the desired length.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.